JP2012238898A - Wide bandgap semiconductor vertical mosfet - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high voltage resistant vertical MOSFET which, even if it is a wide bandgap semiconductor vertical MOSFET, features low on-resistance and high reliability.SOLUTION: There is provided a MOSFET, composed of a wide bandgap semiconductor and having an active part and a voltage resistant structure part disposed on the periphery thereof, which comprises an ndrift layer 3 and a p base layer 4 on one side of an nsemiconductor substrate 1 and an nsource layer 5 placed inside the active part in that order. The MOSFET further comprises a trench 100 which, in the active part, extends from the surface of the nsource layer 5 to reach the ndrift layer 3, and, in the voltage resistant structure part, extends from the p base layer 4 on the outermost surface to reach the ndrift layer 3, a p-type channel formation layer 6 which covers the side wall of the trench, and a gate electrode which fills the trench including the surface of the p-type channel formation layer. A gate electrode 8 inside the voltage resistant structure part is composed to be in a potentially floating state, while a gate electrode 8 on the outermost periphery is conductively connected to an nstopper region 16.

Description

The present invention relates to the vertical a MOSFET T, in particular (hereinafter referred to as SiC) silicon carbide or gallium nitride (hereinafter referred to as GaN) and about 3eV bandgap typified by, wider than the silicon semiconductor 1.08eV A wide band gap semiconductor is used as a constituent material of a main semiconductor substrate.

  Conventionally, so-called power devices that handle large electric power have been manufactured mainly using silicon semiconductors. In order to enable a large current capacity, a power device is often configured to allow current to flow in the longitudinal direction (thickness direction) between both main surfaces of a chip. 4 and 5 are sectional views of a vertical MOSFET which is a typical conventional power device. The vertical MOSFET shown in FIG. 4 has a so-called planar gate structure in which the gate electrode 23 and the gate insulating film 24 immediately below the gate electrode 23 are formed in a plane parallel to the main surface of the semiconductor substrate. The MOS channel (inversion layer) is formed on the surface of the p well 25 immediately below the gate electrode 23 and the gate insulating film 24.

When this vertical MOSFET is turned on when an ON signal equal to or higher than the threshold voltage is input to the gate electrode 23, the vertical MOSFET passes through an n channel (not shown) formed as an inversion layer on the surface of the p-well region 25 immediately below the gate insulating film 24. The main current flows from the n ⁺ semiconductor substrate 20, the n buffer layer 21, and the n ⁻ drift layer 22, which are the side regions, to the source region 28. This MOSFET has a structure in which the main current is cut off by turning off the input signal to the gate electrode, and the depletion layer spreads around the pn junction between the n ⁻ drift layer 22 and the p well region 25 to maintain the off voltage. Can be used for switching. The n buffer layer 21 can reduce the thickness of the n ⁻ drift layer 22, which is a high resistance region, while maintaining the breakdown voltage by suppressing the extension of the depletion layer from the pn junction when an off high voltage is applied. This is a layer having the effect of reducing the on-voltage. Reference numeral 20 denotes an n ⁺ semiconductor substrate (substrate). A drain electrode 29 is formed on the back surface of the semiconductor substrate 20 by ohmic contact. Further, the surface side is covered with an interlayer insulating film 30 for ensuring insulation from the gate electrode 23, and directly on the surface of the n ⁺ source region 28 and on the surface of the p well region 25 with a high impurity concentration. Source electrodes 27 are formed in common contact with each other through the p ⁺ region 26. Since the planar gate structure of the vertical MOSFET described above is a structure arranged in a planar shape on the surface of the semiconductor substrate, there is an advantage that it is easy to manufacture.

On the other hand, the MOSFET shown in the cross-sectional view of FIG. 5 is called a trench MOSFET because it has a so-called trench gate structure in which a gate structure is formed inside a concave trench 51. The trench gate structure is more complex than the planar gate structure, and the number of processes is increased accordingly. However, since the trench gate structure can greatly increase the integration density by miniaturizing the pattern of the device unit formed in the active part where the main current flows on the substrate surface, it is an excellent device with low on-resistance. It is easy to obtain characteristics and has been widely adopted in recent years. In this trench type MOSFET, the constituent elements described below other than the trench gate structure have the same functions as those of the vertical MOSFET of the planar gate structure shown in FIG. Omit the explanation. The constituent elements include, for example, a high impurity concentration n-type semiconductor substrate 40, an n-type high impurity concentration buffer layer 41, an n ⁻ drift region 42, a gate electrode 43, a gate oxide film 44, a p well region 45, a high impurity concentration p. ^{A +} region 46, a source electrode 47, an n ⁺ source region 48, an interlayer insulating film 50, a drain electrode 49, and the like.

  However, in power devices such as vertical MOSFETs using silicon semiconductors, for example, the device unit pattern on the semiconductor substrate surface of trench MOSFETs can be miniaturized to the limit by using LSI microfabrication technology. Therefore, the improvement of device characteristics is almost approaching the limit. Attempts have therefore been made to break through this limit with semiconductor materials having a wider band gap than silicon, such as SiC and GaN. Since these semiconductor materials have a maximum breakdown electric field that is almost an order of magnitude higher than that of silicon, when this semiconductor material is used in a power device, the resistance of the element is expected to be 1/100 or less. Therefore, by using a semiconductor material having a wide band gap such as SiC or GaN and adopting a process similar to that of silicon, the MOSFET having the planar gate structure of FIG. 4 or the trench gate structure of FIG. It has been broken.

  Known documents relating to improvements in power devices such as MOSFETs using wide bandgap semiconductors such as SiC and GaN include trenches shallower than the drift layer, and high impurity concentration n-type regions and trenches deeper than the drift layer at the bottom of the trench. An SiC-trench MOSFET that can achieve both low on-resistance and high breakdown voltage by forming a SiC-n type sidewall layer along the side wall has been disclosed (Patent Document 1).

  Further, it is known that the SiC-MOSFET is a SiC-MOSFET that obtains a high breakdown voltage and low loss by providing a trench reaching the drift layer and a p-type SiC semiconductor layer serving as a channel formation region on the trench side wall. (Patent Documents 2 and 3).

  Furthermore, there is a known document regarding a method of leaving a p-type epitaxial layer formed on the inner surface of a groove as a channel formation region only on the side surface of the groove by RIE etching, although it is a silicon MOSFET (Patent Document 4).

JP 2001-77358 A (summary, FIG. 1) Japanese Patent No. 3415340 (paragraph 0029, FIGS. 4 to 6) Japanese Patent No. 3610721 (paragraph 0043, FIG. 13) Japanese Patent Laid-Open No. 2-91976 (FIGS. 1 (c) and (d))

  However, compared to silicon semiconductors, SiC and GaN as semiconductor materials have a wider band gap, but the restrictions on the device manufacturing process are extremely large and the degree of freedom is small. Usually, in the manufacturing process of a silicon device, impurities of donor and acceptor are introduced by ion implantation, then activated by a heat treatment at about 1000 ° C., and subsequently subjected to a thermal diffusion treatment to obtain a desired depth required from the element design. The diffusion layer can be formed, and most pn junctions in the device structure are easily formed by this method.

However, in SiC and GaN, even if a donor or acceptor is introduced into a semiconductor substrate by ions, it is not easy to electrically activate it by a subsequent heat treatment as compared to a silicon semiconductor. For example, in order to increase the activation rate of SiC, it is necessary to activate it by performing a heat treatment at a high temperature of 1500 ° C. The activation temperature of 1500 ° C. or higher is a temperature that exceeds the heat resistance temperature of the Si ₃ N ₄ film or the SiO ₂ film normally used as a gate oxide film or a passivation film. For this reason, in a manufacturing process using a SiC semiconductor, it is necessary to perform this high-temperature heat treatment before forming these films. As described above, in the manufacturing process of the SiC semiconductor, although there are limitations associated with the required extremely high temperature process, the ion implantation process can be used.

  However, in SiC, interface states are very likely to be generated at the MOS interface, and the mobility of electrons in the channel is very low. Therefore, a device capable of sufficiently extracting the excellent characteristics of the substrate crystal is manufactured. Not easy to do.

  On the other hand, there are some attempts in GaN, but in general, it is very difficult to introduce both n-type and p-type by ion implantation, and few successful examples are known. For this reason, it is a problem in the manufacturing process that it is necessary to form semiconductor layers and regions only by epitaxial growth.

However, in GaN, it has been reported that the electron mobility in the MOS channel exceeds 100 cm ² / Vs with respect to the interface state of the MOS interface, and the characteristics superior to SiC are obtained for this MOS interface. Cheap. As described above, both SiC and GaN have various problems in manufacturing devices, and it is not easy to overcome them.

  In addition, the gallium nitride-based compound semiconductor substrate has a thermal expansion coefficient different by about 50% and a lattice mismatch of about 15% compared to the silicon semiconductor substrate. There is also a problem of warping when laminated on a silicon substrate. Therefore, it is difficult to handle the wafer, and even in the case of a chip, it is said that soldering is difficult due to warpage. In addition, since the activation rate of the p-type dopant is very low in the GaN semiconductor, it is difficult to accurately control the impurity concentration, and it is difficult to design a breakdown voltage structure like a known SiC semiconductor. is there.

The present invention has been made in view of the above points, and the object of the present invention is a vertical MOSFET whose main constituent material is a wide band gap semiconductor of about 3 eV having a wider band gap than a silicon semiconductor. is to provide a low on-resistance, a wide band gap semiconductor vertical a MOSFET T to high-voltage vertical MOSFET high reliability can be obtained.

According to the first aspect of the present invention, a wide band gap semiconductor having a band gap of 3 eV or more is a main constituent material, and an active portion through which a main current flows and a withstand voltage disposed around the active portion. A one-conductivity type drift layer, a low-concentration one-conductivity type base layer, and a one-conductivity type source layer disposed in the active part in this order The active portion reaches the one conductivity type drift layer from the one conductivity type source layer surface, and the breakdown voltage structure portion reaches the one conductivity type drift layer from the other conductivity type base layer on the outermost surface; An other conductivity type channel forming layer covering the trench sidewall, a gate oxide film covering the inner surface of the trench including the surface of the other conductivity type channel forming layer, and a gate electrode filling the trench, A different potentials at different electrode and the gate electrode of the gate electrode the voltage withstanding structure of the active portion, the gate electrode in the voltage withstanding structure portion is configured potentially floating state, the opposite conductivity type channel forming layer is the other One conductivity type region having a lower impurity concentration than the conductivity type base layer and serving as a depletion layer stopper region is provided at the outermost periphery of the breakdown voltage structure portion, and the outermost gate electrode among the gate electrodes filling the breakdown voltage structure portion is The object of the present invention is achieved by using a wide band gap semiconductor vertical MOSFET that is conductively connected to the surface of the stopper region on one side of the semiconductor substrate .

According to the second aspect of the present invention, a wide band gap semiconductor having a band gap of 3 eV or more is a main constituent material, and an active portion through which a main current flows and a withstand voltage disposed around the active portion. A one-conductivity type drift layer, a low-concentration one-conductivity type base layer, and a one-conductivity type source layer disposed in the active part in this order The active portion reaches the one conductivity type drift layer from the one conductivity type source layer surface, and the breakdown voltage structure portion reaches the one conductivity type drift layer from the other conductivity type base layer on the outermost surface; An other conductivity type channel forming layer covering the trench sidewall, a gate oxide film covering the inner surface of the trench including the surface of the other conductivity type channel forming layer, and a gate electrode filling the trench, The gate electrode of the active part and the gate electrode of the breakdown voltage structure part have different potentials in different electrodes, and the gate electrode filling the breakdown voltage structure part is conductively connected to the surface of the other conductivity type base region on one side of the semiconductor substrate. The other-conductivity-type channel forming layer has a lower impurity concentration than the other-conductivity-type base layer, and a one-conductivity-type region serving as a depletion layer stopper region is provided on the outermost periphery of the withstand-voltage structure, A wide bandgap semiconductor vertical MOSFET in which the outermost gate electrode among the gate electrodes filling the conductive layer is conductively connected to the surface of the stopper region on one side of the semiconductor substrate .

According to a third aspect of the present invention, the gate electrode filling the breakdown voltage structure portion is conductively connected to the surface of the other conductivity type base region adjacent to the active portion side on one surface side of the semiconductor substrate. The wide bandgap semiconductor vertical MOSFET according to claim 2 of the present invention.

According to a fourth aspect of the present invention, the gate electrode in the breakdown voltage structure portion is electrically connected to the surface of the other conductivity type base region adjacent to the one surface side of the semiconductor substrate opposite to the active portion. The wide bandgap semiconductor vertical MOSFET according to claim 2 connected thereto.

According to the present invention, even with a vertical MOSFET whose main constituent material is a wide band gap semiconductor of about 3 eV having a wider band gap than that of a silicon semiconductor, a low on-resistance and highly reliable high breakdown voltage vertical MOSFET can be obtained. it is possible to provide a wide band gap semiconductor vertical MOSFE T to be.

It is sectional drawing of the semiconductor substrate which shows the manufacturing process of the vertical MOSFET concerning this invention (the 1). It is sectional drawing of the semiconductor substrate which shows the manufacturing process of the vertical MOSFET concerning this invention (the 2). It is sectional drawing of the semiconductor substrate which shows the manufacturing process of the vertical MOSFET concerning this invention (the 3). 1 is a cross-sectional view of a semiconductor substrate showing a peripheral voltage-resistant structure surrounding an active part of a wide bandgap semiconductor vertical MOSFET according to the present invention. It is sectional drawing of the semiconductor substrate which shows a different pressure | voltage resistant structure part concerning this invention. It is sectional drawing of the semiconductor substrate which shows the planar gate structure of the conventional vertical MOSFET of silicon. It is sectional drawing of the semiconductor substrate which shows the trench gate structure of the conventional vertical MOSFET of silicon. It is sectional drawing (the 1) of the semiconductor substrate which shows the surrounding pressure | voltage resistant structure part surrounding the active part of the wide band gap semiconductor vertical MOSFET concerning this invention. It is sectional drawing (the 2) of a semiconductor substrate which shows the surrounding pressure | voltage resistant structure part surrounding the active part of the wide band gap semiconductor vertical MOSFET concerning this invention. FIG. 6 is a cross-sectional view (No. 3) of a semiconductor substrate showing a peripheral breakdown voltage structure surrounding an active portion of a wide bandgap semiconductor vertical MOSFET according to the present invention. FIG. 6 is a sectional view (No. 4) of a semiconductor substrate showing a peripheral breakdown voltage structure surrounding an active portion of a wide bandgap semiconductor vertical MOSFET according to the present invention.

Exemplary embodiments of a vertical MOSFET using a wide bandgap semiconductor and a method of manufacturing the same according to the present invention will be described below in detail with reference to the accompanying drawings. In the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. Symbols + and ⁻ such as n ⁺ and n ⁻ represent a relatively higher impurity concentration and a lower impurity concentration, respectively, in comparison with an n-type impurity concentration without these symbols. One conductivity type is referred to as n-type, and the other conductivity type is referred to as p-type. Further, the present invention is not limited only to the description of the examples described below.

  1A to 1C are cross-sectional views of a semiconductor substrate showing a method for manufacturing a vertical MOSFET using a wide band gap semiconductor according to the present invention for each manufacturing process. FIG. 2 is a cross-sectional view of a semiconductor substrate showing a breakdown voltage structure portion of a vertical MOSFET according to the present invention. FIG. 3 is a cross-sectional view of a semiconductor substrate showing different breakdown voltage structure portions of a vertical MOSFET according to the present invention. FIG. 6 is a cross-sectional view of a semiconductor substrate showing a guard ring configuration in a breakdown voltage structure portion of a vertical MOSFET according to the present invention (part 1). FIG. 7 is a sectional view of a semiconductor substrate showing a guard ring configuration in the breakdown voltage structure portion of the vertical MOSFET according to the present invention (part 2). FIG. 8 is a cross-sectional view of a semiconductor substrate showing a guard ring configuration in the breakdown voltage structure portion of the vertical MOSFET according to the present invention (part 3). FIG. 9 is a sectional view of a semiconductor substrate showing a guard ring configuration in the breakdown voltage structure portion of the vertical MOSFET according to the present invention (part 4).

In FIGS. 1-1 to 1-3, (a) to (g) sequentially show the manufacturing process of the vertical MOSFET according to the present invention. In (a), the n-type high impurity concentration wide bandgap semiconductor material may be either SiC or GaN, but here, the following explanation will be made on SiC. In order to facilitate understanding, the following manufacturing process is divided into an active part through which the main current of the MOSFET flows and a peripheral part surrounding the active part, and a breakdown voltage structure for ensuring the breakdown voltage reliability. First, an n-type high impurity concentration buffer layer 2 formed by SiC epitaxial growth on the SiC-n ⁺ semiconductor substrate 1, and further an n ⁻ drift layer 3 thereon can maintain a breakdown voltage by SiC epitaxial growth. The p base layer 4 is formed to have a predetermined impurity concentration and thickness by SiC epitaxial growth or ion implantation thereon, and finally the high impurity concentration n ⁺ source layer 5 is formed. Are sequentially formed by SiC epitaxial growth or ion implantation. However, when a GaN semiconductor is used, the ion implantation method is difficult, so that it is preferably formed by epitaxial growth. Each layer may take different values depending on the design. For example, the n ⁺ buffer layer 2 preferably has an impurity concentration of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ and a thickness of 1 to 5 μm. The n ⁻ drift layer 3 preferably has an impurity concentration of 5 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ and a thickness of 5 to ¹⁵ μm. The p base layer 4 has an impurity concentration of 5 × 10 ¹⁷ to 1 × 10 ²¹ cm ⁻³ and a thickness of about 0.5 to 2 μm. The n ⁺ source layer 5 has an impurity concentration of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ and preferably has a thickness of about 0.2 to 1 μm. This step is the first step in the production method according to the present invention.

  In (b), in order to form a trench gate structure portion, first, trench 100 is formed by etching into a trench shape by a known technique such as anisotropic dry etching, for example, RIE (Reactive Ion Etching) etching method. . The depth of the trench 100 also varies depending on the design, but it is necessary to make it deeper than at least the p base layer 4. The surface width of the trench 100 is about 0.5 to 2 μm. This step is the second step in the production method according to the present invention.

In (c), a p-type SiC epitaxial semiconductor layer 6a having an impurity concentration and a thickness controlled to a predetermined value is formed on the entire surface of the substrate including the trench 100. The p-type SiC epitaxial semiconductor layer 6a includes a p-type channel forming layer 6 which is a trench side wall portion where a MOS channel (inversion layer) is to be formed. The impurity concentration of the p-type channel formation layer 6 is about 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ and the thickness is about 0.2 to 1 μm. The impurity concentration of the p-type channel formation layer 6 is preferably lower than the impurity concentration of the p base layer 4. In the case of a SiC semiconductor, the p-type channel formation layer 6 can be formed by an ion implantation method. In the case of a GaN semiconductor, the p-type channel formation layer 6 is preferably formed by an epitaxial growth method. In the present invention, since the MOS channel (inversion layer) is formed as the p-type channel formation layer 6 different from the p base layer 4, the impurity concentration can be different from that of the p base layer 4, and the channel controllability is taken into consideration. There is an advantage that the selection range for selecting the impurity concentration is wide. For example, when the concentration is lower than that of the p base layer 4 as described above, the gate threshold voltage can be reduced. When the channel (inversion layer) is formed directly on the side wall surface of the p base layer 4 without providing the p-type channel formation layer 6 according to the present invention, the impurity concentration of the p base layer 4 is reduced in order to reduce the gate threshold voltage. If it is lowered, the depletion layer at the time of off tends to spread to the p base layer 4 and the width of the p base layer 4 needs to be widened. Then, there arises a problem that the channel width (length in the current direction) is increased and the channel resistance is increased. According to the present invention, the impurity concentration of the p base layer can be increased and the thickness can be reduced regardless of the gate threshold voltage, so that the problem related to the channel resistance can be avoided.

  In (d), anisotropic dry etching similar to that described above is used to remove the layer portion of the p-type SiC epitaxial semiconductor layer 6a formed in (c) above that is parallel to the main surface of the substrate. Only the p-type channel forming layer 6 on the side wall portion of 100 is left.

In (e), a SiO ₂ film or a Si ₃ N ₄ film to be the gate insulating film 7 is formed on the surface by thermal oxidation or CVD. In SiC, a SiO ₂ film can be formed by thermal oxidation.

  In (f), in order to form the gate electrode 8, the gate electrode material is filled and formed by etching into a gate pattern. As the gate electrode material, conductive polysilicon is usually used. Preferably, the trench 100 should be completely filled. If the film is not completely buried, a groove remains on the surface, so that a process trouble is likely to occur, for example, a film is not normally applied when a photoresist is applied in a subsequent process. The steps in the description from (c) to (f) are defined as the third step in the production method according to the present invention.

In (g), a source electrode 10 that is in ohmic contact with the surfaces of the p base region 4 and the n ⁺ source region 5 and a drain electrode 9 that is in ohmic contact with the back surface of the SiC-n ⁺ semiconductor substrate 1 are formed. For these metal electrodes, a laminated film of Ni, Ti, Al or the like is used.

  In the vertical MOSFET according to the present invention thus formed, a MOS channel (inversion layer) is formed on the surface of the p-type channel formation layer 6 on the side wall of the trench. Since the gate threshold voltage of the MOSFET depends on the impurity concentration of the p-type channel formation layer 6, the merit of being able to control the impurity concentration of the p-type channel formation layer 6 by a manufacturing process is great. It is also advantageous that the channel length can be determined not by the thickness of the p base layer 4 but by the depth of the trench 100. As a result, a MOSFET with very good controllability can be formed. In addition, this method has a feature that the p-type channel formation layer 6 can be formed as close as possible to the corner portion at the bottom of the trench 100, and the breakdown voltage is hardly affected by the depth of the trench 100 or the like. Therefore, it is possible to alleviate the application of a large electric field to the gate insulating film 7 at the trench corner portion.

2, 6, 7, 8, and 9, the peripheral breakdown voltage structure according to the present invention surrounding the active portion of the element for maintaining a large off-voltage will be described. Although the description of the manufacturing method is not much different from that of FIG. 1, it is preferable that the high impurity concentration n ⁺ type source layer 5 on the outermost surface of the substrate is not present in the peripheral breakdown voltage structure according to the present invention. ^In order to remove the ⁺ type source layer 5, the n ⁺ type source layer 5 is dry-etched only in the peripheral breakdown voltage structure portion between the manufacturing steps of the first step described in (a) and the second step described in (b). Add a process to be removed by such processing. In this withstand voltage structure portion, as shown in FIG. 6, the p-type island region 14 formed simultaneously with the p base layer 4 in the active portion is divided into island shapes by the trench 101 in the withstand voltage structure portion, and serves as a guard ring. Will be fulfilled. This guard ring includes a p-type channel formation layer 6, a gate insulating film 7, and a gate electrode 8 in the trench 101 formed at the same time as the trench 100 in the active portion, like the trench 100 in the active portion. It has a potential different from that of the gate electrode 8, is not connected to any external electrode terminal, and is in a floating state in terms of potential. That is, at least the gate electrode in the active part and the gate electrode in the breakdown voltage structure part are not conductively connected. By doing so, the gate electrode 8 in the breakdown voltage structure portion is fixed in potential by capacitive coupling with the p-channel forming layer 6 and the depletion layer extends outward. The guard ring has a function of maintaining the off breakdown voltage with high reliability by sharing a large voltage applied when the MOSFET is turned off. From the viewpoint of withstand voltage design, the design withstand voltage can be changed by changing the width of the p-type island region 14 (width in the direction parallel to the main surface of the substrate) and the number of the trenches 101. It is preferable to add a polyimide film or Si ₃ N ₄ film (not shown) to the outermost surface of the substrate for preventing discharge.

From the viewpoint of stabilizing the potential floating state of the gate electrode 8 in the guard ring and controlling the extension of the depletion layer due to the off voltage, a short-circuit electrode between the surface of the gate electrode 8 and the surface of the p-type island region 14 (FIG. 7). The reference numeral 13 in FIG. 8 and the numeral 15 in FIG. 8 are preferably conductively connected. Further, a short-circuit electrode (see FIGS. 8 and 9) is also provided between the surface of the gate electrode 8 and the n ⁺ -type stopper region 16 of the depletion layer so that the depletion layer does not extend so much as to reach the outermost cut surface of the device chip. The channel stopper is preferably conductively connected according to reference numeral 12). In FIG. 7, the gate electrode 8 in the breakdown voltage structure is conductively connected to the p-type channel forming layer 6 on the active part side (inner side). For this reason, the gate electrode 8 in the breakdown voltage structure and the inner p-type channel formation layer 6 have the same potential, so that the depletion layer tends to extend outward. This is effective when the passivation film has a lot of positive charges and the depletion layer hardly extends on the surface. In FIG. 8, it is conductively connected to the p-type channel forming layer 6 outside the gate electrode 8 in the breakdown voltage structure. For this reason, it becomes difficult for the depletion layer to extend outward. This is effective when the passivation film has a lot of negative charges and the depletion layer tends to extend on the surface.

FIG. 3 shows a cross-sectional structure of another surrounding pressure-resistant structure. In this example, the breakdown voltage is maintained by making the breakdown voltage structure a mesa shape. That is, a mesa region 11 deeper than the low impurity concentration n ⁻ drift layer 3 is formed, and a passivation film (not shown) made of a combination of SiO ₂ film, Si ₃ N ₄ film, polyimide film, etc. is formed on the surface. In this way, the breakdown voltage is maintained. The inclination angle of the mesa can be appropriately selected from a state perpendicular to the main surface of the substrate from a negative bevel angle as shown in FIG. In the manufacturing process of the vertical MOSFET having the mesa bevel structure, in addition to the manufacturing steps shown in FIGS. 1-1 to 1-3, a deeper mesa region 11 is formed in the step (g) and after that step. An etching process for forming this is added.

As described above, the wide band gap semiconductor vertical a MOSFET T according to the present invention is useful for a power semiconductor device such as those used in power supplies and automotive igniter of machinery power conversion apparatus and for various industries such as the inverter is there.

DESCRIPTION OF SYMBOLS 1 Wide band gap n ⁺ Semiconductor substrate 2 High impurity concentration n ⁺ Buffer layer 3 Low impurity concentration n ⁻ Drift layer 4 p Base layer 5 High impurity concentration n ⁺ Source layer 6 p-type channel formation layer 7 Gate insulating film 8 Gate electrode 9 Drain electrode 10 Source electrode 11 Mesa region 12 Short-circuit electrode 13 Short-circuit electrode 14 P-type island region 15 Short-circuit electrode 16 Stopper region 100 Trench 101 Trench.

Claims (4)

A wide-bandgap semiconductor having a band gap of 3 eV or more as a main constituent material, an active part through which a main current flows, and a breakdown voltage structure part arranged around the active part, and a one-conductivity-type semiconductor with a high impurity concentration A one conductivity type drift layer having a low impurity concentration, another conductivity type base layer, and a one conductivity type source layer disposed in the active part are sequentially provided on one surface of the substrate, and the active part includes a surface of the one conductivity type source layer from the surface of the one conductivity type source layer. A trench that reaches one conductivity type drift layer and reaches the one conductivity type drift layer from the other conductivity type base layer on the outermost surface in the breakdown voltage structure portion, another conductivity type channel formation layer that covers the trench sidewall, and the other conductivity A gate oxide film covering the inner surface of the trench including the surface of the type channel forming layer and a gate electrode filling the trench, the gate electrode of the active part and the gate of the breakdown voltage structure part A different potentials and poles at different electrodes, the gate electrode in the voltage withstanding structure portion is configured potentially floating state, the opposite conductivity type channel forming layer is a low impurity concentration than said other conductivity type base layer, the One conductivity type region serving as a stopper region for the depletion layer is provided on the outermost periphery of the breakdown voltage structure portion, and the outermost gate electrode of the gate electrode filling the breakdown voltage structure portion is on one surface side of the semiconductor substrate and the surface of the stopper region A wide bandgap semiconductor vertical MOSFET characterized by being conductively connected to . A wide-bandgap semiconductor having a band gap of 3 eV or more as a main constituent material, an active part through which a main current flows, and a breakdown voltage structure part arranged around the active part, and a one-conductivity-type semiconductor with a high impurity concentration A one conductivity type drift layer having a low impurity concentration, another conductivity type base layer, and a one conductivity type source layer disposed in the active part are sequentially provided on one surface of the substrate, and the active part includes a surface of the one conductivity type source layer from the surface of the one conductivity type source layer. A trench that reaches one conductivity type drift layer and reaches the one conductivity type drift layer from the other conductivity type base layer on the outermost surface in the breakdown voltage structure portion, another conductivity type channel formation layer that covers the trench sidewall, and the other conductivity A gate oxide film covering the inner surface of the trench including the surface of the type channel forming layer and a gate electrode filling the trench, the gate electrode of the active part and the gate of the breakdown voltage structure part The gate electrode filling the withstand voltage structure portion is electrically connected to the surface of the other conductivity type base region on one surface side of the semiconductor substrate, and the other conductivity type channel forming layer is the other electrode. One conductivity type region having a lower impurity concentration than the conductivity type base layer and serving as a depletion layer stopper region is provided at the outermost periphery of the breakdown voltage structure portion, and the outermost gate electrode among the gate electrodes filling the breakdown voltage structure portion is A wide bandgap semiconductor vertical MOSFET characterized in that it is conductively connected to the surface of the stopper region on one side of the semiconductor substrate . 3. The wide band gap according to claim 2, wherein the gate electrode filling the breakdown voltage structure portion is conductively connected to the surface of the other conductivity type base region adjacent to the active portion side on one side of the semiconductor substrate. Semiconductor vertical MOSFET. Wide of claim 2, wherein the gate electrode in the voltage withstanding structure portion is electrically connected to the surface of the other conductivity type base region adjacent to the opposite side of the active portion in one surface of the semiconductor substrate Bandgap semiconductor vertical MOSFET.

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