JP6606819B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  An insulated gate bipolar transistor (IGBT) has an advantage of low on-resistance due to a conductivity modulation effect. Conventionally, carrier storage with the same conductivity type as the drift layer and higher impurity concentration than the drift layer is provided on the front surface of the substrate inside the drift layer in order to efficiently reduce the on-resistance due to the conductivity modulation effect. An IGBT provided with a (Carrier Storage (CS)) layer is known. Since the carrier storage layer becomes a barrier for minority carriers and the effect of storing minority carriers is increased, the current density between the collector and the emitter is increased, and the conductivity modulation effect is enhanced.

  Also, in an insulated gate field effect transistor (MOSFET), the on-resistance is reduced by increasing the impurity concentration on the substrate front side in the drift layer and in the vicinity of the channel. Techniques for achieving this are well known. In the MOSFET, the CS layer provided on the front side of the substrate inside the drift layer functions as a carrier spread (CS: Carrier Spread) layer, so-called JFET (Junction FET) resistance is reduced, and the on-state is reduced. Resistance decreases. Hereinafter, the carrier storage layer and the carrier spread layer are collectively referred to as a CS layer.

Next, the structure of a conventional semiconductor device including a CS layer will be described by taking a planar gate structure IGBT as an example. FIG. 9 is a cross-sectional view showing the structure of a peripheral breakdown voltage structure portion of a semiconductor device having a conventional CS layer. The peripheral voltage withstanding structure 122 is an area that is disposed outside the active region 121 and surrounds the periphery of the active region 121, and relaxes the electric field on the substrate front surface side of the n ⁻ -type drift layer 102 to maintain the withstand voltage. It has a function. The active region 121 is a region through which a current flows in the on state. As shown in FIG. 9, in the conventional semiconductor device, an n ⁻ type drift layer 102, an n type CS layer 103 and a p ⁺ type base layer 104 layer are sequentially formed on the front surface of a p ⁺ type semiconductor substrate 101 by epitaxial growth. It is configured using an epitaxial substrate formed by stacking. That is, the n-type CS layer 103 is provided between the n ⁻ type drift layer 102 and the p ⁺ type base layer 104.

The n-type CS layer 103 is provided from the active region 121 to the peripheral breakdown voltage structure 122. The peripheral breakdown voltage structure portion 122 is provided with a groove 113 that penetrates the p ⁺ type base layer 104 in the depth direction and reaches the n type CS layer 103. A portion of the n-type CS layer 103 exposed at the bottom surface of the groove 113 is provided with a junction termination extension (JTE) structure adjacent to the end of the p ⁺ -type base layer 104. The JTE structure is composed of p-type regions (first and second JTE regions 114 and 115) having a lower impurity concentration than the p ⁺ -type base layer 104. Reference numerals 107, 110, and 112 denote a p ⁺⁺ type contact region, an interlayer insulating film, and a collector electrode, respectively.

  As a device for reducing the on-resistance by providing the CS layer as described above, a trench manufactured (manufactured) using a semiconductor having a wider band gap than silicon (Si) (hereinafter referred to as a wide band gap semiconductor). MOS type semiconductor devices having a gate structure have been proposed (for example, the following Patent Document 1 (paragraphs 0018 to 0019, FIG. 5), the following Patent Document 2 (paragraphs 0016 to 0017, FIGS. 1 and 2), and the following: Patent Document 3 (see page 14, line 32 to page 15, line 14, FIG. 20). In the following Patent Documents 1 to 3, a CS layer made of an epitaxial layer is provided in the drift layer near the boundary with the base layer, at a depth shallower than the bottom of the trench from the front surface of the substrate.

JP 2008-16747 A Japanese Patent No. 5444608 Japanese Patent No. 5054255

  In particular, when a semiconductor device is manufactured (manufactured) using a wide band gap semiconductor such as a silicon carbide (SiC) semiconductor, the epitaxial growth is relatively easy to control the impurity concentration and thickness as in Patent Documents 1 to 3 above. In general, the CS layer is deposited, but in this case, the CS layer is also formed in the peripheral breakdown voltage structure surrounding the active region. However, when the CS layer is formed in the peripheral breakdown voltage structure portion, the impurity concentration of the CS layer may be about 1 to 2 digits higher than the impurity concentration of the drift layer. May be adversely affected and the maximum withstand voltage of the peripheral withstand voltage structure portion may be reduced. Then, the maximum breakdown voltage of the peripheral breakdown voltage structure portion is reduced, so that the breakdown voltage of the entire element is reduced.

  An object of the present invention is to provide a semiconductor device capable of improving the withstand voltage in order to solve the above-described problems caused by the prior art.

In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following characteristics in a semiconductor device having a peripheral breakdown voltage structure portion outside an active region through which a current flows. A drift layer of a first conductivity type having a first main surface and a second main surface is provided. An element structure having a second conductivity type region is provided on the first main surface side of the drift layer. A high-concentration region of a first conductivity type having a higher impurity concentration than the drift layer is provided on the first main surface side of the drift layer and on the element structure side of the active region, and terminates in the active region. It is provided selectively. The peripheral breakdown voltage structure includes a second conductivity type first JTE region in contact with the outer periphery of the high concentration region and the outer periphery of the second conductivity type region, and the first JTE region in contact with the outer periphery of the first JTE region. The second conductivity type second JTE region having a low impurity concentration, and the impurity concentration of the second conductivity type decreases toward the outside. The high concentration region reaches a deeper position on the drift layer side than the first JTE region and the second JTE region.

  In the semiconductor device according to the present invention, in the above-described invention, the high concentration region is a barrier region that suppresses movement of minority carriers moving from the second main surface side to the first main surface side of the drift layer. It is characterized by being.

  In the semiconductor device according to the present invention, in the above-described invention, the high-concentration region causes carriers that move from the first main surface side to the second main surface side of the drift layer to move to the first main surface of the drift layer. The spread region extends in a direction parallel to the surface.

The semiconductor device according to the present invention further has the following characteristics in the above-described invention. The element structure includes a second conductivity type semiconductor region, a first conductivity type semiconductor region, a gate insulating film, and a gate electrode. The second conductivity type semiconductor region is provided on the first main surface side of the drift layer. The first conductivity type semiconductor region is provided inside the second conductivity type semiconductor region. The gate insulating film is provided in contact with a region of the second conductivity type semiconductor region between the drift layer and the first conductivity type semiconductor region. The gate electrode is provided on the opposite side of the first conductivity type semiconductor region with the gate insulating film interposed therebetween. The high concentration region is provided between the drift layer and the second conductivity type semiconductor region.

  According to the above-described invention, the impurity concentration on the first main surface side of the drift layer in the peripheral withstand voltage structure portion can be lowered to such a level that a high withstand voltage can be realized. Thereby, the JTE structure can be provided in the drift layer having a low impurity concentration, and the maximum breakdown voltage of the peripheral breakdown voltage structure portion can be prevented from being lowered. In addition, according to the embodiment, it is possible to prevent the maximum breakdown voltage of the peripheral breakdown voltage structure portion from being lowered, so that the maximum breakdown voltage of the peripheral breakdown voltage structure portion can be made higher than that of the active region.

  The semiconductor device according to the present invention has an effect that the breakdown voltage can be improved.

It is sectional drawing which shows the structure of the active region of the semiconductor device concerning embodiment. It is sectional drawing which shows the structure of the periphery pressure | voltage resistant structure part of the semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device concerning embodiment. It is sectional drawing which shows the structure of the periphery pressure | voltage resistant structure part of the semiconductor device provided with the conventional CS layer.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment)
The structure of the semiconductor device according to the embodiment will be described using an IGBT having a planar gate structure as an example. FIG. 1 is a cross-sectional view illustrating a structure of an active region of a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view illustrating the structure of the peripheral breakdown voltage structure portion of the semiconductor device according to the embodiment. As shown in FIGS. 1 and 2, the semiconductor device according to the embodiment includes a peripheral breakdown voltage structure portion 22 so as to surround the periphery of the active region 21 outside the active region 21 through which a current flows in the on state. The peripheral breakdown voltage structure 22 has a function of relaxing the electric field on the substrate front surface (first main surface) side of the n ⁻ type drift layer 2 and maintaining the breakdown voltage. In the semiconductor device according to the embodiment, the n ⁻ type drift layer 2 and the p ⁺ type base layer 4 are sequentially stacked on the front surface of the p ⁺ type semiconductor substrate 1 serving as the p ⁺ type collector layer by epitaxial growth. It is comprised using the epitaxial base | substrate (semiconductor chip) formed.

In the active region 21, an n-type CS region (high concentration region) 3 including an n-type diffusion region is provided in the surface layer on the p ⁺ -type base layer 4 side inside the n ⁻ -type drift layer 2. N-type CS region 3 is provided in contact with p ⁺ -type base layer 4 deposited on n ⁻ -type drift layer 2. Ie, n-type CS region 3, n ^- the internal type drift layer 2, in the vicinity of the boundary between the p ⁺ -type base layer 4, the lower side of the p ⁺ -type base layer 4 (n ^- -type drift layer 2 side) It is provided to cover. Further, the n-type CS region 3 is provided only in the active region 21 and is not provided in the peripheral breakdown voltage structure portion 22. That, n ^- by n-type CS region 3 inside the type drift layer 2 is provided, only in the active region 21, n ^- impurity concentration type drift layer 2 of the substrate front surface side becomes high Yes.

The n-type CS region 3 becomes a minority carrier (hole) barrier when in the on state. Therefore, the n-type CS region 3 serves as a carrier storage (carrier accumulation) region that suppresses the extraction of minority carriers injected into the n ⁻ -type drift layer 2 from the collector side to the emitter side and enhances the minority carrier accumulation effect. Function. For this reason, by providing the n-type CS region 3, the current density of the n ⁻ -type drift layer 2 is increased, and the conductivity modulation effect can be enhanced. The n-type CS region 3 may extend, for example, over the entire active region 21 in parallel with the front surface of the base so as to cover the lower side of the p ⁺ -type base layer 4 and the JFET region 5 described later.

A MOS gate (insulated gate made of metal-oxide film-semiconductor) structure (element structure) is provided on the front surface side (p ⁺ -type base layer 4 side) of the epitaxial substrate. The MOS gate includes a p ⁺ type base layer 4, a JFET region 5, an n ⁺ type emitter region (first conductivity type semiconductor region) 6, a p ⁺⁺ type contact region 7, a gate insulating film 8 and a gate electrode 9. Specifically, inside the p ⁺ -type base layer 4, n-type JFET region 5 through the p ⁺ -type base layer 4 in the depth direction reaching the n-type CS region 3 is provided. The impurity concentration of JFET region 5 is higher than the impurity concentration of n ⁻ type drift layer 2. The JFET region 5 has a function of reducing the JFET resistance and reducing the on-resistance. A channel is formed along the gate electrode 9 in a portion (second conductivity type semiconductor region) of the p ⁺ type base layer 4 other than the JFET region 5.

An n ⁺ type emitter region 6 and a p ⁺⁺ type contact region 7 are selectively provided inside the p ⁺ type base layer 4. N ⁺ -type emitter region 6 and p ⁺⁺ -type contact region 7 are arranged apart from JFET region 5. p ⁺⁺ -type contact region 7, rather than the n ⁺ -type emitter region 6 is located away from the JFET region 5, and in contact with the n ⁺ -type emitter region 6. the p ⁺ -type base layer 4, on the surface of a portion held with JFET region 5 and the n ⁺ -type emitter region 6, gate insulating film 8 from the surface of the JFET region 5 over the surface of the n ⁺ -type emitter region 6 Is provided. On the surface of the gate insulating film 8, a gate electrode 9 is provided. An interlayer insulating film 10 is provided so as to cover the gate electrode 9.

The interlayer insulating film 10 is provided from the active region 21 to the peripheral breakdown voltage structure portion 22 on the front surface of the epitaxial substrate. In a contact hole penetrating the interlayer insulating film 10 in the depth direction, the n ⁺ -type emitter region 6 and the p ⁺⁺ -type contact region 7 are exposed. Emitter electrode 11 is in contact with n ⁺ -type emitter region 6 and p ⁺⁺ -type contact region 7 through a contact hole penetrating interlayer insulating film 10 in the depth direction, and is electrically connected to gate electrode 9 by interlayer insulating film 10. Is insulated. A collector electrode 12 is provided from the active region 21 to the peripheral breakdown voltage structure 22 on the back surface of the epitaxial base (that is, the back surface of the p ⁺ type semiconductor substrate 1).

In the peripheral breakdown voltage structure 22, a JTE structure including a p-type region having an impurity concentration lower than that of the p ⁺ -type base layer 4 is provided on the front surface side of the epitaxial substrate. The JTE structure has a function of relaxing the electric field in the peripheral voltage withstanding structure portion 22. As described above, since the peripheral breakdown voltage structure portion 22 is not provided with the n-type CS region 3, the impurity concentration of the n ⁻ type drift layer 2 in the peripheral breakdown voltage structure portion 22 is low enough to realize a high breakdown voltage. It has become. The JTE structure is provided in the n ⁻ type drift layer 2 having a low impurity concentration. In the JTE structure, for example, a p-type region (hereinafter referred to as a first JTE region) 14 and a p ⁻ -type region (hereinafter referred to as a second JTE region) 15 having different impurity concentrations are arranged in the direction from the active region 21 to the outside. It may be a double zone JTE structure in parallel so as to be in contact with each other.

Specifically, the peripheral breakdown voltage structure portion 22 is provided with a groove 13 that penetrates the p ⁺ type base layer 4 in the depth direction and reaches the n ⁻ type drift layer 2, and is formed on almost the entire front surface of the substrate. The n ⁻ type drift layer 2 is exposed. For example, first and second JTE regions 14 and 15 are selectively provided concentrically surrounding the active region 21 on the surface layer of the n ⁻ type drift layer 2 exposed at the bottom surface of the groove 13. The first JTE region 14 is provided on the innermost side of the peripheral breakdown voltage structure portion 22 and is in contact with the end portions of the n-type CS region 3 and the p ⁺ -type base layer 4. The second JTE region 15 is provided outside the first JTE region 14 and is in contact with the first JTE region 14.

Next, a method for manufacturing a semiconductor device according to the embodiment will be described by taking, as an example, the case of manufacturing (manufacturing) a IGBT having a withstand voltage of 13 kV class. 3-8 is sectional drawing which shows the state in the middle of manufacture of the semiconductor device concerning Embodiment. 3 to 8, (a) shows the state of the active region 21, and (b) shows the state of the peripheral breakdown voltage structure 22. 3 and 5-7 illustrate arrows indicating ion implantation only in the opening of the ion implantation mask. First, as shown in FIG. 3, a p ⁺ type semiconductor substrate (semiconductor wafer) 1 to be a p ⁺ type collector layer is prepared as a starting substrate. The impurity concentration of the p ⁺ type semiconductor substrate 1 may be about 1 × 10 ¹⁸ / cm ³ , for example. Next, an n ⁻ type drift layer 2 is deposited on the front surface of the p ⁺ type semiconductor substrate 1 by epitaxial growth. The impurity concentration of the n ⁻ type drift layer 2 may be about 1 × 10 ¹⁵ / cm ³ , for example.

Next, an ion implantation mask 31 having an opening corresponding to the formation region of the active region 21 is formed on the surface of the n ⁻ type drift layer 2. That is, the ion implantation mask 31 covers a portion corresponding to the formation region of the peripheral breakdown voltage structure portion 22. Next, ion implantation 32 of n-type impurities is performed using this ion implantation mask as a mask, and the impurity concentration of the surface layer of the n ⁻ -type drift layer 2 is increased, so that, for example, 2 μm from the surface of the n ⁻ -type drift layer 2. An n-type CS region 3 having a certain depth is formed. The impurity concentration of the n-type CS region 3 may be, for example, about 1 × 10 ¹⁶ / cm ³ or more and 1 × 10 ¹⁷ / cm ³ or less. At this time, since the peripheral breakdown voltage structure portion 22 is covered with the ion implantation mask 31, the n-type CS region 3 is not formed in the peripheral breakdown voltage structure portion 22. Next, the ion implantation mask 31 is removed.

Next, as shown in FIG. 4, ap ⁺ type base layer 4 is deposited on the surfaces of n ⁻ type drift layer 2 and n type CS region 3 by epitaxial growth. Through the steps so far, an epitaxial substrate (epitaxial wafer) is formed by sequentially stacking the n ⁻ type drift layer 2 and the p ⁺ type base layer 4 on the p ⁺ type semiconductor substrate 1. Next, as shown in FIG. 5, an ion implantation mask 33 having an opening corresponding to the formation region of the JFET region 5 is formed on the surface of the p ⁺ type base layer 4. Next, ion implantation 34 of n-type impurities is performed using the ion implantation mask 33 as a mask, and a part of the p ⁺ -type base layer 4 is inverted to n-type (returned) to form the JFET region 5. Next, the ion implantation mask 33 is removed.

Next, as shown in FIG. 6, an ion implantation mask 35 having an opening corresponding to the formation region of the n ⁺ -type emitter region 6 is formed. Using the ion implantation mask 35 as a mask, n-type impurity ion implantation 36 is performed to form an n ⁺ -type emitter region 6 in the surface layer of the p ⁺ -type base layer 4. Next, the ion implantation mask 35 is removed. Next, as shown in FIG. 7, an ion implantation mask 37 having an opening corresponding to the formation region of the p ⁺⁺ type contact region 7 is formed. Using the ion implantation mask 37 as a mask, p-type impurity ion implantation 38 is performed to form a p ⁺⁺ -type contact region 7 in the surface layer of the p ⁺ -type base layer 4. Next, the ion implantation mask 37 is removed.

Further, after the p ⁺ type base layer 4 is formed and before activation annealing described later, a JTE structure is formed in the peripheral voltage withstanding structure portion 22 at a predetermined timing. Specifically, for example, an etching mask (not shown) having an opening corresponding to the formation region of the peripheral voltage withstanding structure 22 is formed on the surface of the p ⁺ type base layer 4. Etching is performed using this etching mask as a mask, and a portion corresponding to the peripheral breakdown voltage structure portion 22 of the p ⁺ -type base layer 4 is removed (that is, the groove 13 is formed in the peripheral breakdown voltage structure portion 22). The n ⁻ type drift layer 2 is exposed. In this etching, the surface layer of the n ⁻ type drift layer 2 may be removed together with the p ⁺ type base layer 4, and the n type CS region 3 may be exposed, for example, on the active region 21 side of the trench 13. Then, the step of selectively ion-implanting the p-type impurity is repeatedly performed to selectively form the first and second JTE regions 14 and 15 in the surface layer of the n ⁻ -type drift layer 2 (FIGS. 2 and 8 (b)). )reference).

The order of ion implantation for forming the above-described JFET region 5, n ⁺ -type emitter region 6, p ⁺⁺ -type contact region 7 and first and second JTE regions 14 and 15 can be variously changed. Next, activation annealing (heat treatment) is performed to activate the diffusion regions formed by the respective ion implantations. 5 to 8 illustrate an example in which the n ⁺ -type emitter region 6, the p ⁺⁺ -type contact region 7, and the first and second JTE regions 14 and 15 are formed in this order. Next, as shown in FIG. 8, the gate insulating film 8 is formed by thermally oxidizing the front surface of the epitaxial substrate (the surface on the p ⁺ -type base layer 4 side). Next, for example, a polycrystalline silicon (poly-Si) layer is formed on the gate insulating film 8 as the gate electrode 9 and patterned.

Next, an interlayer insulating film 10 is formed so as to cover the gate electrode 9 and is subjected to heat treatment (reflow) after patterning. When patterning the interlayer insulating film 10, a contact hole is formed and the gate insulating film 8 exposed in the contact hole is also removed to expose the n ⁺ -type emitter region 6 and the p ⁺⁺ -type contact region 7. Next, the emitter electrode 11 is formed so as to fill the contact hole by sputtering, for example. Next, the collector electrode 12 is formed on the back surface of the p ⁺ type semiconductor substrate 1. Next, a passivation protective film is formed on the front surface of the epitaxial substrate. Thereafter, the epitaxial substrate is cut (diced) into chips to complete the IGBT shown in FIGS.

In the semiconductor device manufacturing method according to the above-described embodiment, the case where the p ⁺ type base layer 4 is formed by epitaxial growth has been described as an example. However, the p ⁺ type base layer 4 is formed by ion implantation. Also good. For example, after the n-type CS region 3 is formed, p-type impurity ions are implanted using the same ion implantation mask used to form the n-type CS region 3 as a mask, and p ^{+ is} implanted into the surface layer of the n-type CS region 3. The mold base layer 4 may be formed. In this case, since the n ⁻ -type drift layer 2 is exposed on the front surface of the base in the peripheral breakdown voltage structure portion 22, it is not necessary to form the groove 13 when forming the JTE structure.

Further, although the case where the n-type CS region 3 is formed by ion implantation is described as an example, after depositing an n-type epitaxial layer to be the n-type CS region 3 on the surface of the n ⁻ -type drift layer 2 by epitaxial growth, You may remove an outer part from the boundary of the active region 21 and the periphery pressure | voltage resistant structure part 22 of this n type epitaxial layer. In this case, after depositing an n-type epitaxial layer to be the n-type CS region 3 by epitaxial growth, for example, an etching mask is formed on the surface of the n-type epitaxial layer to cover a portion corresponding to the formation region of the active region 21. . Then, etching may be performed using this etching mask as a mask to remove a portion corresponding to the peripheral breakdown voltage structure portion 22 of the n-type epitaxial layer.

It is also possible to fabricate a planar gate structure MOSFET by applying the present invention. In this case, in the method for manufacturing a semiconductor device according to the above-described embodiment, instead of the p ⁺ type semiconductor substrate 1, an n ⁺ type semiconductor substrate (semiconductor wafer) serving as an n ⁺ type drain layer may be prepared as a starting substrate. Good. Conditions other than the starting substrate of the MOSFET manufacturing method to which the present invention is applied are the same as those of the IGBT manufacturing method shown in FIGS. The cross-sectional structure of a MOSFET to which the present invention is applied is the same as that in the case where an n ⁺ type semiconductor substrate is provided in place of the p ⁺ type semiconductor substrate 1 in the IGBT shown in FIGS. The n ⁺ type emitter region 6 and the emitter electrode 11 become an n ⁺ type source region and a source electrode, respectively. The n-type CS region 3 expands carriers (electrons) moving in the n ⁻ -type drift layer 2 from the source side to the drain side in the on-state in the lateral direction (direction parallel to the substrate front surface). It functions as a carrier spread (carrier diffusion) region.

(Example)
According to the method of manufacturing a semiconductor device according to the above-described embodiment, an IGBT having a planar gate structure having a breakdown voltage of 13 kV and having an n-type CS region 3 (hereinafter referred to as an example) is manufactured. The maximum pressure resistance was measured. For comparison, a conventional planar gate structure IGBT (see FIG. 9) provided with an n-type CS layer 103 was fabricated (hereinafter referred to as a conventional example), and the maximum breakdown voltage of the peripheral breakdown voltage structure 122 was measured. That is, the conventional example includes an n-type CS layer 103 provided from the active region 121 to the peripheral breakdown voltage structure 122. The configuration other than the conventional n-type CS layer 103 is the same as that of the embodiment. As a result, it was confirmed that the maximum withstand voltage of the peripheral withstand voltage structure portion 122 of the conventional example was 15.5 kV. On the other hand, the maximum withstand voltage of the peripheral withstand voltage structure portion 22 of the example is 18 kV, and it was confirmed that the maximum withstand voltage of the peripheral withstand voltage structure portion 22 can be improved as compared with the conventional example.

As described above, according to the embodiment, by providing the n-type CS region only in the active region, the impurity concentration on the substrate front surface side of the n ⁻ -type drift layer in the peripheral breakdown voltage structure portion is increased. The breakdown voltage can be lowered to a level that can be realized. Thereby, the JTE structure can be provided in the n ⁻ type drift layer having a low impurity concentration, and the maximum breakdown voltage of the peripheral breakdown voltage structure portion can be prevented from being lowered. Therefore, the maximum breakdown voltage of the peripheral breakdown voltage structure can be improved as compared with the conventional example described above, and the breakdown voltage of the entire element can be improved. In addition, according to the embodiment, it is possible to prevent the maximum breakdown voltage of the peripheral breakdown voltage structure portion from being lowered, so that the maximum breakdown voltage of the peripheral breakdown voltage structure portion can be made higher than that of the active region. Further, according to the embodiment, since the n-type CS region can be provided in the vicinity of the boundary with the p ⁺ -type base layer inside the n ⁻ -type drift layer in the active region, the on-resistance can be reduced as in the conventional case. Can be achieved. That is, in the IGBT, the n-type CS region functions as a carrier storage region, and the conductivity modulation effect can be enhanced and the on-resistance can be reduced. In the MOSFET, the n-type CS region functions as a carrier spread region, the JFET resistance is reduced, and the on-resistance can be lowered.

  As described above, the present invention can be variously modified without departing from the gist of the present invention. In the above-described embodiment, for example, the dimensions and impurity concentrations of each part are variously set according to required specifications. In the above-described embodiment, the planar gate structure MOS type semiconductor device is described as an example. However, the present invention has the same effect when applied to a trench gate structure MOS type semiconductor device. When the present invention is applied to a MOS semiconductor device having a trench gate structure, an n-type CS layer is formed between the drift layer and the base layer at a depth shallower than the bottom of the trench from the base surface and only in the active region. May be formed. The present invention has the same effect when applied to a semiconductor device manufactured using a wide band gap semiconductor (a semiconductor having a wider band gap than silicon) such as a silicon carbide (SiC) semiconductor. In the embodiment described above, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is the same even if the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the semiconductor device according to the present invention is useful for a semiconductor device provided with a JTE structure (RESURF: Reduced Surface Field) in the peripheral breakdown voltage structure, and in particular, a wide band gap such as a silicon carbide semiconductor. It is suitable for a high breakdown voltage semiconductor device having a breakdown voltage of 13 kV or higher manufactured using a semiconductor.

1 p ⁺ type semiconductor substrate 2 n ⁻ type drift layer 3 n type CS region 4 p ⁺ type base layer 5 JFET region 6 n ⁺ type emitter region 7 p ⁺⁺ type contact region 8 gate insulating film 9 gate electrode 10 interlayer insulating film DESCRIPTION OF SYMBOLS 11 Emitter electrode 12 Collector electrode 13 Groove 14 1st JTE area | region 15 2nd JTE area | region 21 Active area | region 22 Peripheral pressure | voltage resistant structure part 31,33,35,37 Ion implantation mask 32,34,36,38 Ion implantation

Claims (4)

In a semiconductor device having a peripheral breakdown voltage structure outside the active region through which current flows,
A first conductivity type drift layer having a first main surface and a second main surface;
An element structure provided on the first main surface side of the drift layer and having a region of a second conductivity type ;
A high-concentration region of a first conductivity type having a higher impurity concentration than the drift layer, provided on the first main surface side of the drift layer and on the element structure side of the active region, and terminating in the active region; ,
The second conductivity type first JTE region in contact with the outer periphery of the high concentration region and the outer periphery of the second conductivity type region, and the second conductivity having a lower impurity concentration than the first JTE region in contact with the outer periphery of the first JTE region. The peripheral breakdown voltage structure portion, which is formed of a second JTE region of the mold and has a lower impurity concentration of the second conductivity type toward the outside ,
With
The high-concentration region reaches a position deeper on the drift layer side than the first JTE region and the second JTE region.   2. The semiconductor device according to claim 1, wherein the high-concentration region is a barrier region that suppresses movement of minority carriers moving from the second main surface side to the first main surface side of the drift layer. .   The high concentration region is a spread region that spreads carriers moving from the first main surface side of the drift layer toward the second main surface side in a direction parallel to the first main surface of the drift layer. The semiconductor device according to claim 1. The element structure is
A second conductivity type semiconductor region provided on the first main surface side of the drift layer;
A first conductivity type semiconductor region provided inside the second conductivity type semiconductor region;
A gate insulating film provided in contact with a region of the second conductivity type semiconductor region between the drift layer and the first conductivity type semiconductor region;
A gate electrode provided on the opposite side of the first conductivity type semiconductor region across the gate insulating film,
The semiconductor device according to claim 1, wherein the high concentration region is provided between the drift layer and the second conductivity type semiconductor region.

Images