CN116779649B

CN116779649B - Semiconductor power device layout

Info

Publication number: CN116779649B
Application number: CN202311041883.6A
Authority: CN
Inventors: 黄泽军; 江洪湖; 蔡远飞; 华俊武; 于蒙蒙
Original assignee: SHENZHEN RUICHIPS SEMICONDUCTOR CO LTD
Current assignee: SHENZHEN RUICHIPS SEMICONDUCTOR CO LTD
Priority date: 2023-08-18
Filing date: 2023-08-18
Publication date: 2023-12-01
Anticipated expiration: 2043-08-18
Also published as: CN116779649A

Abstract

The invention provides a semiconductor power device layout, which omits a closed structure which utilizes a grid groove to surround a virtual grid groove, reduces the number and the length of the grid groove, reduces the Miller capacitance and reduces the probability of warping. Meanwhile, under the condition that the grooves are not required to be additionally increased, the movement of the multiple sub-regions in the base region is limited, and the thermal stress on the chip is reduced.

Description

Semiconductor power device layout

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor power device layout.

Background

The IGBT is an abbreviation of Insulated Gate Bipolar Transistor (insulated gate bipolar transistor), the IGBT is a device formed by compounding a MOSFET and a bipolar transistor, the input electrode of the IGBT is a MOSFET, the output electrode of the IGBT is a PNP transistor, the IGBT combines the advantages of the MOSFET device, namely, the MOSFET device has the advantages of small driving power and high switching speed, the bipolar device has the advantage of high capacity due to reduced saturation voltage, the frequency characteristic of the IGBT is between the MOSFET and the power transistor, the IGBT can normally work in a frequency range of tens of kHz, the IGBT is widely applied in the modern power electronic technology, and the IGBT takes the dominant role in high-frequency and medium-power application.

From a planar gate IGBT to a trench gate (trench) IGBT, the trench gate IGBT eventually has lower short circuit tolerance due to the increased conductive channel density of the trench structure. To improve the short-circuit tolerance of the device, it is usually achieved by adding a Dummy region, but the Dummy region may cause increased Wafer warpage in the product processing process, and a trench (i.e. Dummy trench) is added in the Dummy region to reduce the warpage effect, so that an IGBT with a Dummy trench structure is formed. Meanwhile, in order to reduce the input capacitance and the Miller capacitance, the virtual gate groove is not connected with a gate bus, so that the switching speed of the device is improved.

Referring to fig. 1 and 2, patent document 1 provides an IGBT layout having a dummy gate trench structure, the layout including a gate trench 202, a dummy gate trench 203, a base contact region 206, a dummy gate contact hole 207 and a source contact hole 208, the gate trench 202 being a continuous stripe-shaped gate trench, having a fold line structure in the middle, two ends extending into a p+ gate contact region 210 and being connected to a gate bus 212, so that every two adjacent gate trenches 202 are in a group, and the tail ends of the gate trenches 202 being connected to each other at a predetermined position from the p+ gate contact region 210 to form a closed dummy gate region; the dummy gate trench 203 is a continuous stripe-shaped dummy gate trench, and is located in the middle of the closed dummy gate region and parallel to the gate trench 202, where two ends or the middle of the dummy gate trench 203 form a closed contact window; the base contact region 206 is a continuous strip-shaped base contact region, and is located between two adjacent gate trenches 202 in a group of every two adjacent gate trenches 202 and is parallel to the gate trenches 202; the dummy gate contact hole 207 is located in the closed contact window on the dummy gate trench 203, and the width is greater than the width of the dummy gate trench 203; the source contact hole 208 is a continuous strip-shaped source contact hole, and covers the base contact region 206, and has a width greater than the width of the base contact region 206 and a length less than the length of the base contact region 206. Specifically, the base contact region 206 is located between two gate trenches 202, the device base region and the source region are connected to the source metal 211 through the source contact hole 208, the dummy gate trench 203 is connected to the source metal 211 through the dummy gate contact hole 207, two ends of the gate trench 202 extend into the p+ gate contact region 210, which is connected to the polysilicon gate 209, and the polysilicon gate 209 is connected to the gate bus 212 through the gate contact hole 211.

The technical contribution is that the grid grooves 202 on two sides of the virtual grid region are mutually connected at proper positions at the tail end to form a closed virtual grid region, so that the carrier transmission between the virtual grid region and the P+ grid contact region 210 is effectively blocked, and the chip performance can be improved; the dummy gate trenches 203 are arranged in parallel with the gate trenches 202 at a certain regular interval, and a closed contact window is formed at a proper position or at two ends of the center of the dummy gate trenches, and the peripheral dummy gate trenches 203 of the closed contact window block charge transmission caused by the dummy gate electrode, so that current distribution on the chip is more uniform. In general terms, the additional trenches (including the gate trench 202 and the dummy gate trench 203) limit the movement of the multi-electrons (i.e., hole carriers) in the base region to reduce the thermal stress on the chip.

However, the scheme adopted in patent document 1 has the following drawbacks:

1. in order to connect the tail ends of the gate trenches 202 to each other at a predetermined position apart from the p+ gate contact region 210 to form a closed dummy gate region, a new gate trench 202 needs to be formed between two adjacent gate trenches 202 as long sides (i.e., sides extending in the left-right direction) as short sides (i.e., sides extending in the front-rear direction), the two newly added short sides and the two long sides together enclose the closed dummy gate region, and the introduction of the short sides results in an increase in the number of gate trenches 202, so that the facing area of the gate trenches 202 and the collector increases, and the miller capacitance (Cgc) becomes larger.

2. On the other hand, in order to form a closed contact window on the dummy gate trench 203, it is also necessary to increase the number of the dummy gate trenches 203, resulting in a further increase in the number of trenches (including the gate trench and the dummy gate trench), which may exacerbate the wafer warp effect.

3. In the closed dummy gate region, the majority carriers remain holes, which provides a longer moving distance for the carriers in view of the longer distance of the dummy gate region along the length direction (i.e., the left-right direction) of the dummy gate trench 203, and when the carriers are transported in the dummy gate region, a large amount of carriers may be transported along the length direction of the dummy gate trench, and heat may be generated during the transporting along this moving distance, which is sufficient to cause a significant increase in thermal stress in the dummy gate region.

Patent document 1: patent name, a semiconductor power device layout; publication number CN105762147a; publication date 2016-07-13.

Disclosure of Invention

The invention aims to at least solve one of the technical problems in the prior art, and provides a semiconductor power device layout which can limit the movement of a plurality of sub-regions in a base region under the condition that a groove is not required to be additionally increased so as to reduce the thermal stress on a chip.

The invention provides a semiconductor power device layout, which comprises a grid groove, a virtual grid groove, a base region contact region, a virtual grid contact hole and a source electrode contact hole, wherein the grid groove is a continuous strip-shaped grid groove, the middle part of the grid groove is of a broken line structure, and two ends or only one end of the grid groove extends into the grid contact region and is connected with a grid bus; the virtual gate grooves are continuous strip-shaped virtual gate grooves and are positioned between every two adjacent gate grooves which are formed by combining every two adjacent gate grooves into a group and are parallel to the gate grooves; the base region contact region is a continuous strip-shaped base region contact region, is positioned between two adjacent grid grooves which are formed by taking every two adjacent grid grooves as a group, and is parallel to the grid grooves; the source contact hole is a continuous strip-shaped source contact hole, covers the base contact region, has a width larger than that of the base contact region and has a length smaller than that of the base contact region; the virtual gate groove sequentially comprises an N-type layer, a P-type layer and an insulating layer from inside to outside, wherein the P-type layer surrounds the outer side of the N-type layer, and the insulating layer surrounds the outer side of the P-type layer; and the virtual gate contact hole covers the N-type layer, and the width of the contact part of the virtual gate contact hole and the N-type layer is smaller than the width of the N-type layer.

As a further improvement, the width of the N-type layer is larger than that of the P-type layer, the P-type layer is a P+ layer, and the N-type layer is an N-layer.

As a further improvement, the ratio of the width of the N-type layer to the width of the P-type layer is greater than 2:1.

As a further improvement, the base contact region is a heavily doped base region.

As a further improvement, the semiconductor device further comprises a base region contact hole; when the base region contact region is a groove, a heavily doped base region is arranged in the base region between the adjacent virtual gate groove and gate groove; and the base region contact hole covers the heavily doped base region, and the width of the base region contact hole and the heavily doped base region contact part is smaller than the width of the heavily doped base region.

The second aspect of the invention provides a semiconductor power device layout, which comprises a grid groove, a virtual grid groove, a base region contact region, a virtual grid contact hole and a source electrode contact hole, wherein the grid groove is a continuous strip-shaped grid groove, the middle part of the grid groove is of a broken line structure, and two ends or only one end of the grid groove extends into the grid contact region and is connected with a grid bus; the virtual gate grooves are continuous strip-shaped virtual gate grooves and are positioned between every two adjacent gate grooves which are formed by combining every two adjacent gate grooves into a group and are parallel to the gate grooves; the base region contact region is a continuous strip-shaped base region contact region, is positioned between two adjacent grid grooves which are formed by taking every two adjacent grid grooves as a group, and is parallel to the grid grooves; the source contact hole is a continuous strip-shaped source contact hole, covers the base contact region, has a width larger than that of the base contact region and has a length smaller than that of the base contact region; the virtual gate trench sequentially comprises a polysilicon layer, an inner insulating layer, a metal layer and an outer insulating layer from inside to outside, wherein the inner insulating layer surrounds the outside of the polysilicon layer, the metal layer surrounds the outside of the inner insulating layer, and the outer insulating layer surrounds the outside of the metal layer; the dummy gate contact hole covers the polysilicon layer, and the width of the contact part between the dummy gate contact hole and the polysilicon layer is smaller than the width of the polysilicon layer.

As a further improvement, the semiconductor device further comprises a base region contact hole; when the base region contact region is used as a groove, a heavily doped base region is arranged in the base region between the adjacent virtual gate groove and gate groove; and the base region contact hole covers the heavily doped base region, and the width of the base region contact hole and the heavily doped base region contact part is smaller than the width of the heavily doped base region.

The invention provides a semiconductor power device layout, which comprises a grid groove, a virtual grid groove, a base region contact region, a virtual grid contact hole and a source electrode contact hole, wherein the grid groove is a continuous strip-shaped grid groove, the middle part of the grid groove is of a broken line structure, and two ends or only one end of the grid groove extends into the grid contact region and is connected with a grid bus; the virtual gate grooves are continuous strip-shaped virtual gate grooves and are positioned between every two adjacent gate grooves which are formed by combining every two adjacent gate grooves into a group and are parallel to the gate grooves; the base region contact region is a continuous strip-shaped base region contact region, is positioned between two adjacent grid grooves which are formed by taking every two adjacent grid grooves as a group, and is parallel to the grid grooves; the source contact hole is a continuous strip-shaped source contact hole, covers the base contact region, has a width larger than that of the base contact region and has a length smaller than that of the base contact region; the virtual gate contact hole is positioned on the virtual gate groove, and the width of the virtual gate contact hole is larger than that of the virtual gate groove; and forming a heavily doped base region in the region where the base region is contacted with the virtual gate contact hole and the virtual gate groove.

Compared with the prior art, the invention has at least the following beneficial effects:

1. the closed structure surrounding the virtual gate trench by the gate trench is eliminated, the number and the length of the gate trenches are reduced, the Miller capacitance is reduced, and the probability of warping is reduced.

2. Meanwhile, under the condition that the grooves are not required to be additionally increased, the movement of the multiple sub-regions in the base region is limited, and the thermal stress on the chip is reduced.

Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a top view of a partial structure of a semiconductor power device layout of the prior art;

FIG. 2 is a partial structural cross-sectional view of a semiconductor power device layout of the prior art;

fig. 3 is a partial structural cross-sectional view of the semiconductor power device layout provided in embodiment 1 of the present invention;

fig. 4 is an enlarged view of F in fig. 3;

fig. 5 is a partial structural cross-sectional view of the semiconductor power device layout provided in embodiment 2 of the present invention;

fig. 6 is an enlarged view at G in fig. 5;

fig. 7 is a partial structural cross-sectional view of the semiconductor power device layout provided in embodiment 3 of the present invention;

fig. 8a is a top view of a semiconductor power device layout according to one embodiment of the present invention;

FIG. 8b is a top view of the enlarged partial structure of the portion of FIG. 8a where the circle is located;

fig. 9a is a top view of a semiconductor power device layout according to another embodiment of the present invention;

FIG. 9b is a top view of the enlarged partial structure of the portion of FIG. 9a shown in circle;

the achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

Reference will now be made in detail to the present embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the accompanying drawings are used to supplement the description of the written description so that one can intuitively and intuitively understand each technical feature and overall technical scheme of the present invention, but not to limit the scope of the present invention.

It should be noted that the present invention is an improvement scheme of the chinese patent with publication number CN105762147B (i.e. patent document 1), and aims to solve the problems in patent document 1, so that the present invention will not be repeated when the same parts of the semiconductor power device layout as patent document 1 are not included in the improvement points of the present invention.

Referring to fig. 1 and 2, the trenches (including the dummy gate trench 203 and the gate trench 202) in the prior art are generally two-layer structures, i.e., the inner layer is N-type polysilicon and the outer layer is an oxide insulating layer, which can cause unstable and uncontrollable parasitic capacitance caused by the dummy gate trench 203 when the dummy gate trench 203 is in a potential floating state, and adversely affect the reduction of the parasitic capacitance caused by the dummy gate trench and affect the reliability of the device, so that the dummy gate trench 203 needs to be connected to the source (or emitter) to eliminate the potential floating state. As analyzed in the background art of patent document 1, since the base region is a hole, the hole (i.e., carrier) is easily induced to move toward the dummy gate trench 203, and a large amount of carriers generate heat during the movement of the base region, thereby increasing thermal stress on the semiconductor device and then inducing a warp effect. To solve this problem, those skilled in the art are continuously improving the layout structure of the semiconductor device, and actually, on the basis of improvement in patent document 1 (i.e., fig. 1 of patent document 1), the first generation product may be called a first generation product, in which the dummy gate trench 203 is enclosed in a smaller area (semi-enclosed area) by using the adjacent gate trench 202, and carriers outside the area can be prevented from moving toward the dummy gate trench 203 located in the area to a large extent. The solution of patent document 1 belongs to a second generation product, which adopts the end parts of adjacent gate trenches 202 to connect with each other, provides a completely closed region (i.e., a virtual gate region) for the virtual gate trench 203, and further utilizes the virtual gate trench 203 to enclose the virtual gate contact hole 207 within the closed region (it should be noted that, in order to make the latch-up condition of the semiconductor device more difficult to meet, the P region (i.e., the base region) and the n+ region generally need to be shorted, so the width of the gate contact hole connected with the source metal needs to be larger than the width of the virtual gate trench 203, i.e., the gate contact Kong Xuyao contacts the base region), so that carriers (multiple holes) in the base region cannot move toward the virtual gate trench 203 and the virtual gate contact hole 207 in a large scale, thereby optimizing the generation product to limit the defects existing in the multiple movement through the form of the semi-closed region.

It can be seen that the same concept is adopted for both the first-generation product and the second-generation product, i.e. a closed region is formed for each virtual gate trench 203, so as to limit the increase of thermal stress caused by the large-scale movement of the base region carriers to the virtual gate trench 203 and the virtual gate contact hole 207.

However, in order to form a closed region for closing the dummy gate trench 203, more trenches must be introduced, which tends to exacerbate the warpage phenomenon, and generally the ratio of the trenches is not allowed to be too much, for example, not more than 20%, in chip design, and it is difficult to control the warpage phenomenon once a certain ratio is exceeded. Particularly when the gate trench 202 is introduced, the miller capacitance is also increased, which is a technical problem to be solved by the current technical route.

The present invention has been made to solve the above problems, and detailed embodiments of the present invention for solving the above technical problems will be provided below with reference to the accompanying drawings.

Example 1

Referring to fig. 3 and 4, the present embodiment provides a semiconductor power device layout, which includes a gate trench 302, a dummy gate trench 303, a base contact region 306, a dummy gate contact hole 307 and a source contact hole 308, where the gate trench 302 is a continuous strip-shaped gate trench 302, the middle part is a broken line structure, and two ends extend into the gate contact region 310 and are connected with a gate bus 312; the dummy gate trench 303 is a continuous stripe-shaped dummy gate trench 303, and is located between two adjacent gate trenches 302, which are a group of every two adjacent gate trenches 302, and is parallel to the gate trenches 302; the base contact region 306 is a continuous strip-shaped base contact region 306, and is located between two adjacent gate trenches 302 in a group of every two adjacent gate trenches 302 and is parallel to the gate trenches 302; the source contact hole 308 is a continuous strip-shaped source contact hole 308, and covers the base contact region 306, the width is greater than the width of the base contact region 306, and the length is less than the length of the base contact region 306; the dummy gate trench 303 sequentially comprises an N-type layer 3031, a P-type layer 3032 and an insulating layer 3033 from inside to outside, wherein the P-type layer 3032 surrounds the outer side of the N-type layer 3031, and the insulating layer 3033 surrounds the outer side of the P-type layer 3032; the dummy gate contact hole 307 covers the N-type layer 3031, and the width of the contact portion between the dummy gate contact hole 307 and the N-type layer 3031 is smaller than the width of the N-type layer 3031.

Further, as shown in fig. 8a, gate bus lines 312 extending in the left-right direction are connected to the gate metal 301, and a plurality of gate bus lines 312 extending in the front-rear direction are provided, and each gate bus line 3112 extending in the front-rear direction is directly connected to the gate metal 301 or connected to the gate metal 301 through the gate bus lines 312 extending in the left-right direction, and gate trench 302 having a zigzag structure extends in the left-right direction as a whole, dummy gate trench 303 is parallel to gate trench 302, both ends float, and terminal 304 surrounds the entire periphery of the chip. As shown in fig. 3, the base contact region 306 is located between two gate trenches 302, the device base region and the source region are connected to the source metal 313 through the source contact hole 308, the dummy gate trench 303 is connected to the source metal 313 through the dummy gate contact hole 307, two ends of the gate trench 302 extend into the p+ gate contact region 310, which is connected to the polysilicon gate 309, and the polysilicon gate 309 is connected to the gate bus 312 through the gate contact hole 311.

As shown in fig. 4, the improvement of the present embodiment compared with patent document 1 is that, on the one hand, the width of the contact portion between the dummy gate contact hole 307 and the dummy gate trench 303 is set smaller than the width of the dummy gate trench 303, that is, the width of the contact portion between the dummy gate contact hole 307 and the N-type layer 3031 is set smaller than the width of the N-type layer 3031, so that the negatively charged dummy gate contact hole 307 cannot directly contact the P region, and there is no problem in that the majority of the attractive P region in patent document 1 moves to the dummy gate contact hole 307 in a large scale. Since the dummy gate contact 307 no longer contacts the P region, in order to keep the P region short to the n+ region, the base contact region 306 is set as a heavily doped base region, i.e., p+ region, and as shown in fig. 3, the base contact region 306 is short to the n+ region through the source contact hole 308.

In one example, as shown in fig. 8a and 8b, compared with patent document 1, the present embodiment does not need to form a closed region for surrounding the dummy gate trench 303, and the short-side gate trench 302 provided in the front-rear direction can be removed, reducing miller capacitance. Since the closed area structure for surrounding the dummy gate trench 303 is eliminated, the structure of the dummy gate trench 303 needs to be improved, specifically, the dummy gate trench 303 sequentially includes an N-type layer 3031, a P-type layer 3032 and an insulating layer 3033 from inside to outside, the P-type layer 3032 is surrounded on the outer side of the N-type layer 3031, and the insulating layer 3033 is surrounded on the outer side of the P-type layer 3032. The junction between the N-type layer 3031 and the P-type layer 3032 forms a depletion layer 400, a self-built electric field pointing from the N-type layer 3031 to the P-type layer 3032 is generated, and the N-type layer 3031 connected with the dummy gate contact hole 307 is electrically conducted with the source metal 313, so that the electric field generated by the N-type layer 3031 points to the N-type layer 3031 from the P-type layer 3032, and due to the existence of the self-built electric field in the depletion layer 400, the electric field in the P-type layer 3032 can not attract the movement of the multiple electrons in the base region to the dummy gate trench 303, i.e., the movement of the multiple electrons in the base region can be limited under the condition that no additional trench is required to be added, so that the thermal stress on a chip is reduced.

In another example, as shown in fig. 9a and 9b, the length of the gate trench 302 may be further shortened. Only one end of each gate trench 302 extends into the gate contact 310 and connects to the gate bus 312, and the other end is suspended without extending into the gate contact 310 or connecting to the gate bus 312. It will be appreciated that the miller capacitance is further reduced and the chance of warpage is reduced due to the reduced length of the gate trench 302. Specifically, as shown in fig. 9a and 9b, one end of each adjacent gate trench 302 extending into the gate contact region 310 and connected to the gate bus line 312 is staggered in the front-rear direction in order along the left-right end, that is, assuming that the left end of the current gate trench 302 extends into the gate contact region 310 and connected to the gate bus line 312, the right end of the next gate trench 302 extends into the gate contact region 310 and connected to the gate bus line 312 in the front-rear direction, the left end of the next gate trench 302 extends into the gate contact region 310 and connected to the gate bus line 312, and so on.

The base contact region 306 in patent document 1 serves as a flexible design region that can be used as a trench or a heavily doped base region, providing flexibility in design. It is appreciated that when base contact region 306 is used as a heavily doped base region, shorting of the base region to the n+ region can be achieved because source contact hole 308 contacts both base contact region 306 and the n+ region. However, when the base contact region 306 is a trench, a heavily doped base region needs to be disposed in the base region between the adjacent dummy gate trench 303 and gate trench 302; and a base contact hole is designed, the base contact hole covers the heavily doped base region, the width of the base contact hole and the heavily doped base contact part is smaller than that of the heavily doped base region, and the base contact hole is connected with the source metal 313 to realize the short circuit of the base region and the N+ region.

As shown in fig. 4, in one example, the N-type layer 3031 has a width greater than the width of the P-type layer 3032, and the P-type layer 3032 is a p+ layer and the N-type layer 3031 is an N-layer. Since the dummy gate contact hole 307 is in contact with only the N-type layer 3031, the N-type layer 3031 should be ensured to have a larger width, so that the dummy gate contact hole 307 only covers the N-type layer 3031 and does not erroneously contact the P-type layer 3032. However, since the overall width of the dummy gate trench 303 is constant, increasing the width of the N-type layer 3031 means that the width of the P-type layer 3032 needs to be reduced, and the width of the P-type layer 3032 is too small, the depletion layer 400 distributed in the P-type layer 3032 may occupy the entire P-type layer 3032 and directly contact with the insulating layer 3033, and the depletion layer 400 distributed in the P-type layer 3032 accumulates a large amount of negative charges due to diffusion, and these negative charges may attract the base region outside the dummy gate trench 303 to move toward the dummy gate trench 303 via the insulating layer 3033 (referred to as a punch through phenomenon of the depletion layer 400), thereby inducing thermal stress. Therefore, it is also necessary to make the P-type layer 3032 a p+ layer and the N-type layer 3031 an N-layer, and the depletion layer 400 is mainly distributed in the P-type layer 3032 because the N-type layer 3031 is doped low, so that the depletion layer 400 can be prevented from penetrating even if the P-type layer 3032 is narrower. Specifically, the ratio of the width of the N-type layer 3031 to the width of the P-type layer 3032 is greater than 2:1. For example, 2.5:1 or 3:1, the present invention is not limited.

Example 2

Referring to fig. 5 and 6, the present embodiment provides a semiconductor power device layout, which includes a gate trench 302, a dummy gate trench 303, a base contact region 306, a dummy gate contact hole 307 and a source contact hole 308, where the gate trench 302 is a continuous strip-shaped gate trench 302, the middle part is a broken line structure, and two ends extend into the gate contact region 310 and are connected with a gate bus 312; the dummy gate trench 303 is a continuous stripe-shaped dummy gate trench 303, and is located between two adjacent gate trenches 302, which are a group of every two adjacent gate trenches 302, and is parallel to the gate trenches 302; the base contact region 306 is a continuous strip-shaped base contact region 306, and is located between two adjacent gate trenches 302 in a group of every two adjacent gate trenches 302 and is parallel to the gate trenches 302; the source contact hole 308 is a continuous strip-shaped source contact hole 308, and covers the base contact region 306, the width is greater than the width of the base contact region 306, and the length is less than the length of the base contact region 306; the dummy gate trench 303 sequentially comprises a polysilicon layer 3034, an inner insulating layer 3035, a metal layer 3036 and an outer insulating layer 3037 from inside to outside, wherein the inner insulating layer 3035 surrounds the outer side of the polysilicon layer 3034, the metal layer 3036 surrounds the outer side of the inner insulating layer 3035, and the outer insulating layer 3037 surrounds the outer side of the metal layer 3036; the dummy gate contact hole 307 covers the polysilicon layer, and the width of the contact portion between the dummy gate contact hole 307 and the polysilicon layer is smaller than the width of the polysilicon layer 3034.

As shown in fig. 4, the improvement of the present embodiment compared with patent document 1 is that, on the one hand, the width of the contact portion of the dummy gate contact hole 307 with the dummy gate trench 303 is set smaller than the width of the dummy gate trench 303, that is, the width of the contact portion of the dummy gate contact hole 307 with the polysilicon layer is set smaller than the width of the polysilicon layer, so that the negatively charged dummy gate contact hole 307 cannot directly contact the P region, and there is no problem in that many photons in the attraction P region move to the dummy gate contact hole 307 in a large scale in patent document 1. Since the dummy gate contact 307 no longer contacts the P region, in order to keep the P region short to the n+ region, the base contact region 306 is set as a heavily doped base region, i.e., p+ region, and as shown in fig. 5, the base contact region 306 is short to the n+ region through the source contact hole 308.

In one example, as shown in fig. 8a and 8b, compared with patent document 1, the present embodiment does not need to form a closed region for surrounding the dummy gate trench 303, and the short-side gate trench 302 provided in the front-rear direction can be removed, reducing miller capacitance. Since the closed region structure for surrounding the dummy gate trench 303 is eliminated, the structure of the dummy gate trench 303 needs to be improved, specifically, the dummy gate trench 303 includes, from inside to outside, a polysilicon layer 3034, an inner insulating layer 3035, a metal layer 3036, and an outer insulating layer 3037, the inner insulating layer 3035 surrounds the outside of the polysilicon layer 3034, the metal layer 3036 surrounds the outside of the inner insulating layer 3035, and the outer insulating layer 3037 surrounds the outside of the metal layer 3036. The metal layer 3036 may be specifically formed of copper metal or other conductive metal material, and the conduction between the polysilicon layer 3034 and the source metal 313 may generate an electric field directed from the inner insulating layer 3035 to the polysilicon layer 3034, and the presence of the metal layer 3036 may block the holes of the electric field attracting the base region from moving toward the dummy gate trench 303, i.e., the movement of the multiple electrons in the base region can be limited without adding a trench additionally, so as to reduce the thermal stress on the chip.

Example 3

Referring to fig. 7, the present embodiment provides a semiconductor power device layout, which includes a gate trench 302, a dummy gate trench 303, a base contact region 306, a dummy gate contact hole 307 and a source contact hole 308, where the gate trench 302 is a continuous stripe-shaped gate trench 302, the middle part is a zigzag structure, and two ends extend into the gate contact region 310 and are connected with a gate bus 312; the dummy gate trench 303 is a continuous stripe-shaped dummy gate trench 303, and is located between two adjacent gate trenches 302, which are a group of every two adjacent gate trenches 302, and is parallel to the gate trenches 302; the base contact region 306 is a continuous strip-shaped base contact region 306, and is located between two adjacent gate trenches 302 in a group of every two adjacent gate trenches 302 and is parallel to the gate trenches 302; the source contact hole 308 is a continuous strip-shaped source contact hole 308, and covers the base contact region 306, the width is greater than the width of the base contact region 306, and the length is less than the length of the base contact region 306; the dummy gate contact hole 307 is located on the dummy gate trench 303, and has a width greater than that of the dummy gate trench 303; the regions of the base region in contact with the dummy gate contact holes 307 and the dummy gate trenches 303 all form heavily doped base regions 305.

Further, as shown in fig. 8a and 8b, gate bus lines 312 extending in the left-right direction are connected to the gate metal 301, the number of gate bus lines 312 extending in the front-rear direction is plural, and each gate bus line 3112 extending in the front-rear direction is directly connected to the gate metal 301 or connected to the gate metal 301 through the gate bus lines 312 extending in the left-right direction, gate trench 302 having a zigzag structure extends in the left-right direction as a whole, dummy gate trench 303 is parallel to gate trench 302, both ends float, and terminal 304 surrounds the entire periphery of the chip. As shown in fig. 7, the base contact region 306 is located between two gate trenches 302, the device base region and the source region are connected to the source metal 313 through the source contact hole 308, the dummy gate trench 303 is connected to the source metal 313 through the dummy gate contact hole 307, two ends of the gate trench 302 extend into the p+ gate contact region 310, which is connected to the polysilicon gate 309, and the polysilicon gate 309 is connected to the gate bus 312 through the gate contact hole 311.

As shown in fig. 7, the dummy gate trench 303 sequentially includes, from inside to outside, a polysilicon layer 3038 and an insulating layer 3039 wrapped around the polysilicon layer 3038, and for each dummy gate trench 303, heavily doped base regions 305 (i.e., p+ regions) are formed on both sides of the dummy gate trench 303, and the heavily doped base regions 305 surround the dummy gate trench 303 and the portion of the dummy gate contact hole 307 in contact with the base regions. It will be appreciated that in this embodiment, since the heavily doped base region 305 is formed in the region where the base region contacts the dummy gate contact hole 307 and the dummy gate trench 303, when the dummy gate trench 303 is connected to the source metal 313 and negatively charged, the electric field will attract the holes in the heavily doped base region 305 to approach the dummy gate trench 303, and since the hole concentration in the heavily doped base region 305 surrounding the dummy gate trench 303 and the dummy gate contact hole 307 is higher than that in the base region, there is a high concentration of holes in the heavily doped base region 305, and the base region has a low concentration of holes, and this concentration difference brings about a diffusion effect, which will hinder the holes in the base region from moving to the dummy gate trench 303 and the dummy gate contact hole 307. I.e. the movement of the polyton in the base region can be restricted without the need of adding extra trenches to reduce the thermal stress on the chip.

The base contact region 306 in patent document 1 serves as a flexible design region that can be used as a trench or a heavily doped base region, providing flexibility in design. In this example, the base region contacted by the dummy gate contact hole 307 is set as the heavily doped base region 305, the n+ region is contacted with the source contact hole 308, and the source contact hole 308 and the dummy gate contact hole 307 are distributed to be contacted with the source metal 313, so that the short circuit between the base region and the n+ region can be realized. When the base contact region 306 is a trench, there is no need to provide an additional base contact hole as in embodiments 1 and 2.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.

Finally, it should be noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A semiconductor power device layout comprises a grid groove, a virtual grid groove, a base region contact region, a virtual grid contact hole and a source electrode contact hole, and is characterized in that,

the grid electrode groove is a continuous strip-shaped grid electrode groove, the middle part of the grid electrode groove is of a broken line structure, and two ends or only one end of the grid electrode groove extends into the grid electrode contact area and is connected with the grid electrode bus;

the virtual gate grooves are continuous strip-shaped virtual gate grooves and are positioned between every two adjacent gate grooves which are formed by combining every two adjacent gate grooves into a group and are parallel to the gate grooves;

the base region contact region is a continuous strip-shaped base region contact region, is positioned between two adjacent grid grooves which are formed by taking every two adjacent grid grooves as a group, and is parallel to the grid grooves;

the source contact hole is a continuous strip-shaped source contact hole, covers the base contact region, has a width larger than that of the base contact region and has a length smaller than that of the base contact region;

the virtual gate groove sequentially comprises an N-type layer, a P-type layer and an insulating layer from inside to outside, wherein the P-type layer surrounds the outer side of the N-type layer, and the insulating layer surrounds the outer side of the P-type layer;

and the virtual gate contact hole covers the N-type layer, and the width of the contact part of the virtual gate contact hole and the N-type layer is smaller than the width of the N-type layer.

2. The semiconductor power device layout of claim 1 wherein the N-type layer has a width greater than a P-type layer width, and wherein the P-type layer is a p+ layer and the N-type layer is an N-layer.

3. The semiconductor power device layout of claim 2 wherein the ratio of the N-type layer width to the P-type layer width is greater than 2:1.

4. A semiconductor power device layout according to claim 1, 2 or 3, wherein the base contact region is a heavily doped base region.

5. A semiconductor power device layout according to claim 1, 2 or 3, further comprising base contact holes;

when the base region contact region is a groove, a heavily doped base region is arranged in the base region between the adjacent virtual gate groove and gate groove;

and the base region contact hole covers the heavily doped base region, and the width of the base region contact hole and the heavily doped base region contact part is smaller than the width of the heavily doped base region.

6. A semiconductor power device layout comprises a grid groove, a virtual grid groove, a base region contact region, a virtual grid contact hole and a source electrode contact hole, and is characterized in that,

the virtual gate trench sequentially comprises a polysilicon layer, an inner insulating layer, a metal layer and an outer insulating layer from inside to outside, wherein the inner insulating layer surrounds the outside of the polysilicon layer, the metal layer surrounds the outside of the inner insulating layer, and the outer insulating layer surrounds the outside of the metal layer;

the dummy gate contact hole covers the polysilicon layer, and the width of the contact part between the dummy gate contact hole and the polysilicon layer is smaller than the width of the polysilicon layer.

7. A semiconductor power device layout according to claim 6 wherein said base contact region is a heavily doped base region.

8. A semiconductor power device layout according to claim 6 or 7, further comprising a base contact hole;

when the base region contact region is used as a groove, a heavily doped base region is arranged in the base region between the adjacent virtual gate groove and gate groove;