CN220604695U - Semiconductor terminal protection structure - Google Patents
Semiconductor terminal protection structure Download PDFInfo
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- CN220604695U CN220604695U CN202322071884.7U CN202322071884U CN220604695U CN 220604695 U CN220604695 U CN 220604695U CN 202322071884 U CN202322071884 U CN 202322071884U CN 220604695 U CN220604695 U CN 220604695U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 46
- 229920005591 polysilicon Polymers 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000010953 base metal Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 5
- 238000002347 injection Methods 0.000 abstract description 30
- 239000007924 injection Substances 0.000 abstract description 30
- 230000000712 assembly Effects 0.000 description 4
- 238000000429 assembly Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Abstract
The utility model provides a semiconductor terminal protection architecture, relate to the technical field of semiconductor protection, including active region and terminal protection region, the active region is used for the power device to work, the terminal protection region is used for the power device to connect on the semiconductor, when the power device works, play the guard action to the semiconductor, prevent the semiconductor from being broken down under the operating condition, the terminal protection region is provided with the conductive polycrystalline silicon body subassembly, alternate between the conductive polycrystalline silicon body subassembly and distribute the field limiting ring injection region, and the depth of field limiting ring injection region is trapezoidal distribution; in summary, the utility model improves the tolerance of the terminal protection area without increasing the occupied area of the chip by arranging the field limiting ring injection area in a ring shape and deepening the depth at the edge, and has simple structure and cost saving.
Description
Technical Field
The utility model relates to the technical field of semiconductor protection, in particular to a semiconductor terminal protection structure.
Background
Along with the continuous maturity of power MOS device technology and design, domestic and foreign power MOS device competition is also more and more vigorous, reduce the cost of device, improve the performance and the reliability of device are also more and more urgent, generally speaking, semiconductor power device includes active region and terminal protection district, wherein, active region is the working region of power device, take N channel MOS device as an example, active region is the epitaxial layer that forms on the silicon substrate, and further form the P well region on the epitaxial layer, wherein, the silicon substrate is N+ region, the external high potential in during operation bottom, the epitaxial layer is N-region, be the collector region, play the effect of amplifying circuit, terminal protection district is used for guaranteeing that each active region reduces the electric field intensity of surface after the scribing, prevent the edge breakdown of device. Typically, after active area dicing, the sides of the chip edge are equipotential with the bottom, and if no action is added at the very edge region, a very high voltage is required to be applied in the lateral direction, and if the same width and thickness as the bottom are used at the edge region, the device may be broken down.
In the related art, the existing terminal protection area generally adopts a mode of adding one or more P-wells to form a protection ring or a voltage division ring, and meanwhile, in the existing process, in order to prevent parasitic triode from being generated by N-region inversion on the surface of the most edge part of the terminal protection area, an N-well can be injected into the most edge part of the terminal to form a cut-off ring structure.
In view of the above-mentioned related art, the inventors consider that there is a problem in that the terminal protection area occupies a large area of the chip, and the manufacturing cost is high.
Disclosure of Invention
Aiming at the defects of large occupied chip area and high manufacturing cost of a terminal protection area in the prior art, the utility model aims to provide a semiconductor terminal protection structure, which comprises the following specific schemes:
the utility model provides a semiconductor terminal protection architecture, includes active region and terminal protection zone, is provided with virtual dotted line that sets up between active region and the terminal protection zone, terminal protection zone parcel formula sets up in the periphery of active region, the terminal protection zone is provided with first semiconductor substrate, first semiconductor substrate includes first conductivity type drift region, field limit shielding insulating layer and electrically conductive polycrystalline silicon body subassembly, the field limit shielding insulating layer parcel sets up the outside of electrically conductive polycrystalline silicon body subassembly, electrically conductive polycrystalline silicon body subassembly is provided with a plurality of, a plurality of electrically conductive polycrystalline silicon body subassembly is in the inside of first conductivity type drift region in proper order transversely vertical distribution, a plurality of interlude between the electrically conductive polycrystalline silicon body subassembly has the field limit ring injection district, the field limit ring injection district is the cyclic annular and is provided with a plurality of, a plurality of the field limit ring injection district is trapezoidal distribution in the degree of depth, and a plurality of field limit ring injection district width is unequal.
Further preferably, the first semiconductor substrate further comprises a first conductivity type substrate disposed below the first conductivity type drift region and a base metal access layer disposed at a bottom of the first conductivity type substrate.
The upper portion of the active region is provided with a first conductive type source region and a second conductive type region, the first conductive type source region is arranged on the upper portion of the second conductive type region, and source metal is connected to the outside of the first conductive type source region.
The conductive polysilicon body component comprises a conductive silicon body and a first type conductive well region, the first type conductive well region is circularly wrapped at the bottom of the conductive silicon body, and the field limiting shielding insulating layer is arranged between the conductive silicon body and the first type conductive well region at intervals.
The first semiconductor substrate further comprises an insulating dielectric layer, and the insulating dielectric layer is paved on the top of the conductive polysilicon body assembly.
The lower part of the active region is provided with a second semiconductor substrate, the second semiconductor substrate comprises first conductive polysilicon and a first insulating layer, the first conductive polysilicon and the first insulating layer are both provided with a plurality of first conductive polysilicon, the first conductive polysilicon is the same in size, the first insulating layer is the same in width, and the first insulating layer is round and wrapped at the bottom of the first conductive polysilicon.
And a second type conductive well region is wrapped outside the upper part of the conductive polysilicon body assembly.
Compared with the prior art, the utility model has the following beneficial effects:
(1) The semiconductor terminal protection structure comprises an active region and a terminal protection region, wherein the active region is used for a power device to work, the terminal protection region is used for connecting the power device to a semiconductor, when the power device works, the semiconductor is protected from breakdown in a working state, a first semiconductor substrate is used for providing a moving place for electrons, a first conductive drift region is used for transmitting electrons, a field limiting shielding insulating layer is used for insulating electrons from the outside, a conductive polysilicon body component is used for conducting an electronic amplifying circuit, the field limiting ring injection region is annular and is provided with a plurality of field limiting ring injection regions, the active region of the terminal electrons is effectively increased, all injection regions are connected into a piece, a graded junction with the doping concentration taking the field limiting ring injection region as the center is formed, and the depth of the field limiting ring injection region far away from the active region is gradually increased, so that when the device is reversely biased, the field limiting ring injection region of the terminal protection region is consumed and the device is completely, and simultaneously, the field limiting ring injection region is not increased in depth, and the stretching capacity of the chip is not increased, so that the occupied area is reduced; in summary, the utility model improves the tolerance of the terminal protection area without increasing the occupied area of the chip by arranging the field limiting ring injection area in a ring shape and deepening the depth at the edge, and has simple structure and cost saving.
Drawings
FIG. 1 is an overall schematic of an embodiment of the present utility model;
FIG. 2 is a schematic cross-sectional view of an embodiment of the present utility model;
fig. 3 is a schematic diagram of a well region according to an embodiment of the utility model.
Reference numerals: 1. an active region; 2. a terminal protection area; 3. a source metal layer; 4. a first conductive type source region; 5. a second conductivity type region; 6. a second semiconductor substrate; 61. a first conductive polysilicon; 62. a first insulating layer; 7. a first semiconductor substrate; 8. a first conductivity type drift region; 9. a field limiting shielding insulating layer; 10. a conductive polysilicon body assembly; 101. a conductive silicon body; 102. a first type conductive well region; 11. a second type conductive well region; 12. a first conductivity type substrate; 13. and a base metal access layer.
Detailed Description
The present utility model will be described in further detail with reference to examples and drawings, but embodiments of the present utility model are not limited thereto.
As shown in fig. 1, a semiconductor terminal protection structure comprises an active area 1 and a terminal protection area 2, wherein virtual dotted lines are arranged between the active area 1 and the terminal protection area 2, the terminal protection area 2 is arranged on the periphery of the active area 1 in a ring-shaped wrapping manner, wherein the active area 1 is used for a power device to work, the terminal protection area 2 is used for the power device to be connected to a semiconductor, and when the power device works, the semiconductor is protected from breakdown in a working state.
In order to realize the protection effect on the semiconductor, the terminal protection region 2 is provided with a first semiconductor substrate 7 for providing a moving place for electrons, as shown in fig. 2, the first semiconductor substrate 7 comprises a first conductive type drift region 8, a field limiting shielding insulating layer 9 and a conductive polysilicon body assembly 10, the field limiting shielding insulating layer 9 is wrapped and arranged outside the conductive polysilicon body assembly 10 for insulating electrons from the outside and for conducting an electronic amplifying circuit, the conductive polysilicon body assembly 10 is provided with a plurality of conductive polysilicon body assemblies 10, the plurality of conductive polysilicon body assemblies 10 are sequentially and transversely vertically distributed inside the first conductive type drift region 8, field limiting ring injection regions are alternately distributed among the plurality of conductive polysilicon body assemblies 10, the field limiting ring injection regions are annularly provided with a plurality of field limiting ring injection regions, the plurality of field limiting ring injection regions are distributed in a trapezoid shape in depth, and the widths of the plurality of field limiting ring injection regions are unequal.
The depth of the field limiting ring injection region from one end of the terminal protection region 2 close to the active region 1 to one end far away from the active region 1 is gradually increased, and the width is gradually widened, meanwhile, the whole field limiting ring injection region is connected into a whole annular shape, electrons are consumed in the field limiting ring injection region, a semiconductor is prevented from being broken down, the voltage withstand capability of a device terminal is greatly improved, and the overlarge occupied area of a chip is avoided while the depth is increased.
The first semiconductor substrate 7 further comprises an insulating dielectric layer laid on top of the conductive polysilicon body assembly 10 for improving the conductive efficiency of the semiconductor.
In order to facilitate electron flow between the semiconductor and other devices, the first semiconductor substrate 7 further comprises a first conductivity type substrate 12 and a base metal access layer 13, the first conductivity type substrate 12 being arranged below the first conductivity type drift region 8, the base metal access layer 13 being arranged at the bottom of the first conductivity type substrate 12 for accessing the base circuit.
Accordingly, the active region 1 is provided at an upper portion thereof with a first conductive type source region 4 and a second conductive type region 5 for connection to a collector device, the first conductive type source region 4 is provided at the second conductive type region 5, and a source metal is connected to the outside of the first conductive type source region 4.
The conductive polysilicon body assembly 10 comprises a conductive silicon body 101 and a first type conductive well region 102, the first type conductive well region 102 is circularly wrapped at the bottom of the conductive silicon body 101, the field limiting shielding insulating layer 9 is arranged between the conductive silicon body 101 and the first type conductive well region 102 at intervals, meanwhile, a second type conductive well region 11 is wrapped at the outer part of the upper part of the conductive polysilicon body assembly 10, as shown in fig. 3, a plurality of well regions are arranged to facilitate increasing the movement space of electrons, and therefore the possibility of breakdown of a semiconductor due to excessive voltage is reduced.
The lower part of the active region 1 is provided with a second semiconductor substrate 6, the second semiconductor substrate 6 comprises a first conductive polysilicon 61 and a first insulating layer 62, the first conductive polysilicon 61 and the first insulating layer 62 are both provided with a plurality of first conductive polysilicon 61, the sizes of the plurality of first conductive polysilicon 61 are the same, the widths of the plurality of first insulating layers 62 are the same for the circulation of electrons, and the first insulating layer 62 is arranged at the bottom of the first conductive polysilicon 61 in a round package.
The working principle of the utility model is as follows:
after the semiconductor is connected into the device, the device works in the active region 1, source metal is connected, electrons in the semiconductor circulate, a plurality of field limiting ring injection regions are arranged between a plurality of conductive polysilicon body assemblies 10 arranged below the terminal protection region 2 in an inserted mode, the active region of the terminal electrons is effectively enlarged, all injection regions are connected into one piece, a graded junction with doping concentration changing in a certain gradient mode by taking the field limiting ring injection region as the center is formed, meanwhile, the depth of the field limiting ring injection region far away from the active region 1 is gradually increased, when the device is reversely biased, the field limiting ring injection region of the terminal protection region 2 is consumed completely due to the increase of the depth of the field limiting ring injection region, the withstand voltage capability of a device terminal is greatly improved, meanwhile, the capacity of the field limiting ring injection region is improved in a mode with unequal depths, the chip is prevented from being stretched, the occupied area of the chip is reduced, and the cost is reduced.
The above description is only a preferred embodiment of the present utility model, and the protection scope of the present utility model is not limited to the above examples, and all technical solutions belonging to the concept of the present utility model belong to the protection scope of the present utility model. It should be noted that modifications and adaptations to the present utility model may occur to one skilled in the art without departing from the principles of the present utility model and are intended to be within the scope of the present utility model.
Claims (7)
1. The utility model provides a semiconductor terminal protection architecture, includes active region (1) and terminal protection zone (2), is provided with virtual dotted line that sets up between active region (1) and the terminal protection zone (2), and terminal protection zone (2) parcel formula sets up in the periphery of active region (1), a serial communication port, terminal protection zone (2) are provided with first semiconductor substrate (7), first semiconductor substrate (7) include first conductivity type drift region (8), field limit shielding insulating layer (9) and electrically conductive polycrystalline silicon body subassembly (10), field limit shielding insulating layer (9) parcel sets up the outside of electrically conductive polycrystalline silicon body subassembly (10), electrically conductive polycrystalline silicon body subassembly (10) are provided with a plurality of, and a plurality of electrically conductive polycrystalline silicon body subassembly (10) are in order transversely vertical distribution and are in inside first conductivity type drift region (8), a plurality of alternate between electrically conductive polycrystalline silicon body subassembly (10) and distribute the field limit and pour into the district into and be the ring-shaped and be provided with a plurality of, a plurality of field limit is pour into the upper strata and be the trapezoidal region of degree of depth limit and do not distribute in the field limit and wait.
2. The semiconductor terminal protection structure according to claim 1, characterized in that the first semiconductor substrate (7) further comprises a first conductivity type substrate (12) and a base metal access layer (13), the first conductivity type substrate (12) being arranged below the first conductivity type drift region (8), the base metal access layer (13) being arranged at the bottom of the first conductivity type substrate (12).
3. The semiconductor terminal protection structure according to claim 1, characterized in that the active region (1) is provided with a first conductivity type source region (4) and a second conductivity type region (5) at an upper portion, the first conductivity type source region (4) is provided at an upper portion of the second conductivity type region (5), and a source metal layer (3) is externally connected to the first conductivity type source region (4).
4. The semiconductor terminal protection structure according to claim 1, wherein the conductive polysilicon body assembly (10) comprises a conductive silicon body (101) and a first type conductive well region (102), the first type conductive well region (102) is circularly wrapped at the bottom of the conductive silicon body (101), and a field limiting shielding insulating layer (9) is arranged between the conductive silicon body (101) and the first type conductive well region (102) at intervals.
5. The semiconductor termination protection structure according to claim 1, characterized in that the first semiconductor substrate (7) further comprises an insulating dielectric layer laid on top of the conductive polysilicon body assembly (10).
6. The semiconductor terminal protection structure according to claim 1, wherein a second semiconductor substrate (6) is disposed at a lower portion of the active region (1), the second semiconductor substrate (6) includes a first conductive polysilicon (61) and a first insulating layer (62), the first conductive polysilicon (61) and the first insulating layer (62) are both provided with a plurality of first conductive polysilicon (61), and the plurality of first conductive polysilicon (61) are the same in size, and the plurality of first insulating layers (62) are the same in width, and the first insulating layer (62) is disposed at a bottom of the first conductive polysilicon (61) in a circular package.
7. The semiconductor termination protection structure according to claim 4, wherein the conductive polysilicon body assembly (10) is provided with a second type conductive well region (11) on the upper portion of the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322071884.7U CN220604695U (en) | 2023-08-03 | 2023-08-03 | Semiconductor terminal protection structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322071884.7U CN220604695U (en) | 2023-08-03 | 2023-08-03 | Semiconductor terminal protection structure |
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| CN220604695U true CN220604695U (en) | 2024-03-15 |
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| CN202322071884.7U Active CN220604695U (en) | 2023-08-03 | 2023-08-03 | Semiconductor terminal protection structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117912959A (en) * | 2024-03-20 | 2024-04-19 | 芯联集成电路制造股份有限公司 | Semiconductor device, preparation method thereof and electronic device |
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2023
- 2023-08-03 CN CN202322071884.7U patent/CN220604695U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117912959A (en) * | 2024-03-20 | 2024-04-19 | 芯联集成电路制造股份有限公司 | Semiconductor device, preparation method thereof and electronic device |
| CN117912959B (en) * | 2024-03-20 | 2024-05-28 | 芯联集成电路制造股份有限公司 | Semiconductor device, preparation method thereof and electronic device |
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