CN110544718B - Silicon carbide MOS field effect transistor - Google Patents

Silicon carbide MOS field effect transistor Download PDF

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CN110544718B
CN110544718B CN201910850227.8A CN201910850227A CN110544718B CN 110544718 B CN110544718 B CN 110544718B CN 201910850227 A CN201910850227 A CN 201910850227A CN 110544718 B CN110544718 B CN 110544718B
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type base
base region
electrode
source
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CN110544718A (en
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张有润
李坤林
王帅
钟炜
陈航
杨啸
张波
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The invention relates to a silicon carbide MOS field effect transistor, belonging to the technical field of high-power semiconductors. The P-type base region of the MOSFET protrudes into the JFET region by 0.3um, and plays a role in shielding an electric field and protecting field oxygen when entering the JFET region in a reverse state. The highest field intensity of the gate oxide of the device is 1MV/cm, and the reliability of the gate oxide layer is effectively improved. In addition, the contact area of a grid electrode and a drain electrode is reduced by the P-type base region entering the JFET region, the grid-drain capacitance is reduced, and the reverse transmission capacitance of the device is 6.5pF/cm2Compared with the traditional structure, the high-frequency characteristic of the device is improved by 62 percent.

Description

Silicon carbide MOS field effect transistor
Technical Field
The invention belongs to the technical field of high-power semiconductors, and particularly relates to a silicon carbide MOS field effect transistor.
Background
The critical breakdown electric field of SiC is about 10 times that of Si material, so the pressure resistance of the SiC is much higher than that of a silicon-based device, the thermal conductivity of the SiC material is three times that of the Si, and the SiC material has good heat dissipation capability, so the SiC material is more suitable for being used in a high-temperature environment than the Si. Meanwhile, SiC is the only material capable of forming SiO2 by oxidation in all current compound semiconductor materials, which is very beneficial to manufacturing semiconductor devices such as MOS field effect transistors.
SiC MOSFET devices have many advantages not found in currently popular Si-based devices and may be suitable for more stringent application conditions. SiC MOSFETs have lower losses than Si IGBTs, and lower losses represent less heat generated by the chip, resulting in improved system efficiency. Meanwhile, the SiC chip area is getting smaller and smaller, and the size and number of heat dissipation elements are also reduced accordingly, such as reducing or even not using a heat dissipation fan, thereby reducing the size and weight of the whole power system. Therefore, the SiC MOSFET device has been widely used in high-voltage and high-efficiency converters due to its characteristics of low specific on-resistance, high operating frequency, stable operation at high temperature, and the like. Device loss is an important factor to be considered in a power system and is also a key factor which currently restricts the upper limit of the working frequency of the power system. In the SiC MOSFET, at a high frequency, it is necessary to reduce the reverse transfer capacitance and the gate-drain charge as much as possible in order to obtain a high-speed and low-loss performance. The present invention aims to reduce the switching losses of the device.
Disclosure of Invention
The invention aims to solve the technical problem in the prior art and provides a silicon carbide MOS field effect transistor.
In order to solve the above technical problem, an embodiment of the present invention provides a silicon carbide MOS field effect transistor, including a drain, an N + substrate, an N-drift region, a first P-type base region, a second P-type base region, a first N + source region, a second N + source region, a JFET region, a first gate dielectric, a second gate dielectric, a first gate electrode, a second gate electrode, a first source, a second source, and a schottky electrode;
the drain electrode, the N + substrate and the N-drift region are sequentially stacked from bottom to top, and the first P-type base region and the second P-type base region are respectively positioned at two ends above the N-drift region; the first N + source region is positioned on the partial upper layer of the first P-type base region, and the second N + source region is positioned on the partial upper layer of the second P-type base region; the first source electrode is positioned at one end above the first P-type base region, the first gate dielectric is positioned on the first N + source region, the second source electrode is positioned at one end above the second P-type base region, and the second gate dielectric is positioned on the second N + source region; the first gate dielectric and the second gate dielectric are respectively provided with a first gate electrode and a second gate electrode;
the JFET region is positioned on the N-drift region between the first P-type base region and the second P-type base region; the Schottky electrode is positioned on the JFET area;
the first P-type base region and the second P-type base region respectively protrude into the JFET region by 0.3 um.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, the JFET region is also located on the first P-type base region and the second P-type base region.
Further, the first gate electrode and the second gate electrode are polysilicon gates.
Further, the first gate dielectric and the second gate dielectric are SiO2。
The invention has the beneficial effects that: the first P-type base region and the second P-type base region in the device respectively protrude into the JFET region by 0.3um, and when the device is in a reverse state, the first P-type base region and the second P-type base region protruding into the JFET region can play a role in shielding an electric field and protecting field oxygen. In addition, the P-type base region protruding into the JFET region reduces the contact area between the grid electrode and the drain electrode, the grid-drain capacitance can be reduced, the switching loss is reduced, and the high-frequency characteristic of the device is improved.
Drawings
FIG. 1 is a schematic structural diagram of a conventional split-gate MOSFET (SG-MOS);
FIG. 2 is a schematic structural diagram of a silicon carbide MOSFET (N-MOS) according to an embodiment of the present invention;
fig. 3 is a graph of reverse transfer capacitance versus drain-source voltage for a conventional split-gate MOSFET (SG-MOS) and a silicon carbide MOSFET (N-MOS) according to an embodiment of the present invention.
In the drawings, the components represented by the respective reference numerals are listed below:
1. the Schottky diode comprises a first gate dielectric, a second gate dielectric, a Schottky electrode, a first N + source region, a second P-type base region, a first N + source region 6, a first P-type base region 7, a first N + drift region 8, an N-drift region 9, a JFET region 10, an N + substrate 11, a first gate electrode 12, a second gate electrode 13, a first source electrode 14, a second source electrode 15 and a drain electrode.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 2, a silicon carbide MOS field effect transistor according to an embodiment of the present invention includes a drain 15, an N + substrate 10, an N-drift region 8, a first P-type base region 7, a second P-type base region 5, a first N + source region 6, a second N + source region 4, a JFET region 9, a first gate dielectric 1, a second gate dielectric 3, a first gate electrode 11, a second gate electrode 12, a first source 13, a second source 14, and a schottky electrode 2;
the drain electrode 15, the N + substrate 10 and the N-drift region 8 are sequentially stacked from bottom to top, and the first P-type base region 7 and the second P-type base region 5 are respectively located at two ends above the N-drift region 8; the first N + source region 6 is positioned on a partial upper layer of the first P-type base region 7, and the second N + source region 4 is positioned on a partial upper layer of the second P-type base region 5; the first source electrode 13 is located at one end above the first P-type base region 7, the first gate dielectric 1 is located on the first N + source region 6, the second source electrode 14 is located at one end above the second P-type base region 5, and the second gate dielectric 3 is located on the second N + source region 4; the first gate dielectric 1 and the second gate dielectric 3 are respectively provided with a first gate electrode 11 and a second gate electrode 12;
the JFET region 9 is positioned on the N-drift region 8 between the first P-type base region 7 and the second P-type base region 5; the schottky electrode 2 is located on the JFET region 9;
the first P-type base region 7 and the second P-type base region 5 respectively protrude into the JFET region by 0.3 um.
In the above embodiment, the first P-type base region 7 and the second P-type base region 5 respectively protrude into the JFET region by 0.3um, and when the JFET is in a reverse state, the first P-type base region 7 and the second P-type base region 5 protruding into the JFET region can play roles in shielding an electric field and protecting field oxygen. In addition, the contact area between the grid electrode and the drain electrode is reduced by protruding into the JFET, the grid-drain capacitance can be greatly reduced, the switching loss is reduced, and the high-frequency characteristic of the device is improved. The highest field intensity of the gate oxide of the device is 1MV/cm, the gate oxide is greatly protected, and the reverse transmission capacitance is 6.5pF/cm2Compared with the traditional structure, the structure is reduced by 62 percent, and the device is improvedHigh frequency characteristics of (1).
Optionally, the JFET region 9 is also located on the first P-type base region 7 and the second P-type base region 5. Compared with the JFET region 9 of the traditional device, the JFET region 9 of the device of the invention extends upwards for a part, and the extending height is 0.5 um.
Optionally, the first gate electrode 11 and the second gate electrode 12 are polysilicon gates.
Optionally, the first gate dielectric 1 and the second gate dielectric 3 are SiO2。
Fig. 3 is a graph comparing the reverse transfer capacitance with drain-source voltage variation of the conventional split gate structure (SG-MOS) shown in fig. 1 and the device of the present invention (N-MOS) shown in fig. 2, in which the solid line is a graph of the reverse transfer capacitance with drain-source voltage variation of the conventional split gate structure (SG-MOS) and the dotted line is a graph of the reverse transfer capacitance with drain-source voltage variation of the device of the present invention (N-MOS). The lower reverse transmission capacitance can effectively reduce the switching loss. The reverse transfer capacitance as a function of drain-source voltage is shown in the upper graph, which can be seen at VDSThe reverse transfer capacitance of the conventional split gate structure is 17.5pF/cm at 1800V2The reverse transmission capacitance of the device is 6.5pF/cm2This is because the contact area of the gate to drain of the device of the present invention is reduced, thereby reducing the gate to drain capacitance.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (3)

1. A silicon carbide MOS field effect transistor comprises a drain electrode (15), an N + substrate (10), an N-drift region (8), a first P-type base region (7), a second P-type base region (5), a first N + source region (6), a second N + source region (4), a JFET region (9), a first gate dielectric (1), a second gate dielectric (3), a first gate electrode (11), a second gate electrode (12), a first source electrode (13), a second source electrode (14) and a Schottky electrode (2);
the drain electrode (15), the N + substrate (10) and the N-drift region (8) are sequentially stacked from bottom to top, and the first P-type base region (7) and the second P-type base region (5) are respectively located at two ends above the N-drift region (8); the first N + source region (6) is positioned on the partial upper layer of the first P-type base region (7), and the second N + source region (4) is positioned on the partial upper layer of the second P-type base region (5); the first source electrode (13) is positioned at one end above the first P-type base region (7), the first gate dielectric (1) is positioned on the first N + source region (6), the second source electrode (14) is positioned at one end above the second P-type base region (5), and the second gate dielectric (3) is positioned on the second N + source region (4); the first gate dielectric (1) and the second gate dielectric (3) are respectively provided with a first gate electrode (11) and a second gate electrode (12);
the JFET region (9) is positioned on the N-drift region (8) between the first P-type base region (7) and the second P-type base region (5); the Schottky electrode (2) is located on the JFET region (9);
the device is characterized in that the first P-type base region (7) and the second P-type base region (5) respectively protrude into the JFET region by 0.3 um; the JFET region (9) is also positioned on the first P-type base region (7) and the second P-type base region (5), and the side surface of the JFET region is in contact with a gate medium.
2. Silicon carbide MOS field-effect transistor according to claim 1, characterized in that the first gate electrode (11) and the second gate electrode (12) are polysilicon gates.
3. Silicon carbide MOS field effect transistor according to claim 1, characterized in that the first gate dielectric (1) and the second gate dielectric (3) are SiO2。
CN201910850227.8A 2019-09-10 2019-09-10 Silicon carbide MOS field effect transistor Active CN110544718B (en)

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CN111223937B (en) * 2020-01-17 2021-04-23 电子科技大学 GaN longitudinal field effect transistor with integrated freewheeling diode

Citations (2)

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Publication number Priority date Publication date Assignee Title
CN106784008A (en) * 2017-01-22 2017-05-31 北京世纪金光半导体有限公司 A kind of SiC MOSFET elements of integrated schottky diode
US20170301764A1 (en) * 2015-08-19 2017-10-19 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device

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JPS6038877A (en) * 1983-08-12 1985-02-28 Hitachi Ltd Insulated gate semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170301764A1 (en) * 2015-08-19 2017-10-19 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
CN106784008A (en) * 2017-01-22 2017-05-31 北京世纪金光半导体有限公司 A kind of SiC MOSFET elements of integrated schottky diode

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