CN216213475U - Shielding gate groove type power MOSFET device - Google Patents
Shielding gate groove type power MOSFET device Download PDFInfo
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- CN216213475U CN216213475U CN202122478254.2U CN202122478254U CN216213475U CN 216213475 U CN216213475 U CN 216213475U CN 202122478254 U CN202122478254 U CN 202122478254U CN 216213475 U CN216213475 U CN 216213475U
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Abstract
The utility model provides a shielded gate trench type power MOSFET device, which comprises a substrate, wherein an epitaxial layer is formed on the substrate; the groove is positioned in the epitaxial layer and extends along the thickness direction of the epitaxial layer, the upper space of the groove is provided with a polycrystalline silicon grid, and the lower space of the groove is provided with a shielding grid; the first dielectric layer is positioned inside the groove and wraps the shielding gate; the first dielectric layer corresponding to the middle position of the shielding grid comprises a first oxide layer, a nitride layer and a second oxide layer which are sequentially arranged along the side wall of the groove. The first dielectric layer corresponding to the middle position of the shielding grid is arranged into a laminated structure, so that the dielectric constant is improved, the source-drain capacitance is increased, more charges can be consumed under the same withstand voltage, the doping concentration of an epitaxial layer is improved, the on-resistance of a unit area is reduced, the chip area is saved, and the low-power driving circuit is very beneficial to low-power driving, power amplification application and medium-low frequency switch application.
Description
Technical Field
The utility model relates to the field of semiconductor device manufacturing, in particular to a shielded gate trench type power MOSFET device.
Background
With the increasing demand of consumer electronics, the demand of power MOSFETs is increasing, for example, in disk drives, automotive electronics, and power devices. The trench mosfet (trench mos) has a low switching loss and a high switching speed due to its high integration level, low on-resistance, low gate-drain charge density, and large current capacity, and is widely used in the low-voltage power field.
As shown in fig. 1, a trench 11 is formed in an epitaxial layer 10 of a conventional shielded gate trench type power MOSFET, and a gate-drain capacitance is completely converted into a source-drain capacitance by a shielded gate structure, so that the gate-drain capacitance is eliminated. In addition, in an off state (the grid source end is connected with 0 potential), because the bottom shielding grid dielectric layer exists, the transverse depletion is generated, and the breakdown voltage BV is improved.
As shown in fig. 1, as a dielectric layer 13 between a shield gate (also commonly referred to as Source poly) 12 and an epitaxial layer 10(EPI) of the shield gate trench type power MOSFET, the higher the dielectric constant is, the larger Cds (Source-drain capacitance) is, and more charges can be consumed under the same withstand voltage, so that the EPI with more concentrated doping can be adopted, thereby reducing the on-Resistance (RSP) per unit area, and further achieving the target parameters with a smaller chip area; when the on-resistance is maintained constant, Cds increases by 50% or more, and Cgd (gate-drain capacitance) and Cgs (gate-source capacitance) can be reduced to the inverse of the factor by which the dielectric constant increases, but Cds (source-drain capacitance) does not increase in reverse in comparison, which increases Qds (output charge) and increases the switching loss. The prior art is a dielectric of single dielectric constant (SiO)2) Or two dielectric constant media (SiO)2And Si3N4) As a dielectric layer between the shielding grid and the epitaxial layer EPI, the structure design is not reasonable, or the output capacitance is too large, or the withstand voltage is not high enough, or the on-resistance is not small enough.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a shielded gate trench type power MOSFET device, which is used for reducing the on-resistance of unit area and saving the chip area.
To achieve the above object, the present invention provides a shielded gate trench type power MOSFET device, comprising:
the substrate of the first conduction type, there is epitaxial layer of the first conduction type on the said substrate;
the groove is positioned in the epitaxial layer and extends along the thickness direction of the epitaxial layer, a polycrystalline silicon grid is arranged in the upper space of the groove, and a shielding grid is arranged in the lower space of the groove;
the first dielectric layer is positioned in the groove and wraps the shielding gate so as to isolate the shielding gate from the epitaxial layer and the polycrystalline silicon grid;
the first dielectric layer corresponding to the middle position of the shielding grid comprises a first oxide layer, a nitride layer and a second oxide layer which are sequentially arranged along the side wall of the groove.
Optionally, the intermediate position comprises a height 1/4 to 3/4 of the shielding grid.
Optionally, the doping concentration of the epitaxial layer corresponding to the middle position of the shielding gate is greater than the doping concentration of the epitaxial layer corresponding to the lower position and the bottom position of the shielding gate.
Optionally, the doping concentration of the epitaxial layer corresponding to the upper position of the shielding gate is less than the doping concentration of the epitaxial layer corresponding to the lower position and the bottom position of the shielding gate.
Optionally, the first dielectric layer corresponding to the middle position of the shielding gate includes a third oxide layer, and the first oxide layer, the second oxide layer, and the third oxide layer are made of the same material.
Optionally, the first oxide layer, the second oxide layer, and the third oxide layer are made of silicon oxide, and the nitride layer is made of silicon nitride.
Optionally, a lateral cross-sectional width of the nitride layer is greater than a lateral cross-sectional width of the first oxide layer or the second oxide layer.
Optionally, the first conductivity type includes an N-type, and the second conductivity type includes a P-type; alternatively, the first conductivity type includes a P-type, and the second conductivity type includes an N-type.
Optionally, the trench further includes a second dielectric layer located on a sidewall of the polysilicon gate.
Optionally, the method further includes:
the body region of the second conduction type is positioned in the epitaxial layer of the first conduction type and is positioned at the periphery of the second dielectric layer;
and the source region of the first conduction type is positioned in the epitaxial layer of the first conduction type, positioned at the periphery of the second dielectric layer and positioned above the body region of the second conduction type.
Optionally, the method further includes:
a gate electrode connected to the polysilicon gate;
a source electrode connected to the body region of the second conductivity type;
and the drain electrode is positioned on the lower surface of the substrate of the first conduction type.
In summary, in the shielded gate trench type power MOSFET device provided by the present invention, the first dielectric layer corresponding to the middle position of the shielded gate includes the first oxide layer, the nitride layer, and the second oxide layer sequentially disposed along the sidewall of the trench, and the first dielectric layer disposed in the stacked structure has a large dielectric constant, increases the source-drain capacitance, and can exhaust more charges under the same withstand voltage, so that a more heavily doped EPI can be used, the on-resistance per unit area is reduced, the chip area is saved, and the device is very beneficial to low-power driving, power amplification applications, and medium-low frequency switching applications.
Drawings
FIG. 1 is a schematic diagram of a shielded gate trench power MOSFET device;
fig. 2 is a schematic structural diagram of a shielded gate trench type power MOSFET device according to an embodiment of the present invention;
fig. 3a to 3d are radar maps based on the simulation data of table 1.
Description of reference numerals:
10-an epitaxial layer; 11-a trench; 12-a shielding grid; 13-a dielectric layer;
100-a substrate; 101-an epitaxial layer; 110-a trench; 120-a shielding grid; 140-polysilicon gate; 130-a first dielectric layer; 131 a-a first oxide layer; 131 b-a nitride layer; 131 c-a second oxide layer; 132-a third oxide layer; 141-body regions of a second conductivity type; 142-a source region of the first conductivity type; 150-a second dielectric layer; 160-interlayer dielectric layer; 171-metal contact vias; 170-source electrode; 180-drain electrode.
Detailed Description
The shielded gate trench type power MOSFET device of the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the concepts of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. The drawings are in simplified form and are not to scale, but are provided for convenience and clarity in describing embodiments of the utility model.
The terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the utility model described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.
Fig. 2 is a structural diagram of the shielded gate trench power MOSFET device provided in this embodiment. As shown in fig. 2, the shielded gate trench type power MOSFET device provided in this embodiment includes:
a substrate 100 of a first conductivity type, an epitaxial layer 101 of the first conductivity type being formed on the substrate 100;
a trench 110 located in the epitaxial layer 101 and extending along a thickness direction of the epitaxial layer 101, wherein a polysilicon gate 140 is disposed in an upper space of the trench 110, and a shield gate 120 is disposed in a lower space thereof;
a first dielectric layer 130 located inside the trench 110, wrapping the shield gate 120, and isolating the shield gate 120 from the epitaxial layer 101 and the polysilicon gate 140;
the first dielectric layer 130 corresponding to the middle of the shielding gate 120 includes a first oxide layer 131a, a nitride layer 131b, and a second oxide layer 131c sequentially disposed along the sidewall of the trench 110.
Specifically, in this embodiment, the first conductive type may include an N type, and in this case, the second conductive type may include a P type; accordingly, the first conductive type may include a P type, and at this time, the second conductive type may include an N type. The following description will be given taking an N-type shielded gate trench power MOSFET device as an example.
The first conductive type substrate 100 may include, but is not limited to, a silicon substrate, a silicon carbide substrate, or a silicon germanium substrate. Preferably, in this embodiment, the substrate 100 of the first conductivity type is a silicon substrate. Specifically, the first conductive type substrate 100 may be a substrate formed by performing ion implantation of a first conductive type to an intrinsic substrate. The epitaxial layer 101 of the first conductivity type may serve as a drift region.
The number of the grooves 110 may be one or multiple, where fig. 2 illustrates that the number of the grooves 110 is three, and in an actual example, the number of the grooves 110 is not limited thereto. The plurality of grooves 110 are arranged at intervals in a direction perpendicular to the direction in which the grooves 110 extend. The plurality of grooves 11 may be arranged at equal intervals or at unequal intervals.
The depth of the trench 110 may be set according to actual needs, preferably, the depth of the trench 110 is smaller than the thickness of the epitaxial layer 101 of the first conductivity type, the trench 110 may be a deep trench, and the aspect ratios of the trenches 110 may be all greater than 5:1, for example, the aspect ratio of the trench 11 may be greater than 15: 1.
The inner space of the trench 110 is divided into an upper half and a lower half, wherein the upper half is the polysilicon gate 140, and the lower half is the shield gate 120. The shielding gate 120 is wrapped by the first dielectric layer 130 at the lower half of the trench 110, and the shielding gate 120 is isolated from the epitaxial layer 101 and the polysilicon gate 140, that is, the first dielectric layer 130 is disposed on the upper portion (including the top), both sides, and the lower portion (including the bottom) of the shielding gate 120.
In this embodiment, the first dielectric layer 130 includes two portions, the first portion is the first dielectric layer 130 located in the middle of the shielding gate 120, and the second portion is the first dielectric layer 130 corresponding to a position different from the middle of the shielding gate, that is, the first dielectric layer 130 located in the upper portion and the lower portion of the shielding gate 120 is included, where the first dielectric layer located at the top of the shielding gate 120 may be used as an inter-gate insulating layer between the shielding gate 120 and the polysilicon gate 140. The second portion of the first dielectric layer 130 includes a third oxide layer 132, the materials of the first oxide layer 131a, the second oxide layer 131c and the third oxide layer 132 are the same, for example, the materials of the first oxide layer 131a, the second oxide layer 131c and the third oxide layer 132 are all silicon oxide, the material of the nitride layer 131b is silicon nitride, and preferably, the lateral cross-sectional width of the nitride layer 131b is greater than the lateral cross-sectional width of the first oxide layer 131a or the second oxide layer 131 c. In other embodiments of the present invention, the materials of the first oxide layer 131a, the second oxide layer 131c and the third oxide layer 132 may also be different, and are not limited herein.
The upper half of the trench 110 has a second dielectric layer 150 as a gate dielectric layer on its sidewall, and the thickness of the second dielectric layer 150 is much lower than that of the first dielectric layer 130. The material of the second dielectric layer 150 is the same as that of the third oxide layer 132 in the first dielectric layer 130, for example, the second dielectric layer 150 and the first dielectric layer 130 are fused and joined together, so as to isolate the shield gate 120 and the polysilicon gate 140 in the trench 110 from the epitaxial layer 101.
The shielded gate trench type power MOSFET device further includes a body region (P-body)141 of a second conductivity type and a source region (N-Plus)142 of a first conductivity type, the body region 141 of the second conductivity type being located within the epitaxial layer 101 of the first conductivity type, and the body region 141 of the second conductivity type being located at the periphery of the second dielectric layer 142, the source region (N-Plus)142 of the first conductivity type, the source region 142 of the first conductivity type being located within the epitaxial layer 101 of the first conductivity type, being located at the periphery of the second dielectric layer 150, and being located above the body region 142 of the second conductivity type.
The shielded gate trench type power MOSFET device further includes: a gate electrode (not shown) connected to the polysilicon gate 140, a source electrode 170, and a drain electrode 180; the source electrode 170 is connected to the body region 141 of the second conductivity type, for example, the source electrode 170 is connected to the body region 141 of the second conductivity type through a metal contact via 171 penetrating the interlayer dielectric layer 160; the drain electrode 180 is located on a lower surface of the first conductive type substrate 100. As an example, the source electrode 170, the gate electrode, and the drain electrode 180 may each include a metal electrode, for example, a copper electrode, an aluminum electrode, a gold electrode, a silver electrode, a nickel electrode, or the like.
In this embodiment, the middle position of the shielding grid 120 includes positions 1/4 to 3/4 of the height of the shielding grid 120, and preferably, the middle position is located at positions 1/3 to 2/3 of the height of the shielding grid 120.
The first dielectric layer 130 in the middle of the shielding gate 120 is a first oxide layer 131a, a nitride layer 131b, and a second oxide layer 131c sequentially disposed along the sidewall of the trench 110, and compared with a dielectric layer with a single dielectric constant, the dielectric constant is large, the depletion region has more charges under the same withstand voltage, and the acting force between the charges in units of the same distance is small, so that the peak value of an electric field is favorably suppressed, and thus, the advantages of withstand voltage and on-resistance are obtained, but Cds is a disadvantage, and the disadvantage is suppressed to a great extent due to the avoidance of the upper section of the shielding gate 120, and thus, the advantage is better than the single dielectric constant.
If the first dielectric layer 130 at the lower portion of the shielding gate 120 is the first oxide layer 131a, the nitride layer 131b, and the second oxide layer 131c sequentially disposed along the sidewall of the trench 110, although it is more beneficial to reduce Cds, and the acting force between unit charges at the same distance near two surfaces of the first dielectric layer is smaller, which is beneficial to suppress an electric field, the electric field is too high and the withstand voltage of the device is too low near the bottom of the trench 110 due to more depletion charges thereof under the same withstand voltage (increased by 1 time under the condition of the same dielectric thickness), which is not advantageous in terms of the overall performance of the device;
if the first dielectric layer 130 at the upper portion of the shielding gate 120 is disposed as the first oxide layer 131a, the nitride layer 131b, and the second oxide layer 131 sequentially disposed along the sidewall of the trench 110, although the acting force between the unit charges at the same distance near both sides of the first dielectric layer is smaller, which is not favorable for suppressing the electric field, the depletion charges are more (increased by 1 time under the same dielectric thickness) under the same withstand voltage, which results in a decrease in the electric field near the PN junction and an increase in the withstand voltage of the device, and the Cds is too large, which is also not advantageous from the overall performance of the device.
Due to the arrangement of the laminated structure of the first dielectric layer 130 at the middle position of the shielding gate 120 and the higher charge density in Si in the epitaxial layer near the middle position of the shielding gate 120, the epitaxial layer EPI2 corresponding to the middle position of the shielding gate 120 is allowed to have a higher doping. That is, the doping concentration of the epitaxial layer EPI2 corresponding to the middle position of the shield gate 120 is the highest among the three epitaxial layers (EPI1, EPI2, and EPI 3). That is, the doping concentration of the epitaxial layer EPI2 corresponding to the middle position of the shield gate 120 is greater than the doping concentration of the epitaxial layer EPI3 corresponding to the upper position of the shield gate 120 and the doping concentration of the epitaxial layer EPI1 corresponding to the lower position of the shield gate 120. And the doping concentration of the epitaxial layer EPI1 corresponding to the lower position of the shield gate 120 is greater than the doping concentration of the epitaxial layer EPI3 corresponding to the upper position of the shield gate 120.
In addition, compared with the first dielectric layer made of a single dielectric material in the conventional shielded gate trench type power MOSFET device, if the on-resistance is kept unchanged, Cds in the shielded gate trench type power MOSFET device provided by the embodiment is greatly reduced, Cgd and Cgs can be reduced to be close to the reciprocal multiple of the increased multiple of the dielectric constant, and therefore the shielded gate trench type power MOSFET device has great advantages.
Table 1 is simulation data for simulations of the conventional shielded gate trench power MOSFET device structure (fig. 1) and the shielded gate trench power MOSFET device structure provided in this example (fig. 2). Fig. 3a to 3d are radar plots (values in the plots represent the multiples optimized for the parameters) based on the simulation data of table 1. Referring to table 1 and fig. 3a to 3d, it can be seen that compared to the conventional shielded gate trench power MOSFET device, the Cds of the shielded gate trench power MOSFET device provided in the present embodiment has been reduced much if the on-resistance is maintained unchanged, and Cgd and Cgs can be reduced to about the reciprocal of the increase of the dielectric constant. In addition, the layout (located in the middle of the shield gate) of the two dielectric constant material layers (the first and second oxide layers and the nitride layer) in the first dielectric layer in the structure of the shield gate trench type power MOSFET device provided by this embodiment is optimal.
TABLE 1
According to the simulation design (FIG. 2, RSP is 8m omega. mm)2) Data, same Breakdown Voltage (BV) and on-resistance (Ron) compared to the currently optimal conventional structure (FIG. 1, RSP 11.3m Ω. mm)2) The chip Area (Area) can be saved by 30%, the input capacitance (ciss) and the reverse transfer capacitance (crss) can be reduced by more than 50%, but the output capacitance (coss) is increased by about 80% due to the disadvantage of the high-k dielectric, as shown in fig. 3a and 3 b; if compared under the same withstand voltage (BV) and chip Area (Area), the on-resistance (Ron) is reduced by 30%, the input capacitance (ciss) is reduced by 35%, the reverse transfer capacitance (crss) is reduced by 50%, and the output capacitance (coss) is increased by about 120%, as shown in fig. 3c and 3 d. The SGT structure with high dielectric constant medium provided in this embodiment is not suitable for low power driving, power amplification application, and low and medium frequency switch application, in which the output capacitance is well optimizedIt is often advantageous. If the voltage is the same as the conventional voltage-resistant common conventional structure (RSP is about 16m omega mm)2) Compared with the prior art, the chip area can be saved by 50%, the capacitance reduction rate is higher, the output capacitance increase rate is lower (the increase rate under the same on-resistance is about 20%), and the advantages are more obvious.
In summary, the utility model provides a shielded gate trench type power MOSFET device, which includes a substrate, wherein an epitaxial layer is formed on the substrate; the groove is positioned in the epitaxial layer and extends along the thickness direction of the epitaxial layer, the upper space of the groove is provided with a polycrystalline silicon grid, and the lower space of the groove is provided with a shielding grid; the first dielectric layer is positioned inside the groove and wraps the shielding gate; the first dielectric layer corresponding to the middle position of the shielding grid comprises a first oxide layer, a nitride layer and a second oxide layer which are sequentially arranged along the side wall of the groove. The first dielectric layer corresponding to the middle position of the shielding grid is arranged into a laminated structure, so that the dielectric constant is improved, the source-drain capacitance is increased, more charges can be consumed under the same withstand voltage, the doping concentration of an epitaxial layer is improved, the on-resistance of a unit area is reduced, the chip area is saved, and the low-power driving circuit is very beneficial to low-power driving, power amplification application and medium-low frequency switch application.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (9)
1. A shielded gate trench power MOSFET device comprising:
the substrate of the first conductivity type, there is epitaxial layer of the first conductivity type on the said substrate;
the groove is positioned in the epitaxial layer and extends along the thickness direction of the epitaxial layer, a polycrystalline silicon grid is arranged in the upper space of the groove, and a shielding grid is arranged in the lower space of the groove;
the first dielectric layer is positioned in the groove, wraps the shielding gate and isolates the shielding gate from the epitaxial layer and the polycrystalline silicon grid;
the first dielectric layer corresponding to the middle position of the shielding gate comprises a first oxide layer, a nitride layer and a second oxide layer which are sequentially arranged along the side wall of the groove.
2. The shielded gate trench power MOSFET of claim 1 wherein the intermediate position comprises a height of the shielded gate from 1/4 to 3/4.
3. The shielded gate trench power MOSFET of claim 1 wherein the doping concentration of the epitaxial layer corresponding to the middle position of the shielded gate is greater than the doping concentration of the epitaxial layer corresponding to the lower position of the shielded gate.
4. The shielded gate trench power MOSFET of claim 3 wherein the doping concentration of the epitaxial layer corresponding to the upper position of the shielded gate is less than the doping concentration of the epitaxial layer corresponding to the lower position of the shielded gate.
5. The shielded gate trench power MOSFET of claim 1 wherein the first dielectric layer opposite the center of the shielded gate comprises a third oxide layer, and the first, second, and third oxide layers are made of the same material.
6. The shielded gate trench power MOSFET of claim 1 wherein the nitride layer has a lateral cross-sectional width greater than a lateral cross-sectional width of the first oxide layer or the second oxide layer.
7. The shielded gate trench power MOSFET of claim 1 further including a second dielectric layer in the trench on the sidewall of the polysilicon gate.
8. The shielded gate trench power MOSFET device of claim 7 further comprising:
the body region of the second conduction type is positioned in the epitaxial layer of the first conduction type and is positioned at the periphery of the second dielectric layer;
the source region of the first conduction type is positioned in the epitaxial layer of the first conduction type, positioned at the periphery of the second dielectric layer and positioned above the body region of the second conduction type;
the first conductivity type comprises an N-type and the second conductivity type comprises a P-type; alternatively, the first conductivity type includes a P-type, and the second conductivity type includes an N-type.
9. The shielded gate trench power MOSFET device of claim 8 further comprising:
a gate electrode connected to the polysilicon gate;
a source electrode connected to the body region of the second conductivity type;
and the drain electrode is positioned on the lower surface of the substrate of the first conduction type.
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