CN111969040B - Super junction MOSFET - Google Patents

Super junction MOSFET Download PDF

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Publication number
CN111969040B
CN111969040B CN202010869506.1A CN202010869506A CN111969040B CN 111969040 B CN111969040 B CN 111969040B CN 202010869506 A CN202010869506 A CN 202010869506A CN 111969040 B CN111969040 B CN 111969040B
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type semiconductor
region
conductivity
conductivity type
doped
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CN111969040A (en
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任敏
郭乔
蓝瑶瑶
李吕强
高巍
李泽宏
张金平
张波
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

Abstract

The invention belongs to the technical field of power semiconductors, and relates to a super junction MOSFET. According to the super junction MOSFET device, the second conductive type semiconductor columns with gradually changing lengths and gradually changing concentrations are introduced into the drift region, the length of the voltage-resistant columns close to the JFET region is reduced to avoid lateral depletion of the adjacent voltage-resistant columns, Cgd capacitance caused by longitudinal expansion is rapidly reduced, the minimum point on a Cgd-Vds curve is moved to the direction of larger Vds, the Cgd capacitance value is raised when the Vds is smaller, and the Cgd-Vds curve is flatter. Therefore, the switching time can be accelerated, the switching power consumption can be reduced, the switching oscillation can be reduced, the EMI can be relieved, and the dynamic characteristic of the super junction device can be improved.

Description

Super junction MOSFET
Technical Field
The invention belongs to the technical field of power semiconductors, and relates to a super-junction MOSFET.
Background
The power super-junction MOSFET structure utilizes the P columns and the N columns which are mutually alternated to replace an N drift region of a traditional power device, so that the on-resistance is effectively reduced, and the lower on-power consumption is obtained. Due to the characteristics of unique high input impedance, low driving power, high switching speed, excellent frequency characteristic, good thermal stability and the like, the high-frequency-stability high-frequency-power-stability switching power supply is widely applied to various fields such as switching power supplies, automobile electronics and motor driving. A conventional superjunction MOSFET structure is shown in fig. 1.
The capacitive characteristics are critical to the turn-on and turn-off process of the power superjunction device. The curves of the gate-drain capacitances Cgd and Vds affect the switching speed and emi (electromagnetic interference) characteristics of the device. If the Cgd curve has a large steep drop, the super junction device is more likely to have voltage oscillation and current oscillation during the switching process, which causes EMI noise to damage surrounding equipment.
Disclosure of Invention
Aiming at the problems, the invention provides a super junction MOSFET device with improved dynamic characteristics, which enables the minimum point on the Cgd-Vds curve to move towards the direction of larger Vds on the premise of not influencing the voltage resistance of the device, so that the Cgd is increased under low leakage voltage, the Cgd-Vds curve is flatter, and the purposes of increasing the switching speed, reducing the switching power consumption, reducing the switching oscillation and relieving EMI (electro-magnetic interference) are achieved, thereby improving the dynamic characteristics of the super junction device.
The technical scheme of the invention is as follows: a super junction MOSFET, as shown in FIG. 2, comprises a metalized drain 1, a heavily doped first conductivity type semiconductor substrate 2 located above the metalized drain 1, a lightly doped first conductivity type semiconductor region 3 located above the first conductivity type semiconductor substrate 2; the two sides of the top of the lightly doped first conductive type semiconductor region 3 are provided with second conductive type semiconductor body regions 5; a first-conductivity-type lightly-doped JFET (junction field effect transistor) region 8 is arranged between the second-conductivity-type semiconductor body regions 5; the second conductive type semiconductor body region 5 is provided with a second conductive type semiconductor heavily-doped contact region 6 and a first conductive type semiconductor source region 7, and the second conductive type semiconductor body region 5 between the first conductive type semiconductor source region 7 and the first conductive type lightly-doped JFET region 8 is a channel region; the heavily doped polysilicon electrode 10 covers the channel region and the first conductivity type JFET region 8; the heavily doped polysilicon electrode 10 is separated from the channel region and the JFET region 8 by a gate oxide layer 9; the upper surface of the second conductive type semiconductor heavily doped contact region 6 and part of the upper surface of the first conductive type semiconductor source region 7 are in direct contact with the metalized source electrode 11; the metalized source 11 and the polysilicon electrode 10 are electrically isolated by an insulating medium layer. The bottom of the second conductivity type semiconductor body 5 also has 2 or more second conductivity type semiconductor pillars 41, 42.... 4n (n is 2 or more), the top of the second conductivity type semiconductor pillars 41, 42.. 4n is in contact with the second conductivity type semiconductor body 5, and the side faces of adjacent second conductivity type semiconductor pillars 41, 42.. 4n are in contact with each other. The lengths and doping concentrations of the second conductivity type semiconductor pillars 41, 42 are successively decreased from the direction away from the JFET region 8 to the direction close to the JFET region 8.
Further, the total amount of impurities of the second-conductivity- type semiconductor pillars 41, 42.
Further, the gate oxide layer 9 is made of one of silicon oxide, silicon nitride, silicon oxynitride, and lead oxide.
The invention has the beneficial effects that: the second conductive type semiconductor columns with gradually changed lengths and gradually changed concentrations are introduced into the drift region, the length of the voltage-resistant columns close to the JFET region is reduced to avoid lateral depletion of adjacent voltage-resistant columns, Cgd capacitance is rapidly reduced due to longitudinal expansion, the minimum point on a Cgd-Vds curve is moved to the direction of larger Vds, the Cgd capacitance value is raised when the Vds is smaller, and the Cgd-Vds curve is flatter. Therefore, the switching time can be accelerated, the switching power consumption can be reduced, the switching oscillation can be reduced, the EMI can be relieved, and the dynamic characteristic of the super junction device can be improved.
Drawings
Fig. 1 is a front view of the structure of a conventional super junction MOSFET;
fig. 2 is a front view of a super junction MOSFET structure of the present invention;
fig. 3 is a front view of a super junction MOSFET structure of embodiment 2;
fig. 4 is a schematic diagram of Cgd of a conventional superjunction device at low drain voltage;
fig. 5 is a comparison of depletion layer simulations for a conventional superjunction MOSFET structure (a) and a superjunction MOSFET structure (b) of the present invention when Vds is 7V;
fig. 6 is a comparison of depletion layer simulations for a conventional superjunction MOSFET structure (a) and a superjunction MOSFET structure (b) of the present invention when Vds is 20V;
fig. 7 is a comparison of Cgd-Vds curves simulation for a conventional superjunction MOSFET structure (a) and a superjunction MOSFET structure (b) of the present invention;
fig. 8 is a comparison of drain turn-off voltage simulations for a conventional superjunction MOSFET structure (a) and a superjunction MOSFET structure (b) of the present invention.
Description of reference numerals: the structure of the transistor comprises a metalized drain electrode 1, a first conductive type semiconductor substrate 2, a first conductive type semiconductor lightly doped epitaxial layer 3, second conductive type semiconductor columns 41 and 42, a second conductive type semiconductor body region 5, a second conductive type semiconductor heavily doped contact region 6, a first conductive type semiconductor source region 7, a JFET region 8, a gate oxide layer 9, a polysilicon electrode 10 and a metalized source electrode 11.
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and embodiments:
example 1
As shown in fig. 2, comprises a metalized drain 1, a heavily doped first conductive type semiconductor substrate 2 located above the metalized drain 1, and a lightly doped first conductive type semiconductor region 3 located above the first conductive type semiconductor substrate 2; the two sides of the top of the lightly doped first conductive type semiconductor region 3 are provided with second conductive type semiconductor body regions 5; a first-conductivity-type lightly-doped JFET (junction field effect transistor) region 8 is arranged between the second-conductivity-type semiconductor body regions 5; the second conductive type semiconductor body region 5 is provided with a second conductive type semiconductor heavily-doped contact region 6 and a first conductive type semiconductor source region 7, and the second conductive type semiconductor body region 5 between the first conductive type semiconductor source region 7 and the first conductive type lightly-doped JFET region 8 is a channel region; the heavily doped polysilicon electrode 10 covers the channel region and the first conductivity type JFET region 8; the heavily doped polysilicon electrode 10 is separated from the channel region and the JFET region 8 by a gate oxide layer 9; the upper surface of the second conductive type semiconductor heavily doped contact region 6 and part of the upper surface of the first conductive type semiconductor source region 7 are in direct contact with the metalized source electrode 11; the metalized source 11 and the polysilicon electrode 10 are electrically isolated by an insulating medium layer. The bottom of the second conductivity type semiconductor body 5 also has 2 or more second conductivity type semiconductor pillars 41, 42.... 4n (n is 2 or more), the top of the second conductivity type semiconductor pillars 41, 42.. 4n is in contact with the second conductivity type semiconductor body 5, and the side faces of adjacent second conductivity type semiconductor pillars 41, 42.. 4n are in contact with each other. The lengths and doping concentrations of the second conductivity type semiconductor pillars 41, 42 are successively decreased from the direction away from the JFET region 8 to the direction close to the JFET region 8. The total amount of impurities of the second-conductivity- type semiconductor pillars 41, 42.. 4n and the total amount of impurities of the lightly-doped first-conductivity-type semiconductor region 3 satisfy the charge balance.
The working principle of the embodiment is as follows:
for the conventional super junction device, under a smaller drain-source voltage Vds, PN junctions formed by the lightly doped second conductivity type body region and the lightly doped first conductivity type epitaxial layer are mutually depleted, the width of a depletion layer between a gate and a drain determines the size of a depletion layer capacitor, and a schematic diagram of the Cgd capacitor under a low drain voltage is shown in fig. 4. For the conventional super junction MOSFET, since PN junctions formed by the lightly doped second conductivity type breakdown pillars and the adjacent first conductivity type breakdown pillars are laterally depleted from each other, when Vds is small, as shown in fig. 5(a) and 6(a), their lateral depletion layers rapidly merge to cause longitudinal broadening of the depletion layer, so that the value of Cgd rapidly decreases, resulting in a severe steep drop of the Cgd-Vds curve, as shown in fig. 7 (a). According to the structure provided by the invention, the voltage-resistant column with gradually changed length and concentration is introduced into the drift region, so that the charge balance of the voltage-resistant column is maintained, and the voltage-resistant characteristic is not reduced. By reducing the length of the voltage-resistant column close to the JFET area to avoid lateral depletion of the adjacent voltage-resistant columns, the Cgd capacitance caused by longitudinal expansion is rapidly reduced, and as shown in FIGS. 5(b) and 6(b), under the same Vds, compared with the traditional super-junction MOSFET, the structure provided by the patent has the advantages that the width of a depletion layer between the grid electrode and the drain electrode is shorter, and the value of Cgd is larger. It can be seen that the gradual-change pressure-resistant column provided by the patent can make the corresponding Vds value larger when Cgd is minimum, and raise the Cgd capacitance value when Vds is smaller, so that the Cgd-Vds curve is flatter, as shown in fig. 7 (b). The inductive load switch simulation is carried out under the condition that the drain power supply voltage Vdd is 400V, the oscillation condition of the drain voltage is shown in figure 8, and the structure provided by the patent can effectively reduce the voltage oscillation and the current oscillation of the super-junction MOSFET device during switching, thereby inhibiting the EMI electromagnetic radiation noise in a switch loop.
In the implementation process, certain flexible design can be performed under the condition that the basic structure is not changed according to specific conditions. When the device is manufactured, the silicon can be replaced by semiconductor materials such as silicon carbide, gallium arsenide, indium phosphide or silicon germanium and the like.
Example 2
As shown in fig. 3, on the basis of embodiment 1, the bottom of second conductivity type semiconductor body 5 is determined to be 3 second conductivity type semiconductor pillars 41, 42, and 43, the tops of second conductivity type semiconductor pillars 41, 42, and 43 are in contact with second conductivity type semiconductor body 5, and the side faces of adjacent second conductivity type semiconductor pillars 41, 42, and 43 are in contact with each other. 41. 42 and 43 are successively decreased in length and doping concentration. It is also characterized in that the total amount of impurities of the second conductivity- type semiconductor columns 41, 42, and 43 and the total amount of impurities of the lightly doped first conductivity-type semiconductor region 3 satisfy charge balance.

Claims (3)

1. A super junction MOSFET comprises a metalized drain (1), a heavily doped first conductivity type semiconductor substrate (2) located above the metalized drain (1), and a lightly doped first conductivity type semiconductor region (3) located above the heavily doped first conductivity type semiconductor substrate (2); the two sides of the top of the lightly doped first conductive type semiconductor region (3) are provided with second conductive type semiconductor body regions (5); a first-conductivity-type lightly-doped JFET (8) region is arranged between the second-conductivity-type semiconductor bodies (5); the second conductive type semiconductor body region (5) is provided with a second conductive type semiconductor heavily-doped contact region (6) and a first conductive type semiconductor source region (7) which are arranged in parallel, and the second conductive type semiconductor body region (5) between the first conductive type semiconductor source region (7) and the first conductive type lightly-doped JFET region (8) is a channel region; a heavily doped polysilicon electrode (10) covers the channel region, the first conductivity type JFET region (8) and part of the upper surface of the first conductivity type semiconductor source region (7); the heavily doped polysilicon electrode (10) is isolated from the first conductivity type semiconductor source region (7), the channel region and the JFET region (8) by a gate oxide layer (9); the upper surface of the second conductive type semiconductor heavily-doped contact region (6) and part of the upper surface of the first conductive type semiconductor source region (7) are in direct contact with the metalized source electrode (11); the metalized source electrode (11) is electrically isolated from the polysilicon electrode (10) by an insulating medium layer; the semiconductor device is characterized in that the bottom of the second conductivity type semiconductor body region (5) is also provided with a plurality of second conductivity type semiconductor columns, the tops of the second conductivity type semiconductor columns are contacted with the second conductivity type semiconductor body region (5), and the side faces of the adjacent second conductivity type semiconductor columns are contacted; the length and the doping concentration of the second-conductivity-type semiconductor columns are sequentially decreased from one end far away from the first-conductivity-type lightly-doped JFET region (8) to one end close to the first-conductivity-type lightly-doped JFET region (8).
2. The super junction MOSFET according to claim 1, wherein a total amount of impurities of the plurality of second conductivity type semiconductor pillars and a total amount of impurities of the lightly doped first conductivity type semiconductor region (3) satisfy a charge balance.
3. The super junction MOSFET of claim 2 wherein said first conductivity type semiconductor is an n-type semiconductor and said second conductivity type semiconductor is a p-type semiconductor; or the first conductivity type semiconductor is a p-type semiconductor and the second conductivity type semiconductor is an n-type semiconductor.
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CN107482060A (en) * 2016-06-08 2017-12-15 深圳尚阳通科技有限公司 Superjunction devices and its manufacture method

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CN107482060A (en) * 2016-06-08 2017-12-15 深圳尚阳通科技有限公司 Superjunction devices and its manufacture method

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