CN109713041B - Improved structure suitable for super junction DMOS device - Google Patents
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Abstract
The invention discloses an improved structure suitable for a super-junction DMOS device, which belongs to the technical field of optimization of electronic devices, wherein a heavily doped second conductive type semiconductor island region is also arranged on the contact surface of a first conductive type semiconductor doping substrate and a metalized drain of the super-junction DMOS device, the heavily doped second conductive type semiconductor island region forms a device bottom hole injection region, and the heavily doped second conductive type semiconductor island region is embedded in the first conductive type semiconductor doping substrate and the bottom of the heavily doped second conductive type semiconductor island region is also contacted with the upper surface of the metalized drain; and the carrier lifetime of the lower half area of the first conductive type doped column area and the second conductive type semiconductor doped column area is longer than that of the upper half area.
Description
Technical Field
The invention belongs to the technical field of optimization of electronic devices, and particularly relates to an improved structure suitable for a super junction DMOS device.
Background
The power DMOS has advantages of fast switching speed, low loss, high input impedance, low driving power, good frequency characteristics, etc., and thus plays an important role in power conversion, particularly in high-frequency power conversion. The ever-increasing system performance requires power DMOS to have lower power losses and also higher reliability under high electrical stress. A DMOS device having a super-junction structure is an important power device appearing in recent years, and its basic principle is a charge balance principle, and by introducing a super-junction structure of P columns and n columns spaced from each other in a drift region of a common power DMOS, a trade-off relationship between on-resistance and breakdown voltage of the common DMOS is greatly improved, and thus the DMOS device is widely applied to a power system.
In the prior art, for example, chinese patent publication No. CN107248532A entitled "a super junction DMOS device" provides a super junction DMOS device including a metalized drain electrode, a first conductivity type semiconductor doped substrate, a first conductivity type doped column region, a second conductivity type semiconductor doped column region, a polysilicon gate electrode, a gate dielectric layer, and a metalized source electrode; the metalized drain electrode is positioned on the lower surface of the first conductive type semiconductor doped substrate; the first conductive type doped column region and the second conductive type semiconductor doped column region are positioned on the upper surface of the first conductive type semiconductor doped substrate; a first conductive type doping area with low doping is arranged right above the first conductive type doping column area; the second conductive type semiconductor doped column region is positioned at two sides of the first conductive type doped column region and forms a super junction structure with the first conductive type doped column region; the top of the second conductive type semiconductor doping column region is provided with a second conductive type semiconductor body region which is respectively contacted with the second conductive type semiconductor doping column region and the low-doped first conductive type doping region; the upper layer of the second conductive type semiconductor body region is provided with a first conductive type semiconductor doping source region and a second conductive type semiconductor doping contact region which are mutually independent, wherein the first conductive type semiconductor doping source region is positioned at one side close to the low-doped first conductive type doping region; the polycrystalline silicon gate electrode is positioned on the upper surfaces of the second conductive type semiconductor body region and the low-doped first conductive type doped region and is insulated from the second conductive type semiconductor body region and the low-doped first conductive type doped column region through a gate dielectric layer; the metalized source electrode is positioned on the uppermost layer of the device, and the lower surface of the metalized source electrode covers the second conductive type semiconductor doped contact area, the upper surface of part of the first conductive type semiconductor doped source area, the upper surface and the side surface of the gate dielectric layer; the first conductive type semiconductor doping column region is provided with a first conductive type semiconductor doping column region, the first conductive type semiconductor doping column region is provided with a second conductive type semiconductor body region, the second conductive type semiconductor doping column region is provided with a first conductive type semiconductor doping column region, the first conductive type semiconductor doping column region is provided with a second conductive type semiconductor doping column region, the second conductive type semiconductor doping column region is provided with a second conductive type semiconductor doping column region, the first conductive type semiconductor doping column region is provided with a first conductive type semiconductor doping column region and a second conductive type semiconductor region, the first conductive type semiconductor doping column region is provided with a first conductive type semiconductor doping column region; the vertical length of the dielectric layer structure is shorter than that of the second conductive type semiconductor doped column region, and the low-doped first conductive type doped region means that the doping concentration of the first conductive type doped region is lower than that of the first conductive type doped column region; the lateral surface of a second conductive type doped column region of the super junction structure is provided with a dielectric layer structure to fix an avalanche breakdown point of the super junction DMOS device, and meanwhile, the doping concentration of the top of the second conductive type doped column region of the super junction structure is reduced, so that an electric field near a second conductive type semiconductor body region is reduced. Finally, an avalanche breakdown current path is enabled to avoid the base resistance of a parasitic BJT, and when the super junction DMOS device is subjected to avalanche breakdown, the parasitic triode is effectively prevented from being started, so that the reliability (namely UIS failure resistance) of the super junction DMOS device in non-clamping inductive load application is improved.
Vertical super junction power DMOS has good application in many areas by virtue of its low on-resistance, but in high frequency applications, super junction power DMOS presents some drawbacks. The research finds that the column structure of the drift region brings two effects to the body diode of the super junction power DMOS: firstly, the area of the junction is much larger, so that IRM and Qrr are increased when the body diode is injected in the forward direction; and secondly, the rapid depletion of the first conductive type and the second conductive type junction pillars causes the reverse recovery of the body diode to be too hard, so that the body diode is easy to fail. The problems of voltage overshoot, emi (electromagnetic interference) and the like caused by too small softness factor are important reasons for the failure of the super junction device, so that it is very important to improve the softness factor of the super junction device.
Disclosure of Invention
Aiming at the problems, the invention provides the super-junction DMOS device, which realizes additional hole charge supplement at the later stage of the body diode reverse recovery process by optimizing the service life of a current carrier of a super-junction region and introducing a hole injection region at the bottom of the device, so as to improve the softness factor of the body diode reverse recovery process, realize smaller voltage overshoot, avoid EMI (electromagnetic interference) failure and reduce the starting risk of a parasitic triode, and achieve the effect of improving the reliability of the device.
The purpose of the invention is realized by the following technical scheme:
an improved structure suitable for super junction DMOS device which characterized in that: a heavily doped second conductive type semiconductor island region is further arranged on the contact surface of the first conductive type semiconductor doped substrate and the metalized drain of the super junction DMOS device, the heavily doped second conductive type semiconductor island region forms a device bottom hole injection region, the heavily doped second conductive type semiconductor island region is embedded in the first conductive type semiconductor doped substrate, and the bottom of the heavily doped second conductive type semiconductor island region is also in contact with the upper surface of the metalized drain; and the carrier lifetime of the lower half area of the first conductive type doped column area and the second conductive type semiconductor doped column area is longer than that of the upper half area.
The doping degree of the heavily doped second conductive type semiconductor island region is at least 2 orders of magnitude higher than the doping degree of the first conductive type doped column region and the second conductive type semiconductor doped column region; that is, the heavy doping is relative to the first conductive type doped column region and the second conductive type semiconductor doped column region, and is generally higher than 2 orders of magnitude, which is called as heavy doping.
After the process flow of the device preparation is completed, light ions such as protons or alpha particles enter the device, the tail ends of the shooting ranges of the light ions fall on the upper half area of the first conductive type doped column area and the upper half area of the second conductive type doped column area to form a local defect area, platinum atoms are doped into the device, and the platinum atoms are distributed in the local defect area through annealing; such that the carriers in the upper half regions of the first conductivity type doped column region and the second conductivity type semiconductor doped column region will be lower than in the lower half regions.
A metalized drain electrode of the super-junction DMOS device is positioned on the lower surface of the first conduction type semiconductor doped substrate; the first conductive type doped column region and the second conductive type semiconductor doped column region are positioned on the upper surface of the first conductive type semiconductor doped substrate; the second conductive type semiconductor doped column region is positioned at two sides of the first conductive type doped column region and forms a super junction structure with the first conductive type doped column region; the top of the second conductive type semiconductor doping column region is provided with a second conductive type semiconductor body region which is respectively contacted with the second conductive type semiconductor doping column region and the first conductive type doping column region; the upper layer of the second conductive type semiconductor body region is provided with a first conductive type semiconductor doping source region and a second conductive type semiconductor doping contact region which are mutually independent, wherein the first conductive type semiconductor doping source region is positioned at one side close to the first conductive type doping column region; the polycrystalline silicon gate electrode is positioned on the upper surfaces of the second conductive type semiconductor body region and the first conductive type doped column region and is insulated from the second conductive type semiconductor body region and the first conductive type doped column region through a gate dielectric layer; the metalized source electrode is positioned on the uppermost layer of the device, and the lower surface of the metalized source electrode covers the second conductive type semiconductor doped contact area, the upper surface of part of the first conductive type semiconductor doped source area, the upper surface of the gate dielectric layer and the side surface of the gate dielectric layer.
The polycrystalline silicon gate electrode and the gate dielectric layer of the super junction DMOS device can extend downwards, the second conductive type semiconductor body region is located on the two sides of the polycrystalline silicon gate electrode and the gate dielectric layer to form a trench gate structure, and the formed MOSFET channel is located on the side face of the second conductive type semiconductor body region.
According to the technical scheme, the improved structure suitable for the super-junction DMOS device is characterized in that a heavily-doped second-conductivity-type semiconductor island region is introduced into the lower surface of a first-conductivity-type semiconductor doped column substrate of a conventional super-junction DMOS device, meanwhile, the lower surface of the heavily-doped second-conductivity-type semiconductor island region is in contact with a metalized drain electrode, and the super-junction column region is provided with a long-carrier service life region and a short-carrier service life region through an electron irradiation method. By the measures, due to the existence of the heavily doped second conductivity type semiconductor island region, a PN junction formed by the heavily doped second conductivity type semiconductor island region and the first conductivity type semiconductor doped column substrate is forward biased during reverse recovery, hole current of the first conductivity type doped column region is provided, the current reduction time of a reverse recovery current curve is prolonged, and finally the softness factor of the device is increased; the super-junction column region reduces the combination of the column region of the second conductive type semiconductor island region close to the drain end and carriers by modulating the carrier life of different regions, so that more carriers can be provided at the same time to slow down the current falling slope, the current falling duration of a reverse recovery current curve is prolonged, the softness factor of a device is further increased, the reverse recovery curve of a super-junction diode is improved, the voltage overshoot and EMI equivalent response is relieved, and better reliability is realized.
Drawings
The foregoing and following detailed description of the invention will be apparent when read in conjunction with the following drawings, in which:
fig. 1 is a schematic structural diagram of a super junction DMOS device mentioned in the background art;
FIG. 2 is a schematic structural view of a basic embodiment of the present invention;
FIG. 3 is a schematic structural view of a preferred embodiment of the present invention;
in the figure:
1. a metalized drain electrode; 2. a first conductivity type semiconductor doped substrate; 3. a second conductivity type semiconductor island region; 5. a first conductivity type doped column region; 6. a second conductivity type semiconductor doped column region 7, a second conductivity type semiconductor body region; 8. a first conductive type semiconductor doping source region; 9. a second conductivity type semiconductor doped contact region; 10. a polysilicon gate electrode; 11. a gate dielectric layer; 12. and (6) metalizing the source electrode.
Detailed Description
The technical solutions for achieving the objects of the present invention are further illustrated by the following specific examples, and it should be noted that the technical solutions claimed in the present invention include, but are not limited to, the following examples.
Example 1
As a most basic embodiment of the present invention, as shown in fig. 2, this example discloses an improved structure suitable for a super junction DMOS device, wherein a heavily doped second conductivity type semiconductor island region 3 is further disposed on the contact surface of the first conductivity type semiconductor doped substrate 2 and the metalized drain of the super junction DMOS device, the heavily doped second conductivity type semiconductor island region 3 constitutes a device bottom hole injection region, the heavily doped second conductivity type semiconductor island region 3 is embedded in the first conductivity type semiconductor doped substrate 2 and the bottom thereof is also in contact with the upper surface of the metalized drain; and the carrier lifetime of the lower half region of each of the first conductivity type doped column region 5 and the second conductivity type semiconductor doped column region 6 is longer than that of the upper half region.
According to the technical scheme, the improved structure suitable for the super-junction DMOS device is characterized in that a heavily-doped second-conductivity-type semiconductor island region 3 is introduced into the lower surface of a first-conductivity-type semiconductor doped column substrate of a conventional super-junction DMOS device, meanwhile, the lower surface of the heavily-doped second-conductivity-type semiconductor island region 3 is in contact with a metalized drain electrode, and the super-junction column region is enabled to have a long-carrier service life region and a short-carrier service life region through an electron irradiation method. By the measures, due to the existence of the heavily doped second conduction type semiconductor island region 3, a PN junction formed by the heavily doped second conduction type semiconductor island region 3 and the first conduction type semiconductor doped column substrate is forward biased during reverse recovery, hole current of the first conduction type doped column region 5 is provided, the current reduction time of a reverse recovery current curve is prolonged, and finally the softness factor of the device is increased; the super junction column region reduces the combination of the column region of the second conductive type semiconductor island region 3 close to the drain end and the current carrier by modulating the service life of the current carrier in different regions, so that more current carriers can be provided at the same time to slow down the current falling slope, the current falling duration of a reverse recovery current curve is prolonged, the softness factor of a device is further increased, the reverse recovery curve of a super junction diode is improved, the voltage overshoot and EMI equivalent response is relieved, and better reliability is realized.
Example 2
As a preferred embodiment of the present invention, as shown in fig. 2, this example discloses an improved structure suitable for a super junction DMOS device, wherein a heavily doped second conductivity type semiconductor island region 3 is further disposed on the contact surface of the first conductivity type semiconductor doped substrate 2 and the metalized drain of the super junction DMOS device, the heavily doped second conductivity type semiconductor island region 3 constitutes a device bottom hole injection region, the heavily doped second conductivity type semiconductor island region 3 is embedded in the first conductivity type semiconductor doped substrate 2 and the bottom thereof is also in contact with the upper surface of the metalized drain; and the lifetime of carriers in the lower half region of each of the first conductivity type doped column region 5 and the second conductivity type semiconductor doped column region 6 is longer than that in the upper half region.
The doping degree of the heavily doped second conduction type semiconductor island region 3 is at least 2 orders of magnitude higher than the doping degree of the first conduction type doped column region 5 and the second conduction type semiconductor doped column region 6; i.e. the heavy doping is relative to the first conductivity type doped column region 5 and the second conductivity type semiconductor doped column region 6, and is generally higher than 2 orders of magnitude, i.e. it is called heavy doping.
After the process flow of the device preparation is completed, light ions such as protons or alpha particles enter the device, the ends of the range fall in the upper half regions of the first conductive type doped column region 5 and the second conductive type doped column region 6, such as column regions a 'and B' in fig. 2 and 3, to form local defect regions, a certain amount of platinum atoms are doped in the device, and the platinum atoms are mainly distributed in the local defect regions of a 'and B' through annealing. So that the carriers in the a 'and B' regions will be lower than in the a and B regions. As shown in fig. 2, the shaded circles represent the distribution of platinum atoms in the regions a 'and B'.
As shown in fig. 2, a metalized drain electrode 1 of the super junction DMOS device is positioned on the lower surface of a first conductive type semiconductor doped substrate 2; the first conductive type doped column region 5 and the second conductive type semiconductor doped column region 6 are positioned on the upper surface of the first conductive type semiconductor doped substrate 2; the second conductive type semiconductor doped column region 6 is positioned at two sides of the first conductive type doped column region 5 and forms a super junction structure with the first conductive type doped column region 5; the top of the second conductive type semiconductor doping column region 6 is provided with a second conductive type semiconductor body region 7, and the second conductive type semiconductor body region 7 is respectively contacted with the second conductive type semiconductor doping column region 6 and the first conductive type doping column region 5; the upper layer of the second conductive type semiconductor body region 7 is provided with a first conductive type semiconductor doping source region 8 and a second conductive type semiconductor doping contact region 9 which are independent from each other, wherein the first conductive type semiconductor doping source region 8 is positioned at one side close to the first conductive type doping column region 5; the polycrystalline silicon gate electrode 10 is positioned on the upper surfaces of the second conductive type semiconductor body region 7 and the first conductive type doped column region 5 and is insulated from the second conductive type semiconductor body region 7 and the first conductive type doped column region 5 through a gate dielectric layer 11; the metalized source electrode is positioned on the uppermost layer of the device, and the lower surface of the metalized source electrode covers the second conductive type semiconductor doping contact area 9, the upper surface of part of the first conductive type semiconductor doping source area 8, the upper surface and the side surface of the gate dielectric layer 11.
As shown in fig. 3, the polysilicon gate electrode 10 and the gate dielectric layer 11 of the super junction DMOS device may be extended downward and the second conductivity type semiconductor body region 7 may be located at both sides of the polysilicon gate electrode 10 and the gate dielectric layer 11 to form a trench gate structure, and the MOSFET channel is located at the side of the second conductivity type semiconductor body region 7.
According to the technical scheme, the heavily-doped second conduction type semiconductor island region 3 is introduced into the lower surface of a first conduction type semiconductor doped column substrate of the conventional super-junction DMOS device, meanwhile, the lower surface of the heavily-doped second conduction type semiconductor island region 3 is in contact with a metalized drain electrode, and the super-junction column region is provided with a long carrier service life region and a short carrier service life region through an electron irradiation method. By the measures, due to the existence of the heavily doped second conduction type semiconductor island region 3, a PN junction formed by the heavily doped second conduction type semiconductor island region 3 and the first conduction type semiconductor doped column substrate is forward biased during reverse recovery, hole current of the first conduction type doped column region 5 is provided, the current reduction time of a reverse recovery current curve is prolonged, and finally the softness factor of the device is increased; the super junction column region reduces the combination of the column region of the second conductive type semiconductor island region 3 close to the drain end and the current carrier by modulating the service life of the current carrier in different regions, so that more current carriers can be provided at the same time to slow down the current falling slope, the current falling duration of a reverse recovery current curve is prolonged, the softness factor of a device is further increased, the reverse recovery curve of a super junction diode is improved, the voltage overshoot and EMI equivalent response is relieved, and better reliability is realized.
Claims (3)
1. An improved structure suitable for super junction DMOS device which characterized in that: a heavily-doped second-conductivity-type semiconductor island region (3) is further arranged on the contact surface of the first-conductivity-type semiconductor doped substrate (2) and the metalized drain of the super-junction DMOS device, the heavily-doped second-conductivity-type semiconductor island region (3) forms a device bottom hole injection region, the heavily-doped second-conductivity-type semiconductor island region (3) is embedded in the first-conductivity-type semiconductor doped substrate (2) and the bottom of the heavily-doped second-conductivity-type semiconductor island region is also in contact with the upper surface of the metalized drain, and the doping degree of the heavily-doped second-conductivity-type semiconductor island region (3) is at least 2 orders of magnitude higher than that of the first-conductivity-type doped column region (5) and the second-conductivity-type semiconductor doped column region (6); and the service life of the current carrier of the lower half part of the first conductive type doping column region (5) and the second conductive type semiconductor doping column region (6) is longer than that of the upper half part, after the process flow of the device preparation is completed, light ions are incident into the device, the tail end of the range of the light ions falls on the upper half part of the first conductive type doping column region (5) and the second conductive type semiconductor doping column region (6) to form a local defect region, platinum atoms are doped into the device, and then the platinum atoms are distributed in the local defect region through annealing.
2. The improved structure of claim 1 for use in a superjunction DMOS device wherein: a metalized drain electrode (1) of the super-junction DMOS device is positioned on the lower surface of the first conduction type semiconductor doped substrate (2); the first conductive type doped column region (5) and the second conductive type semiconductor doped column region (6) are positioned on the upper surface of the first conductive type semiconductor doped substrate (2); the second conductive type semiconductor doped column region (6) is positioned at two sides of the first conductive type doped column region (5) and forms a super junction structure with the first conductive type doped column region (5); the top of the second conduction type semiconductor doping column region (6) is provided with a second conduction type semiconductor body region (7), and the second conduction type semiconductor body region (7) is respectively contacted with the second conduction type semiconductor doping column region (6) and the first conduction type semiconductor doping column region (5); the upper layer of the second conductive type semiconductor body region (7) is provided with a first conductive type semiconductor doping source region (8) and a second conductive type semiconductor doping contact region (9) which are independent from each other, wherein the first conductive type semiconductor doping source region (8) is positioned at one side close to the first conductive type doping column region (5); the polycrystalline silicon gate electrode (10) is positioned on the upper surfaces of the second conductive type semiconductor body region (7) and the first conductive type doped column region (5) and is insulated from the second conductive type semiconductor body region (7) and the first conductive type doped column region (5) through a gate dielectric layer (11); the metallization source electrode is located on the uppermost layer of the device, and the lower surface of the metallization source electrode covers the second conduction type semiconductor doping contact area (9), the upper surface of part of the first conduction type semiconductor doping source area (8), the upper surface of the gate dielectric layer (11) and the side surfaces of the gate dielectric layer.
3. The improved structure of claim 2 for use in a superjunction DMOS device wherein: a polysilicon gate electrode (10) and a gate dielectric layer (11) of the super-junction DMOS device extend downwards, a second conductive type semiconductor body region (7) is located on two sides of the polysilicon gate electrode (10) and the gate dielectric layer (11) to form a trench gate structure, and a formed MOSFET channel is located on the side face of the second conductive type semiconductor body region (7).
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| CN110310983B (en) * | 2019-07-31 | 2024-02-23 | 电子科技大学 | Super junction VDMOS device |
| CN113224164B (en) * | 2021-04-21 | 2022-03-29 | 电子科技大学 | Super junction MOS device |
| CN115172466B (en) * | 2022-09-05 | 2022-11-08 | 深圳市威兆半导体股份有限公司 | Novel super-junction VDMOS structure and preparation method thereof |
| CN116741811B (en) * | 2023-08-11 | 2023-10-20 | 成都森未科技有限公司 | Super-junction MOSFET device and processing method thereof |
| CN117334727B (en) * | 2023-12-01 | 2024-02-27 | 通威微电子有限公司 | Super junction device and manufacturing method thereof |
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