CN109713041A - A kind of structure-improved suitable for superjunction DMOS device - Google Patents
A kind of structure-improved suitable for superjunction DMOS device Download PDFInfo
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Abstract
The invention discloses a kind of structure-improveds suitable for superjunction DMOS device, belong to electronic device optimisation technique field, the second conductive type semiconductor island area of heavy doping is additionally provided in the first conductive type semiconductor doped substrate of superjunction DMOS device and the contact surface of metalized drain, second conductive type semiconductor island area of the heavy doping constitutes bottom device hole injection region, and the second conductive type semiconductor island area insertion of the heavy doping is arranged in the first conductive type semiconductor doped substrate and its bottom is also in contact with the upper surface of metalized drain；And the first conduction type doped column area and the second subregional carrier lifetime in conductive type semiconductor doped column area lower half are longer than the subregional carrier lifetime in the upper half.
Description
Technical field
The invention belongs to electronic device optimisation technique fields, and in particular to a kind of improvement knot suitable for superjunction DMOS device
Structure.
Background technique
Power DMOS because of the advantages that its switching speed is fast, loss is small, input impedance is high, driving power is small, frequency characteristic is good,
It especially plays an important role in HF power conversion in power conversion.The system performance requirements power DMOS of continuous improvement has
While having lower power loss, also there is higher reliability under high electric stress.With superjunction (super-junction)
The DMOS device of structure is a kind of important power device occurred in recent years, its basic principle is charge balance concept, is led to
The super-junction structure for introducing the P column and n column that are spaced each other in the drift region in common power DMOS is crossed, common DMOS is substantially improved
Conducting resistance and breakdown voltage between tradeoff, thus have been widely used in the power system.
In the prior art, such as Publication No. CN107248532A, the middle promulgated by the State Council of entitled " a kind of superjunction DMOS device "
Bright patent document, provides a kind of superjunction DMOS device, including metallization drain electrode, the first conductive type semiconductor doped substrate,
First conduction type doped column area, the second conductive type semiconductor doped column area, polygate electrodes, gate dielectric layer, metallization
Source electrode；Metallization drain electrode is located at the first conductive type semiconductor doped substrate lower surface；First conduction type doped column area and
Second conductive type semiconductor doped column area is located at the first conductive type semiconductor doped substrate upper surface；First conduction type is mixed
There is a first low-doped conduction type doped region right above the area Za Zhu；Second conductive type semiconductor doped column area is located at
First conduction type doped column area two sides, and super-junction structure is formed with the first conduction type doped column area；Second conduction type half
There is the second conductive type semiconductor body area, the second conductive type semiconductor body area is led with second respectively at the top of conductor doped column area
Electric type semiconductor doped column area and the first low-doped conduction type doped region are in contact；Second conductive type semiconductor body area
There is mutually independent first conductive type semiconductor doping source region and the second conductive type semiconductor to adulterate contact zone on upper layer,
In the first conductive type semiconductor doping source region be located at close to the first low-doped conduction type doped region side；The polycrystalline
Silicon gate electrode is located at the second conductive type semiconductor body area and the first low-doped conduction type doped region upper surface, and with second
It is mutually insulated between conductive type semiconductor body area and the first low-doped conduction type doped column area by gate dielectric layer；The gold
Categoryization source electrode is located at the top layer of device, and the lower surface for the source electrode that metallizes is covered on the doping of the second conductive type semiconductor and connects
Touch area, the upper surface of part the first conductive type semiconductor doping source region and the upper surface and side of gate dielectric layer；Its feature
It is that also there is dielectric layer structure in the first conduction type doped column area, the dielectric layer structure is located at second and leads
Electric type semiconductor doped column area side, the bottom connection at the top of dielectric layer structure and the second conductive type semiconductor body area
Touching, the bottom of dielectric layer structure and the upper surface of the first conductive type semiconductor doped substrate are separated by a certain distance；The medium
The vertical length of floor structure is shorter than the vertical length in the second conductive type semiconductor doped column area, the first low-doped conduction
Type doped region refers to that the doping concentration of the first conduction type doped region is lower than the doping concentration in the first conduction type doped column area；
It is a kind of superjunction DMOS device, dielectric layer structure is done by the second conduction type doped column area side in super-junction structure to fix
The avalanche breakdown point of superjunction DMOS device, while the doping concentration at the top of super-junction structure the second conduction type doped column area is reduced,
Reduce the electric field near the second conductive type semiconductor body area.Finally avalanche breakdown current path is made to avoid parasitic BJT's
Base resistance effectively avoids the unlatching of parasitic triode, to improve superjunction when avalanche breakdown occurs for superjunction DMOS device
Reliability (i.e. anti-UIS failure ability) of the DMOS device in non-clamp inductive load application.
Longitudinal superjunction power DMOS has good application in numerous areas by its lower conducting resistance, but in height
Under frequency is applied, superjunction power DMOS shows some disadvantages.The study found that the column structure of drift region gives superjunction power DMOS
Body diode bring two consequences: first is that the big many of the area of knot, IRM and Qrr liter when body diode forward direction being caused to be injected
It is high；Second is that since the rapidly depleting body diode reverse that brings of the first conduction type and the second conduction type knot column was restored
Firmly, it easily fails.And the softness factor it is too small caused by voltage overshoot, EMI(Electromagnetic Interference)
The problems such as be superjunction devices failure major reason, therefore improve superjunction devices the softness factor just seem particularly critical.
Summary of the invention
The present invention is excellent by the carrier lifetime to superjunction region in view of the above problems, provide a kind of superjunction DMOS device
Change, and introduce hole injection region in bottom device, additionally supplements sky in the later period of body diode reverse recovery process to realize
Cave charge realizes smaller voltage overshoot to avoid EMI to improve the softness factor of body diode reverse recovery process
(Electromagnetic Interference) failure and the unlatching risk for reducing parasitic triode, reaching raising device can
By the effect of property.
The purpose of the present invention is what is be achieved through the following technical solutions:
A kind of structure-improved suitable for superjunction DMOS device, it is characterised in that: in the first conduction type of superjunction DMOS device
The second conductive type semiconductor island area of heavy doping, institute are additionally provided on the contact surface of semiconductor doping substrate and metalized drain
The the second conductive type semiconductor island area for stating heavy doping constitutes bottom device hole injection region, the second conductive-type of the heavy doping
The upper of in the first conductive type semiconductor doped substrate and its bottom and metalized drain is arranged in the insertion of type semiconductor island area
Surface is also in contact；And the first conduction type doped column area and the second conductive type semiconductor doped column area lower half portion region
Carrier lifetime be longer than the subregional carrier lifetime in the upper half.
The doping level in the second conductive type semiconductor island area of the heavy doping be higher than the first conduction type doped column area and
Doping level at least two order of magnitude in the second conductive type semiconductor doped column area；I.e. heavy doping is that opposite first conduction type is mixed
For the area Za Zhu and the second conductive type semiconductor doped column area, generally greater than 2 orders of magnitude can be referred to as heavy doping.
The first conduction type doped column area and the second subregional load in conductive type semiconductor doped column area lower half
Flowing the sub- service life is longer than the subregional carrier lifetime in the upper half, is to pass through proton after the process flow for completing device preparation
Or the light ions such as α particle are incident in device, and its end-of-range is allowed to fall in the first conduction type doped column area and the second conduction
The top half region in type semiconductor doped column area is allowed to form local defects area, then mixes pt atom in the devices, then lead to
Crossing annealing makes pt atom be distributed in local defects area；Such first conduction type doped column area and the second conductive type semiconductor are mixed
Carrier in the top half region in the area Za Zhu will be less than lower half portion region.
The metallization drain electrode of superjunction DMOS device is located at the first conductive type semiconductor doped substrate lower surface；First leads
Electric type doped column area and the second conductive type semiconductor doped column area are located at table in the first conductive type semiconductor doped substrate
Face；Second conductive type semiconductor doped column area is located at the first conduction type doped column area two sides, and mixes with the first conduction type
The area Za Zhu forms super-junction structure；There is the second conductive type semiconductor body area at the top of second conductive type semiconductor doped column area,
Second conductive type semiconductor body area respectively with the second conductive type semiconductor doped column area and the first conduction type doped column area
It is in contact；Second conductive type semiconductor body area upper layer has mutually independent first conductive type semiconductor doping source region and the
Two conductive type semiconductors adulterate contact zone, wherein the first conductive type semiconductor doping source region is located at close to the first conduction type
The side in doped column area；The polygate electrodes are located at the second conductive type semiconductor body area and the first conduction type doped column
Area upper surface, and it is mutually exhausted by gate dielectric layer between the second conductive type semiconductor body area and the first conduction type doped column area
Edge；The metallization source electrode is located at the top layer of device, and the lower surface for the source electrode that metallizes is covered on the second conduction type half
Conductor adulterate contact zone, part the first conductive type semiconductor doping source region upper surface and gate dielectric layer upper surface and
Side.
Polygate electrodes, the gate dielectric layer of superjunction DMOS device can extend downwardly and make the second conductive type semiconductor body
Area is located at polygate electrodes, gate dielectric layer two sides form trench grid structure, is formed by MOSFET channel and leads positioned at second
Electric type semiconductor body area side.
A kind of structure-improved suitable for superjunction DMOS device of the technical program, the first of conventional superjunction DMOS device
The lower surface of conductive type semiconductor doped column substrate introduces the second conductive type semiconductor island area of heavy doping, while heavy doping
The lower surface in the second conductive type semiconductor island area be in contact with metalized drain;And to surpass by the method for electron irradiation
The area Jie Zhu has long carrier lifetime region and and short carrier lifetime region.By above-mentioned measure, due to the of heavy doping
The presence on two conductive type semiconductor islands area so that when Reverse recovery heavy doping the second conductive type semiconductor island area and first
The PN junction positively biased that conductive type semiconductor doped column substrate is formed, provides the hole current in the first conduction type doped column area,
The electric current decline duration for increasing reverse recovery current curve, ultimately increases the softness factor of device；Superjunction column area passes through tune
The carrier lifetime of different zones processed reduces the load of the column region sum close to the second conductive type semiconductor island area of drain terminal
Stream is compound, therefore can provide more carriers under same time to slow down electric current descending slope, to increase reversed
The electric current of restoring current curve declines duration, further increases the softness factor of device, improves the anti-of superjunction body diode
To recovery curve, to alleviate the effects such as voltage overshoot, EMI, better reliability is realized.
Detailed description of the invention
It is of the invention aforementioned and be detailed description below and become more apparent upon when reading in conjunction with the following drawings, in attached drawing:
Fig. 1 is a kind of structural schematic diagram for the superjunction DMOS device mentioned in background technique；
Fig. 2 is a kind of structural schematic diagram of basic scheme of the present invention；
Fig. 3 is a kind of structural schematic diagram of preferred embodiment of the present invention；
In figure:
1, metallize drain electrode；2, the first conductive type semiconductor doped substrate；3, the second conductive type semiconductor island area；5,
One conduction type doped column area；6, the second conductive type semiconductor doped column area, the 7, second conductive type semiconductor body area；8,
One conductive type semiconductor doping source region；9, the second conductive type semiconductor adulterates contact zone；10, polygate electrodes；11, grid
Dielectric layer；12, metallizing source.
Specific embodiment
It is further illustrated below by several specific embodiments and realizes the object of the invention technical solution, need to illustrate
It is that claimed technical solution includes but is not limited to following embodiment.
Embodiment 1
As a kind of most basic embodiment of the invention, such as Fig. 2, present embodiment discloses one kind to be suitable for superjunction DMOS device
Structure-improved, in the first conductive type semiconductor doped substrate 2 of superjunction DMOS device and the contact surface of metalized drain
It is additionally provided with the second conductive type semiconductor island area 3 of heavy doping, 3 structure of the second conductive type semiconductor island area of the heavy doping
At bottom device hole injection region, the second conductive type semiconductor island area 3 insertion of the heavy doping is arranged in the first conductive-type
In type semiconductor doping substrate 2 and its bottom is also in contact with the upper surface of metalized drain；And the first conduction type is mixed
The area Za Zhu 5 and the 6 subregional carrier lifetime in lower half of the second conductive type semiconductor doped column area are longer than upper half subregion
The carrier lifetime in domain.
A kind of structure-improved suitable for superjunction DMOS device of the technical program, the first of conventional superjunction DMOS device
The lower surface of conductive type semiconductor doped column substrate introduces the second conductive type semiconductor island area 3 of heavy doping, while heavily doped
The lower surface in the second miscellaneous conductive type semiconductor island area 3 is in contact with metalized drain;And made by the method for electron irradiation
Obtaining superjunction column area has long carrier lifetime region and and short carrier lifetime region.By above-mentioned measure, due to heavy doping
The second conductive type semiconductor island area 3 presence so that when Reverse recovery heavy doping the second conductive type semiconductor island area 3
The PN junction positively biased formed with the first conductive type semiconductor doped column substrate, provides the sky in the first conduction type doped column area 5
Cave electric current increases the electric current decline duration of reverse recovery current curve, ultimately increases the softness factor of device；Superjunction column area
By modulating the carrier lifetime of different zones, the column reduced close to the second conductive type semiconductor island area 3 of drain terminal is trivial
The Carrier recombination of domain sum, therefore more carriers can be provided under same time to slow down electric current descending slope, thus
The electric current for increasing reverse recovery current curve declines duration, further increases the softness factor of device, improves superjunction body two
The Reverse recovery curve of pole pipe realizes better reliability to alleviate the effects such as voltage overshoot, EMI
Embodiment 2
It is preferably carried out scheme, such as Fig. 2 as one kind of the present invention, present embodiment discloses a kind of suitable for superjunction DMOS device
Structure-improved, in the first conductive type semiconductor doped substrate 2 of superjunction DMOS device and the contact surface of metalized drain also
It is provided with the second conductive type semiconductor island area 3 of heavy doping, the second conductive type semiconductor island area 3 of the heavy doping is constituted
The second conductive type semiconductor island area 3 insertion of bottom device hole injection region, the heavy doping is arranged in the first conduction type
In semiconductor doping substrate 2 and its bottom is also in contact with the upper surface of metalized drain；And the first conduction type adulterates
Column area 5 and the 6 subregional carrier lifetime in lower half of the second conductive type semiconductor doped column area are longer than top half region
Carrier lifetime.
Also, the doping level in the second conductive type semiconductor island area 3 of the heavy doping is adulterated higher than the first conduction type
Doping level at least two order of magnitude in column area 5 and the second conductive type semiconductor doped column area 6；I.e. heavy doping is first to lead relatively
For electric type doped column area 5 and the second conductive type semiconductor doped column area 6, generally greater than 2 orders of magnitude can be referred to as
For heavy doping.
The first conduction type doped column area 5 and 6 lower half of the second conductive type semiconductor doped column area are subregional
Carrier lifetime is longer than the subregional carrier lifetime in the upper half, is to pass through matter after the process flow for completing device preparation
The light ions such as son or α particle are incident in device, and are allowed its end-of-range to fall in the first conduction type doped column area 5 and second and led
The top half region in electric type semiconductor doped column area 6, as being allowed to form local in Fig. 2 and 3 area Zhong Zhu A ' and the region B '
Defect area, then mix a certain amount of pt atom in the devices makes pt atom be distributed mainly on A ' and B by annealing ' local lack
Fall into area.Carrier in such A ' and the region B ' will be less than A and B area.As shown in Fig. 2, shaded circles represent A ' and B in figure '
Pt atom distribution in region.
As the metallization drain electrode 1 of Fig. 2, superjunction DMOS device are located at 2 following table of the first conductive type semiconductor doped substrate
Face；First conduction type doped column area 5 and the second conductive type semiconductor doped column area 6 are located at the first conductive type semiconductor and mix
Miscellaneous 2 upper surface of substrate；Second conductive type semiconductor doped column area 6 is located at 5 two sides of the first conduction type doped column area, and with
One conduction type doped column area 5 forms super-junction structure；There is the second conductive-type at the top of second conductive type semiconductor doped column area 6
Type semiconductor body 7, the second conductive type semiconductor body area 7 respectively with the second conductive type semiconductor doped column area 6 and first
Conduction type doped column area 5 is in contact；Second conductive type semiconductor body area, 7 upper layer has mutually independent first conduction type
Semiconductor doping source region 8 and the second conductive type semiconductor adulterate contact zone 9, wherein the first conductive type semiconductor doping source region
8 are located at close to the side in the first conduction type doped column area 5；The polygate electrodes 10 are located at the second conductive type semiconductor
5 upper surface of body area 7 and the first conduction type doped column area, and with the second conductive type semiconductor body area 7 and the first conduction type
It is insulated between doped column area 5 by 11 phase of gate dielectric layer；The metallization source electrode is located at the top layer of device, metallization source electricity
The lower surface of pole is covered on the doping of the second conductive type semiconductor contact zone 9, part the first conductive type semiconductor doping source region 8
Upper surface and gate dielectric layer 11 upper surface and side.
Such as Fig. 3, polygate electrodes 10, the gate dielectric layer 11 of superjunction DMOS device can extend downwardly and make the second conductive-type
Type semiconductor body 7 is located at polygate electrodes 10,11 two sides of gate dielectric layer form trench grid structure, is formed by MOSFET
Channel is located at 7 side of the second conductive type semiconductor body area.
A kind of structure-improved suitable for superjunction DMOS device of the technical program, the first of conventional superjunction DMOS device
The lower surface of conductive type semiconductor doped column substrate introduces the second conductive type semiconductor island area 3 of heavy doping, while heavily doped
The lower surface in the second miscellaneous conductive type semiconductor island area 3 is in contact with metalized drain;And made by the method for electron irradiation
Obtaining superjunction column area has long carrier lifetime region and and short carrier lifetime region.By above-mentioned measure, due to heavy doping
The second conductive type semiconductor island area 3 presence so that when Reverse recovery heavy doping the second conductive type semiconductor island area 3
The PN junction positively biased formed with the first conductive type semiconductor doped column substrate, provides the sky in the first conduction type doped column area 5
Cave electric current increases the electric current decline duration of reverse recovery current curve, ultimately increases the softness factor of device；Superjunction column area
By modulating the carrier lifetime of different zones, the column reduced close to the second conductive type semiconductor island area 3 of drain terminal is trivial
The Carrier recombination of domain sum, therefore more carriers can be provided under same time to slow down electric current descending slope, thus
The electric current for increasing reverse recovery current curve declines duration, further increases the softness factor of device, improves superjunction body two
The Reverse recovery curve of pole pipe realizes better reliability to alleviate the effects such as voltage overshoot, EMI.
Claims (5)
1. a kind of structure-improved suitable for superjunction DMOS device, it is characterised in that: in the first conductive-type of superjunction DMOS device
The second conductive type semiconductor island of heavy doping is additionally provided on the contact surface of type semiconductor doping substrate (2) and metalized drain
The second conductive type semiconductor island area (3) in area (3), the heavy doping constitutes bottom device hole injection region, the heavy doping
The insertion of the second conductive type semiconductor island area (3) be arranged in the first conductive type semiconductor doped substrate (2) and its bottom
Portion is also in contact with the upper surface of metalized drain；And the first conduction type doped column area (5) and the second conduction type are partly led
The subregional carrier lifetime in body doped column area (6) lower half is longer than the subregional carrier lifetime in the upper half.
2. a kind of structure-improved suitable for superjunction DMOS device as described in claim 1, it is characterised in that: the heavy doping
The second conductive type semiconductor island area (3) doping level be higher than the first conduction type doped column area (5) and the second conduction type
Doping level at least two order of magnitude in semiconductor doping column area (6).
3. a kind of structure-improved suitable for superjunction DMOS device as claimed in claim 1 or 2, it is characterised in that: described the
One conduction type doped column area (5) and the second subregional carrier lifetime in conductive type semiconductor doped column area (6) lower half
It is longer than the subregional carrier lifetime in the upper half, is after the process flow for completing device preparation, by the way that light ion is incident
Into device, and its end-of-range is allowed to fall in the first conduction type doped column area (5) and the second conductive type semiconductor doped column
The top half region in area (6) is allowed to form local defects area, then mixes pt atom in the devices, then keeps platinum former by annealing
Son is distributed in local defects area.
4. a kind of structure-improved suitable for superjunction DMOS device as described in claim 1, it is characterised in that: superjunction DMOS device
The metallization drain electrode (1) of part is located at first conductive type semiconductor doped substrate (2) lower surface；First conduction type doped column
Area (5) and the second conductive type semiconductor doped column area (6) are located at first conductive type semiconductor doped substrate (2) upper surface；
Second conductive type semiconductor doped column area (6) is located at first conduction type doped column area (5) two sides, and with the first conduction type
Doped column area (5) forms super-junction structure；At the top of second conductive type semiconductor doped column area (6) there is the second conduction type partly to lead
The area Ti Ti (7), the second conductive type semiconductor body area (7) respectively with the second conductive type semiconductor doped column area (6) and first
Conduction type doped column area (5) is in contact；Second conductive type semiconductor body area (7) upper layer has mutually independent first conduction
Type semiconductor doping source region (8) and the second conductive type semiconductor doping contact zone (9), wherein the first conductive type semiconductor
Doping source region (8) is located at close to the side in the first conduction type doped column area (5)；The polygate electrodes (10) are located at second
Conductive type semiconductor body area (7) and first conduction type doped column area (5) upper surface, and with the second conductive type semiconductor body
It is mutually insulated between area (7) and the first conduction type doped column area (5) by gate dielectric layer (11)；The metallization source electrode is located at
The top layer of device, the lower surface for the source electrode that metallizes are covered on the second conductive type semiconductor doping contact zone (9), part the
The upper surface of one conductive type semiconductor doping source region (8) and the upper surface and side of gate dielectric layer (11).
5. a kind of structure-improved suitable for superjunction DMOS device as claimed in claim 4, it is characterised in that: superjunction DMOS device
Polygate electrodes (10), the gate dielectric layer (11) of part extend downwardly and make the second conductive type semiconductor body area (7) positioned at more
Crystal silicon gate electrode (10), gate dielectric layer (11) two sides form trench grid structure, are formed by MOSFET channel and lead positioned at second
Electric type semiconductor body area (7) side.
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| CN110310983A (en) * | 2019-07-31 | 2019-10-08 | 电子科技大学 | A kind of hyperconjugation VDMOS device |
| CN110310983B (en) * | 2019-07-31 | 2024-02-23 | 电子科技大学 | Super junction VDMOS device |
| CN113224164A (en) * | 2021-04-21 | 2021-08-06 | 电子科技大学 | Super junction MOS device |
| CN113224164B (en) * | 2021-04-21 | 2022-03-29 | 电子科技大学 | Super junction MOS device |
| CN115172466A (en) * | 2022-09-05 | 2022-10-11 | 深圳市威兆半导体股份有限公司 | Novel super-junction VDMOS structure and preparation method thereof |
| CN115172466B (en) * | 2022-09-05 | 2022-11-08 | 深圳市威兆半导体股份有限公司 | Novel super-junction VDMOS structure and preparation method thereof |
| CN116741811A (en) * | 2023-08-11 | 2023-09-12 | 成都森未科技有限公司 | Super-junction MOSFET device and processing method thereof |
| CN116741811B (en) * | 2023-08-11 | 2023-10-20 | 成都森未科技有限公司 | Super-junction MOSFET device and processing method thereof |
| CN117334727A (en) * | 2023-12-01 | 2024-01-02 | 通威微电子有限公司 | Super junction device and manufacturing method thereof |
| CN117334727B (en) * | 2023-12-01 | 2024-02-27 | 通威微电子有限公司 | Super junction device and manufacturing method thereof |
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| CN109713041B (en) | 2022-05-24 |
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