CN107359125A - A kind of method and device for optimizing body diode reverse recovery characteristics - Google Patents
A kind of method and device for optimizing body diode reverse recovery characteristics Download PDFInfo
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- CN107359125A CN107359125A CN201710560598.3A CN201710560598A CN107359125A CN 107359125 A CN107359125 A CN 107359125A CN 201710560598 A CN201710560598 A CN 201710560598A CN 107359125 A CN107359125 A CN 107359125A
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- 238000011084 recovery Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims description 35
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 238000002513 implantation Methods 0.000 claims description 16
- 150000002500 ions Chemical class 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 238000005224 laser annealing Methods 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 4
- 238000005457 optimization Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000009527 percussion Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The invention discloses a kind of method and device for the reverse recovery characteristic for optimizing body diode, it is handled in COOLMOS devices, and wherein drain region is formed at COOLMOS bottom devices, and n heavily doped regions doping concentration is higher than the doping concentration of n doped substrate regions.The present invention by device be thinned after in the subregional n-type heavy doping of device back side forming portion, the buffer layer structure of local can be formed, improve the softness of body diode reverse recovery, backward voltage interconversion rate (dv/dt) is reduced, so as to optimize the reverse recovery characteristic of body diode.
Description
Technical field
The present invention relates to a kind of method and device for optimizing body diode reverse recovery characteristics.
Background technology
In high-voltage switch gear application, it is necessary to using the strong high-pressure MOS device of the body diode and durability with superperformance
Part, but the higher conducting resistance of conventional high-pressure MOS component adds the quiescent dissipation of on-off circuit, with superjunction devices
Development, multiple commercial vendors have developed the COOLMOS devices of different process fabrication techniques, and COOLMOS devices compare common high pressure
MOS device has lower conducting internal resistance, therefore can have lower working loss.All multirows are had been widely used at present
Industry.
A parasitic common pn-junction body diode in conventional COOLMOS structures.Diode is by on-state to reverse resistance
The switching process of disconnected state is referred to as Reverse recovery, COOLMOS P+ doped regions and P posts formed jointly with N epitaxial layers intrinsic two
Pole pipe is referred to as body diode, it is necessary to which the reverse drain current that body diode provides is electricity in switch application especially bridge circuit
Road afterflow, because thering is p+ doped regions and P posts to carry out few son note to n-substrate area simultaneously during the body diode conducting of COOLMOS devices
Enter, so as to cause COOLMOS devices that there are worse body diode reverse recovery characteristics compared to ordinary high pressure MOS device.Body two
The poor reverse recovery characteristic of pole pipe will produce high voltage change ratio (dv/dt), device when this is likely to result in Reverse recovery
Part power consumption is too high and grid opens by mistake the problems such as the generation opened, thus application of the reverse recovery characteristic of body diode to device
Reliability is extremely critical influence factor.
The content of the invention
It is an object of the invention to provide a kind of method for optimizing body diode reverse recovery characteristics, can effectively optimize
Voltage change ratio (dv/dt) of the COOLMOS device body diodes in reversely restoring process, it is reliable so as to improve the application of device
Property.
To achieve the object of the present invention, the present invention adopts the following technical scheme that：One kind optimization body diode reverse recovers special
The method of property, it is handled in COOLMOS devices, and wherein drain region is formed at COOLMOS bottom devices, and the drain region
Including the overweight doped regions of n, the n heavily doped region adjacent with the overweight doped regions of n and n doped substrate regions, the n heavily doped regions are located at
In the n doped substrate regions of COOLMOS devices, the overweight doped regions of n are in contact with drain metal electrode, the overweight doping of n
Area doping p-type impurity doping concentration ＞ 1e18/cm3, the n heavily doped regions doping concentration higher than n doped substrate regions doping it is dense
Degree.
On the basis of above-mentioned technical proposal, further comprise following attached technical scheme：
Preferably, the n heavily doped regions thickness is 0.5 μm~5 μm, and n doped substrate regions thickness is 40 μm~100 μm, institute
It is 1e to state n heavily doped regions doping concentration16/cm3~1e18/cm3, the doping concentration of n doped substrate regions is 1e14/cm3~5e14/
cm3。
Preferably, the n doping forming process comprises the following steps：
Step 1: on n doped substrate regions make COOLMOS device architectures, including p posts, p+ doped regions, n+ doped regions,
Grid oxic horizon, grid polycrystalline silicon, gate metal electrode, source metal electrode；
Step 2: thinned wafer, using n heavy doping lithography mask versions, is carried on the back to appointed thickness to the n doped substrates after being thinned
Face is exposed, and is blocked using photoresist and is carried out local p-type impurity ion implanting, implantation dosage 1e13cm-2~3e14cm-2, note
Enter energy 50kev~1000kev；
Injected Step 3: carrying out the overweight Doped ions of n to the COOLMOS devices back side, implantation dosage 1e14cm-2~
7e15cm-2, Implantation Energy 10kev；
Step 4: using laser annealing, the annealing of appointed thickness is carried out to the back side；
Step 5: being metallized to the COOLMOS devices back side, drain metal electrode is formed；
Preferably, for thinned wafer to appointed thickness, the appointed thickness is 40 μm~100 μm in the step 2；
Preferably, the annealing of appointed thickness is carried out in the step 4 to the back side, the appointed thickness is 0.1 μm~5 μm；
Preferably, the source metal electrode is electrical connected with n+ doped regions, and the p+ doped regions surround n+ doped regions, institute
State p posts one end be connected with p+ doped regions and the other end then towards n heavily doped regions side extend, wherein the p posts and n heavy doping
It is n doped substrate regions between area, side of the n heavily doped regions opposite side then with the overweight doped regions of n is connected, and the overweight doped regions of n
Opposite side be then connected with drain metal electrode.
To achieve the object of the present invention, the present invention uses another technical scheme：One kind optimization diode reverse recovery characteristic
Device, it include drain region, p posts, p+ doped regions, n+ doped regions, grid oxic horizon, grid polycrystalline silicon, gate metal electrode,
Source metal electrode, and the drain region is mixed including the overweight doped regions of n, the n heavily doped regions adjacent with the overweight doped regions of n and n
Miscellaneous substrate zone, the n heavily doped regions are located in the n doped substrate regions of COOLMOS devices, the overweight doped regions of n and drain electrode gold
Belong to contact electrode, the overweight doped region doping p-type impurity doping concentration ＞ 1e of n18/cm3, the n heavily doped regions adulterate dense
Doping concentration of the degree higher than n doped substrate regions.
Preferably, the n heavily doped regions thickness is 0.5 μm~5 μm, and n doped substrate regions thickness is 40 μm~100 μm, institute
It is 1e to state n heavily doped regions doping concentration16/cm3~1e18/cm3, the doping concentration of n doped substrate regions is 1e14/cm3~5e14/
cm3。
Preferably, the source metal electrode is electrical connected with n+ doped regions, and the p+ doped regions surround n+ doped regions, institute
State p posts one end be connected with p+ doped regions and the other end then towards n heavily doped regions side extend, wherein the p posts and n heavy doping
It is n doped substrate regions between area, side of the n heavily doped regions opposite side then with the overweight doped regions of n is connected, and the overweight doped regions of n
Opposite side be then connected with drain metal electrode.
The method have the advantages that：
The common COOLMOS devices back side is exactly an overweight doped region of n, when body diode reverse is recovered, the pole of body two
Pipe can be equivalent to the P-i-N diode of a monolayer material, and this diode is break-over diode, and be served as a contrast by being adulterated in n
The n heavily doped regions of local are added in bottom, the buffer layer structure of local can be formed, improve body diode reverse recovery
Softness, backward voltage interconversion rate (dv/dt) is reduced, so as to optimize the reverse recovery characteristic of body diode.
Brief description of the drawings：
Fig. 1 is the device profile map of the present invention；
Fig. 2 is the corresponding device profile in a wherein step of the invention；
Fig. 3 is the corresponding device profile in another step of the present invention.
Embodiment
As Figure 1-3, the present invention provides a kind of method of optimization COOLMOS body diode reverse recovery characteristics, wherein
Drain region is formed at COOLMOS bottom devices, and drain region includes the overweight doped regions of n, n heavily doped regions and n doped substrate regions,
N heavily doped regions are located in the n doped substrates of COOLMOS devices, and n is overweight, and doped region is in contact with drain metal electrode, and n is overweight to be mixed
Miscellaneous area's doping p-type impurity concentration is very high, can form good Ohmic contact, n heavily doped regions doping concentration is higher than n doping linings
Bottom area, the cushion effect of local is formed at the COOLMOS devices back side, the recovery softness of body diode, while not shadow can be improved
The other specification of Chinese percussion instrument part.
Further improve is the implantation dosage 1e in n heavily doped regions13cm-2~3e14cm-2, Implantation Energy 50kev~
1000kev, it is sufficient to cushion is formed, and the body diode for improving COOLMOS devices recovers softness, and not to COOLMOS devices
Other specification impacts.
Further be that n is overweight Doped ions injection, the implantation dosage 1e of improving14cm-2~7e15cm-2, Implantation Energy
For 10kev, it is sufficient to form good Ohmic contact with drain metal electrode.
N heavily doped regions and the overweight doped region forming processes of n comprise the following steps：
Step 1: common COOLMOS device architectures are made in n doped substrates, including p posts 4, p+ doped regions 5, n+ mix
Miscellaneous area 6, grid oxic horizon 7, grid polycrystalline silicon 8, gate metal electrode 21, source metal electrode 22；
Step 2: thinned wafer is to 40 μm~100 μm of appointed thickness, using n heavy doping lithography mask versions, after being thinned
The n doped substrates back side is exposed, and is blocked using photoresist and is carried out local p-type impurity ion implanting, implantation dosage 1e13cm-2
~3e14cm-2, Implantation Energy 50kev~1000kev.
Injected Step 3: carrying out the overweight Doped ions of n to the device back side, implantation dosage 1e14cm-2~7e15cm-2, injection
Energy is 10kev.
Step 4: using laser annealing, the annealing of appointed thickness is carried out to the back side, does not influence COOLMOS devices front gold
Category.
Step 5: being metallized to the COOLMOS devices back side, drain metal electrode 23 is formed.
Similarly, the present invention provides a kind of device for optimizing diode reverse recovery characteristic, and it includes drain region, p posts 4, p
+ doped region 5, n+ doped regions 6, grid oxic horizon 7, grid polycrystalline silicon 8, gate metal electrode 21, source metal electrode 22, and leak
Polar region includes the adjacent n heavily doped regions 2 of the overweight doped regions 1 of n, doped region overweight with n 1 and n doped substrate regions 3, n heavily doped regions
2 in the n doped substrate regions 3 of COOLMOS devices, and n is overweight, and doped region 1 is in contact with drain metal electrode 23, doping that n is overweight
Adulterate p-type impurity doping concentration ＞ 1e in area 118/cm3, doping concentration of the doping concentration of n heavily doped regions 2 higher than n doped substrate regions 3.
Preferably, the thickness of n heavily doped regions 2 is 0.5 μm~5 μm, and the thickness of n doped substrate regions 3 is 40 μm~100 μm, and n is heavily doped
The miscellaneous doping concentration of area 2 is 1e16/cm3~1e18/cm3, the doping concentration of n doped substrate regions 3 is 1e14/cm3~5e14/cm3。
Preferably, source metal electrode 22 and n+ doped regions 6 are electrical connected, and p+ doped regions 5 surround n+ doped regions 6, p posts 4
One end be connected with p+ doped regions 5 and the other end then towards n heavily doped regions 2 side extend, wherein p posts 4 and n heavily doped regions 2 it
Between be n doped substrate regions 3, the side of the opposite side of n heavily doped regions 2 then doped region 1 overweight with n is connected, and the overweight doped regions 1 of n
Opposite side be then connected with drain metal electrode 23.
By introducing a n heavily doped region being spaced apart at the COOLMOS devices back side, junction depth is more overweight than n to be mixed the present invention
Miscellaneous area is deep, and so as to realize the buffering effect layer of regional area, it is reversely extensive that optimization can be reached when body diode reverse is recovered
The effect of multiple softness, so as to reduce the dv/dt of device, improves the reliability of device, reduces reverse recovery loss.
Embodiment
First, backing material prepares, and uses resistivity as 21 Ω cm, and the n-type area that thickness is 725 μm melts monocrystalline substrate 3,
Its crystal orientation is<100>；
2nd, COOLMOS device architectures, including p posts 4, p+ doped regions 5, n+ doped regions 6, grid are made in n doped substrates
Oxide layer 7, grid polycrystalline silicon 8, gate metal electrode 21, source metal electrode 22；
3rd, using thinned machine, thinned wafer is to 60 μm.As shown in Figure 2.
4th, using n heavy doping lithography mask versions, the n doped substrates back side after being thinned is exposed, hidden using photoresist
Gear carries out local n-type ion implanting, implantation dosage 1e14cm-2, Implantation Energy 1000kev, injection depth is about 1 μm, such as Fig. 3
It is shown.
5th, the photoresist in removal step four, the n-type of overall importance to the device back side is overweight, and Doped ions inject, injectant
Measure as 3e15cm-2, Implantation Energy 10kev.
6th, using laser annealing, the annealing of 1 μm of depth is carried out to chip back, have activated n heavy doping and the overweight doping of n
Ion, while do not influence COOLMOS device front metals.
7th, the COOLMOS devices back side is metallized, forms drain metal electrode 23.As shown in Figure 1.
The present invention is described in detail above by specific embodiment, but these not form the limit to the present invention
System.For example inject replacement n-type Doped ions using hydrogen and carry out making n heavily doped regions etc..The situation of the principle of the invention is not being departed from
Under, those skilled in the art can also make many modification and improvement, and these also should be regarded as protection scope of the present invention.Certainly on
The technical concepts and features of embodiment only to illustrate the invention are stated, its object is to allow person skilled in the art to understand this
The content of invention is simultaneously implemented according to this, and it is not intended to limit the scope of the present invention.It is all according to main technical schemes of the present invention
The equivalent transformation that is done of Spirit Essence or modification, should all be included within the scope of the present invention.
Claims (9)
1. a kind of method for optimizing body diode reverse recovery characteristics, it is handled in COOLMOS devices, wherein drain region shape
Into in COOLMOS bottom devices, and the drain region includes the overweight doped regions of n (1), the n adjacent with the overweight doped regions of n (1) weights
Doped region (2) and n doped substrate regions (3), it is characterised in that：The n heavily doped regions (2) are located at the n doping of COOLMOS devices
In substrate zone (3), the overweight doped regions of n (1) are in contact with drain metal electrode (23), the overweight doped regions of n (1) doping
P-type impurity doping concentration ＞ 1e18/cm3, n heavily doped regions (2) doping concentration higher than n doped substrate regions (3) doping it is dense
Degree.
A kind of 2. method for optimizing body diode reverse recovery characteristics according to claim 1, it is characterised in that：The n
Heavily doped region (2) thickness is 0.5 μm~5 μm, and n doped substrate regions (3) thickness is 40 μm~100 μm, the n heavily doped regions (2)
Doping concentration is 1e16/cm3~1e18/cm3, the doping concentration of n doped substrate regions (3) is 1e14/cm3~5e14/cm3。
A kind of 3. method for optimizing diode reverse recovery characteristic according to claim 2, it is characterised in that：The n mixes
Miscellaneous forming process comprises the following steps：
Step 1: COOLMOS device architectures are made on n doped substrate regions (3), including p posts (4), p+ doped regions (5), n+ mix
Miscellaneous area (6), grid oxic horizon (7), grid polycrystalline silicon (8), gate metal electrode (21), source metal electrode (22)；
Step 2: thinned wafer, using n heavy doping lithography mask versions, enters to appointed thickness to the n doped substrates back side after being thinned
Row exposure, blocked using photoresist and carry out local p-type impurity ion implanting, implantation dosage 1e13cm-2~3e14cm-2, inject energy
Measure 50kev~1000kev；
Injected Step 3: carrying out the overweight Doped ions of n to the COOLMOS devices back side, implantation dosage 1e14cm-2~7e15cm-2,
Implantation Energy is 10kev；
Step 4: using laser annealing, the annealing of appointed thickness is carried out to the back side；
Step 5: being metallized to the COOLMOS devices back side, drain metal electrode (23) is formed.
A kind of 4. method for optimizing diode reverse recovery characteristic according to claim 3, it is characterised in that：The step
For thinned wafer to appointed thickness, the appointed thickness is 40 μm~100 μm in two.
A kind of 5. method for optimizing diode reverse recovery characteristic according to claim 3, it is characterised in that：The step
The annealing of appointed thickness is carried out in four to the back side, the appointed thickness is 0.1 μm~1 μm.
A kind of 6. method for optimizing diode reverse recovery characteristic according to claim 3, it is characterised in that：The source electrode
Metal electrode (22) is electrical connected with n+ doped regions (6), and the p+ doped regions (5) surround n+ doped regions (6), the p posts (4) one
End is connected with p+ doped regions (5) and the other end then extends towards the side of n heavily doped regions (2), wherein the p posts (4) and n are heavily doped
It is n doped substrate regions (3) that side of n heavily doped regions (2) opposite side then with the overweight doped regions of n (1) is connected between miscellaneous area (2),
And the opposite side of the overweight doped regions of n (1) is then connected with drain metal electrode (23).
7. a kind of device for optimizing diode reverse recovery characteristic, it includes drain region, p posts (4), p+ doped regions (5), n+ doping
Area (6), grid oxic horizon (7), grid polycrystalline silicon (8), gate metal electrode (21), source metal electrode (22), and the leakage
Polar region includes the overweight doped regions of n (1) and the adjacent n heavily doped regions (2) of the overweight doped regions of n (1) and n doped substrate regions (3),
It is characterized in that：The n heavily doped regions (2) are located in the n doped substrate regions (3) of COOLMOS devices, the overweight doped regions of n
(1) it is in contact with drain metal electrode (23), the overweight doped regions of n (1) the doping p-type impurity doping concentration ＞ 1e18/cm3, institute
State the doping concentration that n heavily doped regions (2) doping concentration is higher than n doped substrate regions (3).
A kind of 8. method for optimizing body diode reverse recovery characteristics according to claim 7, it is characterised in that：The n
Heavily doped region (2) thickness is 0.5 μm~5 μm, and n doped substrate regions (3) thickness is 40 μm~100 μm, the n heavily doped regions (2)
Doping concentration is 1e16/cm3~1e18/cm3, the doping concentration of n doped substrate regions (3) is 1e14/cm3~5e14/cm3。
A kind of 9. method for optimizing body diode reverse recovery characteristics according to claim 7, it is characterised in that：The source
Pole metal electrode (22) is electrical connected with n+ doped regions (6), and the p+ doped regions (5) surround n+ doped regions (6), the p posts (4)
One end is connected with p+ doped regions (5) and the other end then extends towards the side of n heavily doped regions (2), wherein the p posts (4) and n weights
It is n doped substrate regions (3) that side of n heavily doped regions (2) opposite side then with the overweight doped regions of n (1) is connected between doped region (2)
Connect, and the opposite side of the overweight doped regions of n (1) is then connected with drain metal electrode (23).
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| CN201710560598.3A CN107359125A (en) | 2017-07-03 | 2017-07-03 | A kind of method and device for optimizing body diode reverse recovery characteristics |
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| CN201710560598.3A CN107359125A (en) | 2017-07-03 | 2017-07-03 | A kind of method and device for optimizing body diode reverse recovery characteristics |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108054212A (en) * | 2017-12-22 | 2018-05-18 | 南京方旭智芯微电子科技有限公司 | The manufacturing method of superjunction field-effect tube and superjunction field-effect tube |
| CN109713041A (en) * | 2018-12-27 | 2019-05-03 | 四川立泰电子有限公司 | A kind of structure-improved suitable for superjunction DMOS device |
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| CN104282759A (en) * | 2013-07-10 | 2015-01-14 | 富士电机株式会社 | Super junction MOSFET, method of manufacturing the same, and complex semiconductor device |
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| CN102403354A (en) * | 2010-09-15 | 2012-04-04 | 无锡华润上华半导体有限公司 | CoolMOS device and manufacturing method for same |
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| CN109713041A (en) * | 2018-12-27 | 2019-05-03 | 四川立泰电子有限公司 | A kind of structure-improved suitable for superjunction DMOS device |
| CN109713041B (en) * | 2018-12-27 | 2022-05-24 | 四川立泰电子有限公司 | Improved structure suitable for super junction DMOS device |
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Application publication date: 20171117 |