CN106898652B - A kind of silicon carbide VDMOS device - Google Patents
A kind of silicon carbide VDMOS device Download PDFInfo
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- CN106898652B CN106898652B CN201710137017.5A CN201710137017A CN106898652B CN 106898652 B CN106898652 B CN 106898652B CN 201710137017 A CN201710137017 A CN 201710137017A CN 106898652 B CN106898652 B CN 106898652B
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 17
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 17
- 239000002019 doping agent Substances 0.000 claims abstract description 8
- 230000003247 decreasing effect Effects 0.000 claims abstract description 7
- 238000009413 insulation Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 6
- 125000005842 heteroatom Chemical group 0.000 abstract description 3
- 238000005457 optimization Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention proposes a kind of silicon carbide VDMOS devices.Compared to traditional structure, main innovation of the invention is the method that the area JFET is laterally adulterated using variation.Traditional planar gate silicon carbide VDMOS is in order to reduce the area the JFET resistance under device on-state, the usually whole dopant dose for improving the area JFET, however when excessively high area JFET is entrained in device pressure resistance, to will lead to electric field at gate oxide center excessively high and puncture.The present invention in the area JFET using the method laterally adulterated of variation, the dopant dose in the area JFET from p trap to far from successively decreasing at p trap.When break-over of device, conducting resistance is reduced；When pressure-resistant, gate oxide electric field spike is reduced at JFET district center due to low-doped, the highly doped hetero moiety of two sides raises two sides gate oxide lower electric field originally, and the electric field in gate oxide is transversely distributed more uniform.The method of the area JFET variation doping can effectively reduce device on-resistance, while not influence device pressure resistance in doping optimization section.
Description
Technical field
Invention belongs to power semiconductor technologies field, is related to a kind of silicon carbide VDMOS device.
Background technique
SiC (silicon carbide) is used as third generation semiconductor material with wide forbidden band, has high critical breakdown electric field, is suitble to manufacture high
Press large power semiconductor device.When making planar gate silicon carbide VDMOS device, in order to reduce the area the JFET resistance of device, often
The whole dopant dose for improving the area JFET, by reducing the width of depletion region in the area JFET to increase the conductive path in the area JFET simultaneously
Reduce the unit area resistance in the area JFET.
However due to the high critical breakdown electric field of SiC itself and relative to the higher dielectric constant of silica, cause
Its gate oxide bears high electric field to SiC MOSFET in the bar state, and field distribution is anxious from gate oxide center to source
Quick depletion.For planar gate SiC MOSFET, the area JFET dopant dose is higher, highest of the gate oxide in identical resistance to pressure
Electric field is also higher, it is generally recognized that the maximum electric field on gate oxide cannot be guaranteed MOSFET reliably and with long-term when being greater than 3MV/cm
Sex work, this limitation greatly reduce the upper limit of the area JFET dopant dose.
Summary of the invention
The purpose of the present invention proposes a kind of planar gate SiC VDMOS with low on-resistance aiming at the above problem
Device.
The technical scheme is that a kind of silicon carbide VDMOS device, including gate structure, source configuration, drain junction
Structure, drift region 7 and the area JFET 8.Wherein drift region 7 is located on drain electrode structure, and source configuration is located on drift region 7, source electrode
The area JFET 8 is formed between structure；
The source configuration includes P type trap zone 3 and N-type source region 4 and p-type body contact zone 5 positioned at P type trap zone top,
The N-type source region 4 and the common exit of p-type body contact zone 5 are source electrode；N-type source region 4 is far from 5 side of p-type body contact zone and p-type
Well region forms channel region between 3 edge；
The gate structure is covered on channel region and the area JFET 8, and the gate structure includes gate insulation layer 1 and is located at
Polysilicon or metal grid region 2 on gate insulation layer, 2 exit of grid region are grid；
The drain electrode structure is located under drift region, including N-type drain region 6, and 6 exit of N-type drain region is drain electrode；
Its feature is being:
The dopant dose in the area JFET 8 is gradually dropped from the contact surface of the area JFET 8 and P type trap zone 3 to the middle part in the area JFET 8
It is low.
Further, the area JFET 8 is from the contact surface of the area JFET 8 and P type trap zone 3 to the middle part in the area JFET 8 successively shape
At 1st area, 2 areas n, area, doping concentration by 1st area, 2 areas n, area decreasing order, n >=
2。
Further, 1st area, 2 areas n, area junction depth be variation, junction depth press 1st area, 2
The area n, area decreasing order.
Beneficial effects of the present invention are, relative to traditional structure, the present invention has the advantages that conducting resistance is low, relative to
The device that the area JFET is integrally adulterated, in the case where device has same forward conduction resistance, this structure can be reduced under blocking state
Gate oxide peak electric field improves device reliability.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of embodiment 1；
Fig. 2 is the structural schematic diagram of embodiment 2；
Fig. 3 is the structural schematic diagram of embodiment 3.
Specific embodiment
With reference to the accompanying drawings and examples, the technical schemes of the invention are described in detail:
Embodiment 1
As shown in Figure 1, this example is the area JFET variation laterally doping SiC power MOSFET, including gate structure, source junction
Structure, drain electrode structure, drift region 7 and the area JFET 8.Wherein drift region 7 is located on drain electrode structure, and source configuration is located at drift region 7
On, the area JFET 8 is formed between source configuration；
The source configuration includes P type trap zone 3 and N-type source region 4 and p-type body contact zone 5 positioned at P type trap zone top,
The N-type source region 4 and the common exit of p-type body contact zone 5 are source electrode；N-type source region 4 is far from 5 side of p-type body contact zone and p-type
Well region forms channel region between 3 edge；
The gate structure is covered on channel and the area JFET 8, and the gate structure includes gate insulation layer 1 and is located at grid
Polysilicon or metal grid region 2 on insulating layer, 2 exit of grid region are grid；
The drain electrode structure is located under drift region, including N-type drain region 6, and 6 exit of N-type drain region is drain electrode；
It is characterized in that:
For the dopant dose in the area JFET 8 close to 3 interface of the area JFET 8/P type well region height, this separate interface is low.
The working principle of this example are as follows:
When new device is in blocking state, highly doped hetero moiety of the area JFET at P type trap zone can lift gate oxide thereon
The middle lower electric field of script, the area JFET will not make the electric field mistake in gate oxide thereon far from the low-mix hetero moiety at P type trap zone
Height, the electric field in entire gate oxide are transversely distributed more uniform；When forward conduction, the heavily doped region on p trap side can make JFET
Width of depletion region in area shortens, this has not only broadened the guiding path of electronics, while unspent high-doped zone is alternatively arranged as
The low impedance path of electronic conduction significantly reduces the conducting resistance of device.
Embodiment 2
As shown in Fig. 2, the structure of this example and embodiment 1 is essentially identical, different places is the area JFET 8 from close
3 interface of the area JFET 8/P type well region to far from the interface formed 1st area, 2 areas n, area, doping concentration by 1st area,
2 area n, area decreasing orders, n >=2.
Compared with Example 1, it is easier to realize in technique in this example.
Embodiment 3
As shown in figure 3, the structure of this example and embodiment 2 is essentially identical, different places is 1st area, 2
The junction depth in the area n, area is variation, and junction depth presses 1st area, 2 area n, area decreasing orders.
Compared with Example 2, this example can simplify the area JFET ion injecting process.
Claims (3)
1. a kind of silicon carbide VDMOS device, including gate structure, source configuration, drain electrode structure, drift region (7) and the area JFET
(8)；Wherein drift region (7) are located on drain electrode structure, and source configuration is located on drift region (7), and N is formed between source configuration
The area type JFET (8)；
The source configuration includes P type trap zone (3) and N-type source region (4) and p-type body contact zone positioned at P type trap zone top
(5), the N-type source region (4) and the common exit of p-type body contact zone (5) are source electrode；N-type source region (4) is far from p-type body contact zone
(5) channel region is formed between side and P type trap zone (3) edge；
The gate structure is covered on channel region and the area JFET (8), and the gate structure includes gate insulation layer (1) and is located at
Polysilicon or metal grid region (2) on gate insulation layer, the polysilicon or metal grid region (2) exit are grid；
The drain electrode structure is located under drift region, including N-type drain region (6), and N-type drain region (6) exit is drain electrode；
It is characterized in that:
The dopant dose of the area JFET (8) from the contact surface of the area JFET (8) and P type trap zone (3) to the middle part of the area JFET (8) by
Gradually reduce.
2. a kind of silicon carbide VDMOS device according to claim 1, which is characterized in that the area JFET (8) is from the area JFET
(8) and in the middle part of the contact surface of P type trap zone (3) to the area JFET (8) 1st area, 2 areas n, area are sequentially formed, is mixed
Decreasing order of the miscellaneous concentration by 1st area, 2 areas n, area, n >=2.
3. a kind of silicon carbide VDMOS device according to claim 2, which is characterized in that 1st area, 2
The junction depth in the area n, area is variation, and junction depth presses 1st area, 2 area n, area decreasing orders.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710137017.5A CN106898652B (en) | 2017-03-09 | 2017-03-09 | A kind of silicon carbide VDMOS device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710137017.5A CN106898652B (en) | 2017-03-09 | 2017-03-09 | A kind of silicon carbide VDMOS device |
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| Publication Number | Publication Date |
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| CN106898652A CN106898652A (en) | 2017-06-27 |
| CN106898652B true CN106898652B (en) | 2019-06-04 |
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| CN107302024A (en) * | 2017-07-26 | 2017-10-27 | 电子科技大学 | A kind of carborundum VDMOS device |
| CN108091695B (en) * | 2017-12-13 | 2020-08-28 | 南京溧水高新创业投资管理有限公司 | Vertical double-diffused field effect transistor and manufacturing method thereof |
| CN112447842A (en) * | 2019-08-28 | 2021-03-05 | 比亚迪半导体股份有限公司 | Planar gate MOSFET and manufacturing method thereof |
| CN114613849B (en) * | 2022-05-10 | 2022-08-12 | 深圳市威兆半导体股份有限公司 | Silicon carbide MOS device for improving short circuit characteristic |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2007070050A1 (en) * | 2005-12-14 | 2007-06-21 | Freescale Semiconductor, Inc. | Power mosfet and method of making the same |
| US20080142811A1 (en) * | 2006-12-13 | 2008-06-19 | General Electric Company | MOSFET devices and methods of fabrication |
| JP4309967B2 (en) * | 2007-10-15 | 2009-08-05 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
| TW201019473A (en) * | 2008-11-13 | 2010-05-16 | Anpec Electronics Corp | Semiconductor device with a low JFET region resistance |
| US9331197B2 (en) * | 2013-08-08 | 2016-05-03 | Cree, Inc. | Vertical power transistor device |
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Effective date of registration: 20230109 Address after: 310051 1-1201, No. 6, Lianhui street, Xixing street, Binjiang District, Hangzhou City, Zhejiang Province Patentee after: Hangzhou Xinmai Semiconductor Technology Co.,Ltd. Address before: 611731, No. 2006, West Avenue, hi tech West District, Sichuan, Chengdu Patentee before: University of Electronic Science and Technology of China |
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