CN105097911B - A kind of HEMT device with junction semiconductor layer - Google Patents
A kind of HEMT device with junction semiconductor layer Download PDFInfo
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- CN105097911B CN105097911B CN201510456005.XA CN201510456005A CN105097911B CN 105097911 B CN105097911 B CN 105097911B CN 201510456005 A CN201510456005 A CN 201510456005A CN 105097911 B CN105097911 B CN 105097911B
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- 238000002161 passivation Methods 0.000 claims description 16
- 229910002704 AlGaN Inorganic materials 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 4
- 229910052593 corundum Inorganic materials 0.000 claims description 4
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 4
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- 239000010980 sapphire Substances 0.000 claims description 3
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 17
- 229910002601 GaN Inorganic materials 0.000 description 14
- 238000005530 etching Methods 0.000 description 10
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 9
- 229910017083 AlN Inorganic materials 0.000 description 8
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
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- 229910052737 gold Inorganic materials 0.000 description 2
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
Abstract
The invention belongs to technical field of semiconductors, more particularly to a kind of HEMT device with junction semiconductor layer.The device of the present invention, predominantly grows one layer of junction semiconductor layer, junction semiconductor layer and barrier layer formation two-dimensional hole gas (2DHG) by the barrier layer upper surface between grid leak.Gate metal forms rectifier structure with junction semiconductor layer and avoids adding the leakage current for causing grid 2DHG 2DEG during malleation on grid, while blocking 2DHG using separation layer between drain electrode and junction semiconductor；On the other hand, 2DHG and 2DEG formation polarization superjunction between grid leak, assisted depletion drift region during blocking state, it is effective to improve the electric field concentration effect that device gate leans on drain terminal, meanwhile, the contact portion in p-type doped region and n-type doping area can introduce a new electric field spike, so that device surface Electric Field Distribution is more uniform, so as to improve the breakdown voltage of device.Present invention is particularly suitable for HEMT device.
Description
Technical field
The invention belongs to technical field of semiconductors, more particularly to a kind of HEMT (High with junction semiconductor layer
Electron Mobility Transistor, HEMT) device.
Background technology
Wide bandgap semiconductor gallium nitride (GaN) has high critical breakdown electric field (~3.3 × 106V/cm), high electron mobility
The characteristics such as rate (~2000cm2/Vs), and the hetero-junctions HEMT (HEMT) based on GaN material also has
Two-dimensional electron gas (2DEG) raceway groove of high concentration (~1013cm-2) so that GaN HEMT devices have reverse BV it is high,
The characteristic such as forward conduction resistance is low, working frequency is high, has huge in high current, low-power consumption, High-tension Switch Devices application field
Application prospect.
The key of device for power switching is to realize high-breakdown-voltage, low on-resistance and high reliability.HEMT device is hit
Wear mainly due to the leakage current of grid schottky junction and by caused by the leakage current of cushion.Improve device pressure-resistant,
Need to increase the thickness and quality of cushion on longitudinal direction, this is mainly determined by technology level；The head of district that drifts about is needed in transverse direction
Degree increase, this not only increases the chip area of device (or circuit), cost increase, more seriously, the electric conduction of device
Resistance increase, and then cause power consumption to sharply increase, and devices switch speed is also decreased.
The excellent specific properties such as the high critical breakdown electric field in order to make full use of GaN material, raising device is pressure-resistant, in the industry researcher
Many researchs are carried out.Wherein field plate techniques be it is a kind of be used for improving the pressure-resistant conventional terminal technology of device, document (J.Li,
et.al.“High breakdown voltage GaN HFET with field plate”IEEE Electron Lett.,
Vol.37, no.3, pp.196-197, February.2001.) employ field plate with grid short circuit, as shown in figure 1, field plate draws
Enter the curvature effect that can reduce main knot and electric field spike, so as to improve pressure-resistant.But the introducing of field plate can make device parasitic electricity
Hold increase, influence the high frequency and switching characteristic document of device.(Akira Nakajima,et.al.“GaN-Based Super
Heterojunction Field Effect Transistors Using the Polarization Junction
Concept " IEEE Electron Device Letters, vol.32, no.4, pp.542-544,2011) using polarization superjunction
Thought, above the AlGaN potential barrier of drift region portion grow one layer of top layer GaN, and its interface formed two-dimensional hole gas
(2DHG), 2DHG forms natural " superjunction " with 2DEG below, when blocking pressure-resistant, assisted depletion drift region, optimizer
Part transverse electric field, improves pressure-resistant purpose, as shown in Figure 2 so as to reach.But top layer GaN forms the Europe in hole with gate electrode
Nurse is contacted, and in forward conduction, gate leakage current can be produced when grid voltage is larger, grid swing is limited.
For AlGaN/GaN HEMT devices, enhanced (normally-off) HEMT device is than depletion type (open type) HEMT
Device has more advantages, and it realizes that technology is also the problem of researchers extremely pay close attention to.Document (W.Saito, et.al.,
“Recessed-gate structure approach toward normally off high-voltage AlGaN/GaN
HEMT for power electronics applications,”IEEE Trans.Electron Devices,vol.53,
No.2, pp.356-362,2006) report a kind of accurate enhanced high pressure AlGaN/GaN HEMT are realized using slot grid structure,
As shown in figure 3, recessed grid etching can effectively exhaust 2DEG concentration below grid, threshold voltage is greatly enhanced, but recessed grid
Etching needs to accurately control etching injury caused by etching depth and reduction corona treatment.
The content of the invention
It is to be solved by this invention, aiming above mentioned problem, propose a kind of HEMT device with junction semiconductor layer.
To achieve the above object, the present invention is adopted the following technical scheme that：
A kind of HEMT device with junction semiconductor layer, including substrate 1, the and of cushion 2 for being arranged on the upper surface of substrate 1
The barrier layer 3 of the upper surface of cushion 2 is arranged on, the contact surface formation of the cushion 2 and barrier layer 3 has Two-dimensional electron channeling
First hetero-junctions in road；The two ends of the upper surface of barrier layer 3 have source electrode 4 and drain electrode 5, the upper surface of barrier layer 3 respectively
Middle part has grid structure；The upper surface of barrier layer 3 between the source electrode 4 and grid structure has dielectric passivation layer 10, institute
Stating the upper surface of barrier layer 3 between drain electrode 5 and grid structure has junction semiconductor layer 8；The junction semiconductor layer 8 and gesture
Second hetero-junctions of the contact surface formation with two-dimensional hole gas of barrier layer 3；Characterized in that, the junction semiconductor layer 8 is by p-type
Doped region 81 and n-type doping area 82 are constituted, and the p-type doped region 81 is connected with grid structure, the n-type doping area 82 and electric leakage
The insulating course 11 of two-dimensional hole gas can be blocked by having between pole 5；The grid structure is by insulation gate medium 7 and metal gate electrode 6
Constitute, the insulation gate medium 7 is connected with dielectric passivation layer 10, barrier layer 3 and p-type doped region 81 respectively, its shape of cross section
For U-shape structure, the metal gate electrode 6 is located in insulation gate medium 7, and the metal gate electrode 6 extends along device horizontal direction
And it is covered in the upper surface of insulation gate medium 7；The metal gate electrode 6 also extends to the upper surface of p-type doped region 81 and and junction type
Rectifier structure 9 is formed between semiconductor layer 8.
The total technical scheme of the present invention, one layer of junction semiconductor layer is grown by the barrier layer upper surface between grid leak,
Junction semiconductor layer and barrier layer formation two-dimensional hole gas (2DHG).Gate metal forms rectifier structure with junction semiconductor layer and kept away
Exempt to add the leakage current for causing grid -2DHG-2DEG during malleation on grid, isolate while being used between drain electrode and junction semiconductor
Layer blocks 2DHG；On the other hand, the 2DHG between grid leak and 2DEG formation polarization superjunction, assisted depletion drifts about during blocking state
Area, effectively improves the electric field concentration effect that device gate leans on drain terminal, meanwhile, the contact site in p-type doped region and n-type doping area
Point, a new electric field spike can be introduced so that device surface Electric Field Distribution is more uniform, so that the OFF state for improving device punctures
Voltage.
Further, the upper surface of the junction semiconductor layer 8 between the metal gate electrode 6 and drain electrode 5 has second
Dielectric passivation layer 13, direction extension of the drain electrode 5 along the upper table of second medium passivation layer 13 towards metal gate electrode 6, is formed
Leak field plate electrode 12.
The purpose of such scheme is, by leaking the introducing of field plate 12, can effectively reduce the electric field spike of drain terminal, keep away
Exempt from electric leakage to occur to puncture in advance.
Further, the grid structure is planar insulated gate structure, the lower surface and barrier layer of the insulation gate medium 7
3 upper surface connection.
Further, the grid structure is groove insulated gate structure, and the bottom of the insulation gate medium 7 is located at barrier layer
In 3.
Further, the grid structure is groove insulated gate structure, the lower surface and cushion of the insulation gate medium 7
2 upper surface connection.
Further, it is characterised in that the rectifier structure 9 is that metal gate electrode 6 contacts to form Xiao with p-type doped region 81
Special base barrier contact.
Further, the upper surface of institute's p-type doped region 81 and grid structure junction is doped with N-type semiconductor formation PN junction
Rectification, the rectifier structure 9 is that metal gate electrode 6 forms Ohmic contact with PN junction rectification.
Further, the insulating course 11 is physics insulating course or ion implanting insulating course.
In such scheme, physics insulating course falls the partial etching between junction semiconductor layer 8 and drain electrode 5 to refer to, and makes
Isolate between junction semiconductor layer 8 and drain electrode 5；Injection insulating course of leaving office refers between junction semiconductor layer 8 and drain electrode 5
Inject the N-type separation layer of N-type semiconductor formation heavy doping.
Further, the material that the insulation gate medium 7 is used is Al2O3 or other single or multiple lift dielectric material
Material；The material that the junction semiconductor layer 8 is used is one kind in Si, SiC, GaN, AlN, AlGaN, InGaN, InAlN or several
The combination planted；The cushion 2 and barrier layer 3 use material for one kind in GaN, AlN, AlGaN, InGaN, InAlN or several
The combination planted；The material that the substrate 1 is used is one or more of combination in sapphire, silicon, SiC, AlN or GaN.
Beneficial effects of the present invention are effectively to improve the electric field concentration effect that device gate leans on drain terminal, while being mixed in p-type
Miscellaneous area and the contact portion in n-type doping area, introduce a new electric field spike so that device surface Electric Field Distribution is more uniform,
So as to improve the breakdown voltage of device.
Brief description of the drawings
Fig. 1 is the HEMT device structure with field plate；
Fig. 2 is with the polarization superjunction HEMT device structure being electrically connected with gate electrode；
Fig. 3 is the HEMT device structure with groove insulated gate structure；
Fig. 4 is the HEMT device structure of embodiment 1；
Fig. 5 is the HEMT device structure of embodiment 2；
Fig. 6 is the HEMT device structure of embodiment 3；
Fig. 7 is the HEMT device structure of embodiment 4；
Fig. 8 is the HEMT device structure of embodiment 5；
Fig. 9 is the HEMT device structure of embodiment 6；
It is reverse resistance to conventional MOS-HEMT-structure that Figure 10 is the super hetero-junctions HEMT device structure of junction type proposed by the present invention
Pressure ratio is relatively schemed；
It is reverse resistance to conventional MOS-HEMT-structure that Figure 11 is the super hetero-junctions HEMT device structure of junction type proposed by the present invention
Electric Field Distribution compares figure during pressure.
Embodiment
With reference to the accompanying drawings and examples, technical scheme is described in detail：
Embodiment 1
As shown in figure 4, this example includes substrate 1, is arranged on the cushion 2 of the upper surface of substrate 1 and is arranged on the upper table of cushion 2
The barrier layer 3 in face, the contact surface formation first with Two-dimensional electron gas channel (2DEG) of the cushion 2 and barrier layer 3 is different
Matter knot；The two ends of the upper surface of barrier layer 3 have source electrode 4 and drain electrode 5 respectively, and the upper surface middle part of barrier layer 3 has grid
Pole structure；The upper surface of barrier layer 3 between the source electrode 4 and grid structure has a dielectric passivation layer 10, the drain electrode 5 with
The upper surface of barrier layer 3 between grid structure has junction semiconductor layer 8；8 contact with barrier layer 3 of the junction semiconductor layer
Face forms the second hetero-junctions with two-dimensional hole gas (2DHG)；Characterized in that, the junction semiconductor layer 8 is adulterated by p-type
Area 81 and n-type doping area 82 are constituted, and the p-type doped region 81 is connected with grid structure, the n-type doping area 82 and drain electrode 5
Between have can block the insulating course 11 of two-dimensional hole gas；The grid structure is by insulation gate medium 7 and the structure of metal gate electrode 6
Into the insulation gate medium 7 is connected with dielectric passivation layer 10, barrier layer 3 and p-type doped region 81 respectively, and its shape of cross section is U
Type structure, the metal gate electrode 6 is located in insulation gate medium 7, and the metal gate electrode 6 extends and covered along device horizontal direction
Cover the upper surface in insulation gate medium 7；The metal gate electrode 6 also extends to the upper surface of p-type doped region 81 and partly led with junction type
Rectifier structure 9 is formed between body layer 8；The rectifier structure 9 is that metal gate electrode 6 contacts to form Schottky with p-type doped region 81
Barrier contact, wherein insulating course 11 are to block 2DHG using ion implanting mode.
The operation principle of this example is：First, the p type island region domain of rectifier structure and junction semiconductor layer forms Schottky barrier,
Avoid adding the leakage current for causing grid -2DHG-2DEG during malleation on grid, while isolation structure is blocked using ion implanting mode
2DHG；Secondly junction semiconductor layer/barrier layer/cushion forms polarization super-junction structure, during blocking state, the drift of 2DHG assisted depletions
Area is moved, the electric field concentration effect that device gate leans on drain terminal is effectively improved, makes device surface Electric Field Distribution more uniform, obtain pole
Big pressure-resistant lifting.
Embodiment 2
As shown in figure 5, this example place different from embodiment 1 is, this example device rectifier structure 9 is PN junction rectification, its
His structure is same as Example 1.The p type island region domain of rectifier structure and junction semiconductor layer forms PN junction, it is to avoid when adding malleation on grid
Grid -2DHG-2DEG leakage current is caused, causes device to puncture in advance.
Embodiment 3
As shown in fig. 6, this example place different from embodiment 1 is, insulating course 11 blocks 2DHG using cutting mode, uses
Grid -2DHG-2DEG leakage current caused by when avoiding because of grid plus malleation and cause device to puncture in advance.
Embodiment 4
As shown in fig. 7, this example place different from embodiment 1 is, this example device is in the top of junction type junction semiconductor layer 8
The dielectric passivation layer 10 between dielectric passivation layer 10, grid leak is formed by forming leakage field plate 12 above leakage side, it is electric with drain electrode 5
It is connected.The surface state of device can be improved using dielectric passivation layer, suppress current collapse.The dielectric passivation layer material can be adopted
With with gate medium identical material and being formed simultaneously, or using typical media materials such as SiNx, Al2O3, AlN.At the same time,
The introducing of field plate 12 is leaked, the electric field spike of drain terminal can be effectively reduced, it is to avoid electric leakage occurs to puncture in advance.
Embodiment 5
As shown in figure 8, this example place different from embodiment 1 is, this example device grids structure is groove insulated gate knot
Structure.Groove insulated gate structure all etches grid lower barrierlayer, realizes enhancement device.Recessed grid etching can effectively exhaust grid
2DEG concentration below pole, is greatly enhanced threshold voltage, but all etching can cause to damage grid lower barrierlayer to buffering bed boundary
Wound, influences the electric property of device.
Embodiment 6
As shown in figure 9, this example place different from embodiment 5 is, groove insulated gate structure is by grid lower barrierlayer part
Etching, realizes enhancement device, compared with Example 5, and grid lower barrierlayer partial etching can be avoided because of etching to a certain extent
Caused interface damage.
The HEMT device of the present invention, can use sapphire, silicon, carborundum (SiC), aluminium nitride (AlN) or gallium nitride
(GaN) one or more of combinations in as substrate layer 1 material；One kind or several in GaN, AlN, AlGaN can be used
Kind combination as cushion 2 material；One or more of groups in GaN, AlN, AlGaN, InGaN, InAlN can be used
Cooperate as the material of barrier layer 3；It can use one or more of in Si, SiC, GaN, AlN, AlGaN, InGaN, InAlN
Combine the material as junction type junction semiconductor layer 8；For passivation layer 10, the conventional material of industry is SiNx, can also be used
The dielectric materials such as Al2O3, AlN, insulation gate medium 7 can be used and passivation layer identical material；Source electrode 4, drain electrode 5 are typically adopted
With metal alloy, conventional has Ti/Al/Ni/Au or Mo/Al/Mo/Au etc.；Gate electrode 6 is typically using the larger metal of work function
Alloy, such as Ni/Au or Ti/Au.
Figure 10, Figure 11 are the super hetero-junctions HEMT device structure of junction type proposed by the present invention and conventional MOS-HEMT-structure respectively
It is reverse it is pressure-resistant compare figure, reversely it is pressure-resistant when Electric Field Distribution compare figure.Emulated using Sentaurus TCAD softwares, two kinds
Structure is 10.5 μm in lateral device dimensions, and grid length is 1.5 μm, and grid leak distance is that under conditions of 5 μm, the present invention is carried
The breakdown voltage of the structure gone out brings up to 880V from conventional MOS-HEMT 548V, and breakdown voltage improves 60%.
Claims (10)
1. a kind of HEMT device with junction semiconductor layer, including substrate (1), the cushion for being arranged on substrate (1) upper surface
(2) and it is arranged on the contact surface formation tool of the barrier layer (3) of cushion (2) upper surface, the cushion (2) and barrier layer (3)
There is the first hetero-junctions of Two-dimensional electron gas channel；The two ends of barrier layer (3) upper surface have source electrode (4) and electric leakage respectively
Pole (5), barrier layer (3) upper surface middle part has grid structure；Barrier layer (3) of the source electrode (4) between grid structure
Upper surface has dielectric passivation layer (10), and barrier layer (3) upper surface of the drain electrode (5) between grid structure has junction type
Semiconductor layer (8)；The junction semiconductor layer (8) and the contact surface formation second with two-dimensional hole gas of barrier layer (3) are different
Matter knot；Characterized in that, the junction semiconductor floor (8) is made up of p-type doped region (81) and n-type doping area (82), the p-type
Doped region (81) is connected with grid structure, and two-dimensional hole gas can be blocked by having between the n-type doping area (82) and drain electrode (5)
Insulating course (11)；The grid structure is made up of insulation gate medium (7) and metal gate electrode (6), the insulation gate medium (7)
It is connected respectively with dielectric passivation layer (10), barrier layer (3) and p-type doped region (81), its shape of cross section is U-shape structure, described
Metal gate electrode (6) is located in insulation gate medium (7), and the metal gate electrode (6) extends and is covered in along device horizontal direction
The upper surface of insulation gate medium (7)；The metal gate electrode (6) also extend to p-type doped region (81) upper surface and with junction type half
Rectifier structure (9) is formed between conductor layer (8).
2. a kind of HEMT device with junction semiconductor layer according to claim 1, it is characterised in that the metal gate
The upper surface of junction semiconductor layer (8) between electrode (6) and drain electrode (5) has second medium passivation layer (13), the leakage
Direction extension of the electrode (5) along second medium passivation layer (13) upper table towards metal gate electrode (6), forms leakage field plate electrode
(12)。
3. a kind of HEMT device with junction semiconductor layer according to claim 1, it is characterised in that the grid knot
Structure is planar insulated gate structure, and the lower surface of the insulation gate medium (7) is connected with the upper surface of barrier layer (3).
4. a kind of HEMT device with junction semiconductor layer according to claim 1, it is characterised in that the grid knot
Structure is groove insulated gate structure, and the bottom of the insulation gate medium (7) is located in barrier layer (3).
5. a kind of HEMT device with junction semiconductor layer according to claim 1, it is characterised in that the grid knot
Structure is groove insulated gate structure, and the lower surface of the insulation gate medium (7) is connected with the upper surface of cushion (2).
6. a kind of HEMT device with junction semiconductor layer according to Claims 1 to 5 any one, its feature exists
In the rectifier structure (9) is that metal gate electrode (6) contacts to form Schottky Barrier Contact with p-type doped region (81).
7. a kind of HEMT device with junction semiconductor layer according to Claims 1 to 5 any one, its feature exists
In the upper surface of institute's p-type doped region (81) and grid structure junction is described whole doped with N-type semiconductor formation PN junction rectification
Flow structure (9) is the PN junction rectification with metal gate electrode (6) formation Ohmic contact.
8. a kind of HEMT device with junction semiconductor layer according to claim 5, it is characterised in that the insulating course
(11) it is physics insulating course or ion implanting insulating course.
9. a kind of HEMT device with junction semiconductor layer according to claim 6, it is characterised in that the insulating course
(11) it is physics insulating course or ion implanting insulating course.
10. according to a kind of HEMT device with junction semiconductor layer described in claim 8 or 9, it is characterised in that the insulation
The material that gate medium (7) is used is Al2O3；The material that junction semiconductor layer (8) is used for Si, SiC, GaN, AlN,
One or more of combinations in AlGaN, InGaN, InAlN；The cushion (2) and barrier layer (3) use material for GaN,
One or more of combinations in AlN, AlGaN, InGaN, InAlN；The material that the substrate (1) uses for sapphire, silicon,
One or more of combinations in SiC, AlN or GaN.
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| CN108231880A (en) * | 2017-12-22 | 2018-06-29 | 苏州闻颂智能科技有限公司 | A kind of enhanced GaN base HEMT device and preparation method thereof |
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