CN114464671B - Super junction MOSFET with improved gate capacitance characteristics - Google Patents

Super junction MOSFET with improved gate capacitance characteristics Download PDF

Info

Publication number
CN114464671B
CN114464671B CN202210370737.7A CN202210370737A CN114464671B CN 114464671 B CN114464671 B CN 114464671B CN 202210370737 A CN202210370737 A CN 202210370737A CN 114464671 B CN114464671 B CN 114464671B
Authority
CN
China
Prior art keywords
doped
semiconductor
region
medium
doping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210370737.7A
Other languages
Chinese (zh)
Other versions
CN114464671A (en
Inventor
杨国江
郭智
汪阳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangsu Changjing Technology Co ltd
Jiangsu Changjing Pulian Power Semiconductor Co ltd
Original Assignee
Jiangsu Changjing Technology Co ltd
Jiangsu Changjing Pulian Power Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjing Technology Co ltd, Jiangsu Changjing Pulian Power Semiconductor Co ltd filed Critical Jiangsu Changjing Technology Co ltd
Priority to CN202210370737.7A priority Critical patent/CN114464671B/en
Publication of CN114464671A publication Critical patent/CN114464671A/en
Application granted granted Critical
Publication of CN114464671B publication Critical patent/CN114464671B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

Abstract

A super junction MOSFET for improving gate capacitance characteristics comprises a source metal layer, a highly doped second-type conductivity semiconductor JFET region, a medium-low doped second-type conductivity semiconductor depletion region expansion layer, a medium-low doped second-type conductivity semiconductor column region, a medium-high doped second-type conductivity semiconductor depletion region compression layer, a highly doped second-type conductivity semiconductor drain region and a drain metal layer; on the basis of a super junction MOSFET device, a low-doped area is arranged at the position, close to the JFET, of the second-type conductive column area, a high-doped area is arranged at the position, close to the buffer layer, of the second-type conductive column area, and meanwhile, a higher-doped thin JFET area is arranged to guarantee the current capacity and the grid control capacity of the device. The invention alleviates the abrupt change phenomenon of the grid-drain capacitance along with the voltage change, improves the EMI characteristic of the super junction device and improves the reliability of the device while giving consideration to the switching speed.

Description

Super junction MOSFET with improved gate capacitance characteristics
Technical Field
The invention belongs to the technical field of semiconductor devices, relates to a super junction field effect transistor, and provides a super junction MOSFET for improving the characteristics of gate capacitance.
Background
The super-junction MOSFET adopts the alternately arranged P/N columns to replace a single-conductivity-type drift region of the traditional VDMOS, improves the compromise relation between the on-resistance and the breakdown voltage, breaks through the limitation of silicon, has the characteristics of low power loss, high switching state conversion speed and the like, becomes a novel power device conforming to the development trend of carbon neutralization and has very wide application prospect. The super junction MOSFET can be widely applied to systems such as servo/telecommunication, charging piles, adapters, lighting, smart meters, LCD televisions and the like, and replaces a traditional MOSFET switch in an SMPS topology, so that the system can obtain higher efficiency and lower power consumption.
As a power switching tube in a switching power supply, the nonlinearity characteristic of the parasitic capacitance of the super junction MOSFET device seriously affects the switching characteristics. On one hand, the current passing through related components during the switching process can generate large peak interference and resonance noise, and the overshoot and oscillation of the current and the voltage can generate EMI conduction or radiation noise, and the EMI conduction or radiation noise can be mixedThe system enters a power grid or influences the electromagnetic environment of the system, so that the work of the system and other electromagnetic sensitive devices is influenced, and the reliability of the system is reduced; on the other hand, the high voltage and current which exist in the transient state of the switch simultaneously bring dynamic loss and reduce the working efficiency of the system. And the parasitic capacitance characteristics are crucial to the turn-on and turn-off processes of the power super-junction MOSFET. In order to increase the switching speed of the device to reduce dynamic loss, the super junction needs to be reduced to reduce the gate-drain capacitance C of the MOSFETGD(ii) a However, the gate-drain capacitance CGDToo little will make the switch dv/dt too large, which tends to increase the current and voltage overshoot and oscillation amplitude, making the device EMI noisy and even burning the device.
Disclosure of Invention
The invention aims to solve the problems that: aiming at the problem of parasitic capacitance of the existing super-junction MOSFET device, the gate capacitance characteristic of the super-junction MOSFET is improved, the super-junction MOSFET device with the improved gate capacitance characteristic is provided, the switching characteristic is considered, meanwhile, the EMI noise characteristic of the super-junction device is improved, and the reliability of the device and an application system is improved.
The technical scheme of the invention is as follows: a super-junction MOSFET for improving gate capacitance characteristics sequentially comprises a source metal layer, a middle-high doped second conductivity type semiconductor JFET region, a middle-low doped second conductivity type semiconductor depletion region expansion layer, a middle-low doped second conductivity type semiconductor column region, a middle-high doped second conductivity type semiconductor depletion region compression layer, a doped second conductivity type semiconductor drain region and a drain metal layer from top to bottom;
a polycrystalline silicon gate electrode is arranged in a gate insulating oxide layer on the upper surface of the middle-high doped second type conductivity semiconductor JFET region, the left side and the right side of the middle-high doped second type conductivity semiconductor JFET region are high-doped first type conductivity semiconductor body regions, and a heavily doped first type conductivity semiconductor ohmic contact region and a heavily doped second type conductivity semiconductor source region are arranged on the upper surface in the high-doped first type conductivity semiconductor body regions; the polycrystalline silicon gate electrode and the high-doped first-type conductivity semiconductor body area are isolated, and the polycrystalline silicon gate electrode and the high-doped second-type conductivity semiconductor JFET area are isolated through a gate insulating oxide layer; the polycrystalline silicon gate electrode is isolated from the source metal layer through a gate insulating oxide layer; a highly doped first-type conductivity semiconductor body region is arranged between the heavily doped second-type conductivity semiconductor source region and the moderately doped second-type conductivity semiconductor JFET region; the upper surface of the heavily doped second conduction type semiconductor source region is in contact with the source electrode metal layer and the grid electrode insulating oxide layer; the upper part of the heavily doped first conduction type semiconductor ohmic contact region is in contact with the source electrode metal layer; the medium-doped first-type conductivity type semiconductor column is positioned between the semiconductor columns of the medium-doped second-type conductivity type semiconductor column region, and the medium-doped first-type conductivity type semiconductor column is vertically and respectively connected with the high-doped first-type conductivity type semiconductor body region and the high-doped second-type conductivity type semiconductor drain region;
the medium-low doped second conductivity type semiconductor depletion region expansion layer is positioned below the medium-high doped second conductivity type semiconductor JFET region and is connected with the medium-low doped second conductivity type semiconductor column region; the compression layer of the depletion region of the highly doped second conductivity type semiconductor is positioned above the drain region of the highly doped second conductivity type semiconductor and is connected with the pillar region of the moderately doped second conductivity type semiconductor,
the heavy doping, the high doping, the medium doping and the medium-low doping refer to the impurity concentration of semiconductor doping, and on the basis of the impurity concentration of the super-junction MOSFET semiconductor column, the heavy doping is greater than the high doping, the medium doping is greater than the medium doping, and the medium-low doping is greater than the medium doping.
Preferably, the material of the super junction MOSFET device is one of silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium semiconductor materials.
Preferably, the first conductivity type semiconductor is a P-type semiconductor, and the second conductivity type semiconductor is an N-type semiconductor; or the first type conductivity semiconductor is an N-type semiconductor and the second type conductivity semiconductor is a P-type semiconductor.
Preferably, the medium doping is doping with an impurity concentration level between 1e14cm-3 and 1e16cm-3, the medium-low doping impurity concentration and the medium doping impurity concentration are kept close to each other and are 1% to 90% of the medium doping impurity concentration, the medium-high doping impurity concentration and the medium doping impurity concentration are kept close to each other and are 2 to 10 times of the medium doping impurity concentration, the high doping is doping with an impurity concentration level 1 to 2 orders of magnitude higher than that of the medium doping, and the heavy doping is doping with an impurity concentration level 2 orders of magnitude higher than that of the medium doping.
Further, the thickness of the depletion region extension layer of the medium-low doped second conductivity type semiconductor is set to be LtA elementary charge of q and a semiconductor dielectric constant of
Figure 453991DEST_PATH_IMAGE001
Doping N under the grid0The pinch-off voltage of the super junction device is VpinA concentration N of a middle-low doped semiconductor of the second type conductivity is setlThe relationship of (1) is satisfied;
Figure 317298DEST_PATH_IMAGE002
the thickness L of the depletion region compression layer (11) of the medium and high doped second type conductivity semiconductorbThe relation with the half cell width W of the device satisfies the following conditions:
Figure 513662DEST_PATH_IMAGE003
。
the invention has the beneficial effects that: on the basis of a super junction MOSFET device, a low-doped region is arranged at the position, close to a JFET, of a substrate type column region, a high-doped region is arranged at the position, close to a buffer layer, the buffer layer is a high-doped second-type conductivity semiconductor drain region, and meanwhile, a higher-doped thin JFET region is arranged to guarantee the current capacity and the grid control capacity of the device. When the column depletion region is not pinched off, the depletion region of the second conduction type semiconductor below the gate is obviously expanded, and the barrier capacitance is smaller, so that lower gate-drain capacitance is obtained under low leakage voltage; when the column depletion region is pinched off, the second conductive type semiconductor depletion region above the buffer layer is compressed to prevent the column depletion region from being pinched off, so that the sudden drop of the distributed coupling capacitance forming the gate-drain capacitance is avoided, and the gate-drain capacitance under high drain voltage is higher than that of the conventional structure. The phenomenon that the gate-drain capacitance is steeply changed along with the voltage change is alleviated, the switching speed is considered, meanwhile, the EMI characteristic of the super junction device is improved, and the reliability of the device is improved.
Drawings
Fig. 1 is a schematic diagram of a conventional superjunction MOSFET device.
Fig. 2 is a schematic diagram of depletion region and capacitance of a conventional super junction MOSFET device when pinch-off does not occur at low drain-source voltage.
Fig. 3 is a schematic diagram of a depletion region of a conventional super junction MOSFET device when pinch-off occurs at a high drain-source voltage.
Fig. 4 is a schematic diagram of a super junction MOSFET device with improved gate capacitance according to the present invention.
Fig. 5 is a schematic diagram of a depletion region and a capacitance of a super junction MOSFET device with improved gate capacitance when no pinch-off occurs at a low drain-source voltage.
Fig. 6 is a schematic diagram of a depletion region and a capacitance of a super junction MOSFET device with improved gate capacitance when pinch-off occurs at a high drain-source voltage.
Fig. 7 is an approximate geometry of depletion lines versus cell size in a superjunction MOSFET device.
Fig. 8 is a comparison of the variation curve of the gate-drain capacitance of the super junction MOSFET device with improved gate capacitance according to the drain-source voltage proposed by the present invention with that of the conventional super junction MOSFET device.
In the drawings, wherein: the structure comprises a source metal layer 1, a polysilicon gate electrode 2, a gate insulating oxide layer 3, a second-type conductivity semiconductor source region 4, a heavily doped first-type conductivity semiconductor ohmic contact region 5, a medium-high doped second-type conductivity semiconductor JFET region 6, a medium-low doped second-type conductivity semiconductor depletion region expansion layer 7, a high-doped first-type conductivity semiconductor body region 8, a medium-doped second-type conductivity semiconductor column region 9, a medium-medium doped first-type conductivity semiconductor column 10, a medium-high doped second-type conductivity semiconductor depletion region compression layer 11, a high-doped second-type conductivity semiconductor drain region 12 and a drain metal layer 13.
Detailed Description
The present invention provides a super junction MOSFET with improved gate capacitance characteristics, and the embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As described in the background art, the switching characteristics are severely affected by the characteristic nonlinearity of the parasitic capacitance of the super-junction MOSFET device, the switching speed of the device is increased to reduce dynamic loss, and a low gate-to-drain capacitance CGD is required; however, too small gate-drain capacitance CGD may cause excessive switch dv/dt, which may easily increase current and voltage overshoot and oscillation amplitude, cause excessive EMI noise, and even cause burning of the device. In order to solve the contradiction between the switching speed and the EMI noise of the gate-drain capacitor, the change relation of the gate-drain capacitor along with the drain-source voltage needs to be changed, so that the CGD of the gate-drain capacitor under low drain-source voltage is smaller, the switching speed is ensured, the CGD of the gate-drain capacitor under high drain-source voltage is larger, the condition that the capacitor is steeply changed along with the change of the drain-source voltage is relieved, and the EMI noise is inhibited.
Conventional super junction MOSFET product As shown in FIG. 1, FIG. 2 shows the gate-drain capacitance C of conventional super junction MOSFET deviceGDWhich may be equivalent to a gate capacitance Cox is connected in series with a semiconductor-side capacitance formed by capacitances Ct and Cb. When the drain electrode is connected with the working potential and the gate-source electrode is respectively grounded, the top of the N-type semiconductor column and the gate electrode form longitudinal depletion, the depletion action forms a potential barrier capacitance Ct, the device area is A, the element charge is q, and the semiconductor dielectric constant is
Figure 656062DEST_PATH_IMAGE001
Doping N under the grid0The external drain-source voltage of the device is VDSThe capacitance satisfies:
Figure 231793DEST_PATH_IMAGE004
formula (1)
Referring to fig. 3, at the bottom of the moderately doped N-type semiconductor column, the depletion region is close to the drain region with high doping concentration, the depletion line is bent, and the longitudinal electric field near the depletion line is coupled with the gate electrode to form a capacitor CbThe coupling capacitor CbThe distributed capacitance can be formed by the width W of the half cell, the longitudinal charge distribution Q (x), and the electric field peak E at the top of the N-type semiconductor columntmAnd bottom electric field peak EbmExpressed as:
Figure 41617DEST_PATH_IMAGE005
formula (2)
As shown in FIG. 2, when the drain voltage is low, the alternately arranged PN semiconductor columns are laterally depleted, the formed depletion line is not pinched off, the capacitance at one side of the semiconductor in the gate-drain capacitance is mainly composed of a barrier capacitance Ct with a small width at the top of the N-type semiconductor column, and CbTo gate drain capacitance CGDThe contribution of (c) is negligible; as shown in FIG. 3, when the drain voltage is high, the depletion region pinches off, the barrier capacitance Ct disappears, and the gate-drain capacitance CGDCoupling capacitor C formed by N-type semiconductor column bottom and grid electrodebAnd (4) forming.
As shown in fig. 4, the super junction MOSFET device with improved gate capacitance characteristics according to the embodiment of the present invention includes: the transistor comprises a source metal layer 1, a highly doped second conductivity type semiconductor JFET region 6, a moderately doped second conductivity type semiconductor depletion region expansion layer 7, a moderately doped first conductivity type semiconductor column 10, a moderately doped second conductivity type semiconductor column region 9, a highly doped second conductivity type semiconductor depletion region compression layer 11, a highly doped second conductivity type semiconductor drain region 12 and a drain metal layer 13; a polycrystalline silicon gate electrode 2 is arranged in a gate insulating oxide layer 3 on the upper surface of a medium-high doped second type conductivity type semiconductor JFET region 6, high-doped first type conductivity type semiconductor body regions 8 are arranged on the left side and the right side of the medium-high doped second type conductivity type semiconductor JFET region 6, and a heavily doped first type conductivity type semiconductor ohmic contact region 5 and a heavily doped second type conductivity type semiconductor source region 4 are arranged on the upper surface in the highly doped first type conductivity type semiconductor body regions 8; the polycrystalline silicon gate electrode 2 and the highly doped first conductivity type semiconductor body region 8 and the polycrystalline silicon gate electrode 2 and the highly doped second conductivity type semiconductor JFET region 6 are isolated by the gate insulating oxide layer 3; the polycrystalline silicon gate electrode 2 is isolated from the source metal layer 1 through a gate insulating oxide layer 3; a highly doped first type conductivity semiconductor body region 8 is arranged between the heavily doped second type conductivity semiconductor source region 4 and the middle highly doped second type conductivity semiconductor JFET region 6; the upper surface of the heavily doped second conduction type semiconductor source region 4 is contacted with the source metal layer 1 and the grid insulation oxide layer 3; the upper part of the heavily doped first conduction type semiconductor ohmic contact region 5 is contacted with the source electrode metal layer 1; the medium-doped first conductivity type semiconductor column 10 is positioned between the semiconductor columns of the medium-doped second conductivity type semiconductor column region 9, and is respectively connected with the high-doped first conductivity type semiconductor body region 8 and the high-doped second conductivity type semiconductor drain region 12 from top to bottom; the middle-low doped second conductivity type semiconductor depletion region expansion layer 7 is positioned below the middle-high doped second conductivity type semiconductor JFET region 6 and is connected with the middle-low doped second conductivity type semiconductor column region 9; the middle-high doped second conductivity type semiconductor depletion region compression layer 11 is positioned above the middle-high doped second conductivity type semiconductor drain region 12 and is connected with the middle-high doped second conductivity type semiconductor column region 9. The heavy doping, the high doping, the medium doping and the medium-low doping refer to the impurity concentration of semiconductor doping, and on the basis of the impurity concentration of the super-junction MOSFET semiconductor column, the heavy doping is greater than the high doping, the medium doping is greater than the medium doping, and the medium-low doping is greater than the medium doping.
In the embodiment, the medium-low doped second type conductivity semiconductor depletion region expansion layer 7 is introduced below the medium-high doped second type conductivity semiconductor JFET region 6 above the medium-low doped second type conductivity semiconductor column region 9, and the medium-high doped second type conductivity semiconductor depletion region compression layer 11 is introduced at the bottom of the medium-high doped second type conductivity semiconductor column region 9. During the turn-on or turn-off of the device, the drain-source voltage changes from a high value to a low value or from a low value to a high value, and the depletion region shrinks or expands gradually according to a rule without considering the influence of the gate voltage.
Specifically, the invention arranges a highly doped thin JFET region to ensure the current capability and the grid control capability of the device; as shown in fig. 5, compared with fig. 2, when the device has a lower drain-source voltage and the depletion region of the laterally alternating semiconductor pillar region does not pinch off due to the arrangement of the low-doped depletion region extension layer 7 of the second conductivity type semiconductor near the JFET end of the second conductivity type semiconductor pillar region 9 of the present invention, as can be seen from formula (1), the depletion region of the second conductivity type semiconductor under the gate will be significantly extended in the longitudinal direction compared with the conventional structure, so as to obtain a lower gate-drain capacitance under a low leakage voltage; as shown in fig. 6, compared with fig. 3, the highly doped second conductivity type semiconductor depletion region compressive layer 11 is disposed near the buffer layer end, when the drain-source voltage increases to cause pinch-off of the column depletion region, the second conductivity type semiconductor depletion region above the buffer layer is significantly compressed, so as to prevent pinch-off of the column depletion region, and avoid forming a gate-drain capacitor C at this pointGDThe distributed coupling capacitance of the capacitor is suddenly reduced, and the formula (2) shows that the peak value of an electric field is more violent to change along with the drain voltage, so that the grid-drain capacitance under the high drain voltage is higher than that of a conventional structure. This alleviates the abrupt change of the gate-drain capacitance with the voltage change, as shown in fig. 7, the new structure of the invention has smaller gate-drain capacitance at low drain voltage, which improves the switching speed; the super-junction MOSFET has larger gate-drain capacitance under high drain-source voltage, and reduces dv/dt in the switching process, thereby reducing voltage and current overshoot, weakening oscillation, reducing EMI noise of the super-junction MOSFET, and improving the reliability of devices and application systems.
Further, as described above, the devices of the present invention have different doping concentrations therein, and the skilled person can select the impurity concentration based on the doping impurity concentration of the super junction MOSFET semiconductor pillar to be produced, and the present invention is preferably configured as follows: the medium doping is doping with an impurity concentration order of magnitude between 1e14cm-3 and 1e16cm-3, the medium and low doping impurity concentration keeps close order of magnitude to the medium doping impurity concentration and is 1% to 90% of the medium doping impurity concentration, the medium and high doping impurity concentration keeps close order of magnitude to the medium doping impurity concentration and is 2 to 10 times of the medium doping impurity concentration, the high doping is doping with an impurity concentration 1 to 2 orders of magnitude higher than the medium doping, and the heavy doping is doping with an impurity concentration order of magnitude higher than the medium doping by more than 2 orders of magnitude.
Further, as shown in fig. 4, in the present invention, the thickness L of the depletion region extension layer 7 of the low/medium doped second conductivity type semiconductor istShould not exceed the drain-source voltage to reach the pinch-off voltage VpinThe length of the depletion region where the Ct capacitance is located, the excess being ineffective to improve the gate capacitance, and therefore LtAnd the concentration N of the arranged middle-low doped second type conductivity semiconductorlThe relationship of (a) should be satisfied;
Figure 408882DEST_PATH_IMAGE002
formula (3)
The thickness L of the middle-high doped second conduction type semiconductor depletion region compression layer 11bShould not exceed the drain-source voltage to reach the pinch-off voltage VpinThe length of the bending region in which the longitudinal electric field coupled with the gate exists is represented by the approximate relationship between the length of the bending region and the half-cell width W, L, shown in FIG. 8bIt should satisfy:
Figure 507419DEST_PATH_IMAGE003
formula (4)
Ideally, in the specified range of the present invention, the larger the thickness of the low-doped second conductivity type semiconductor depletion region extension layer and the high-doped second conductivity type semiconductor depletion region compression layer is, the more obvious the improvement effect on the gate capacitance is; the thickness of the highly doped second-type conductivity semiconductor JFET region 6 is smaller than 1um, so that the breakdown of the device at the position is avoided while the control capability of the grid electrode is ensured.
In the invention, the middle-low doped second conductivity type semiconductor depletion region expanding layer 7, the middle-high doped second conductivity type semiconductor depletion region compressing layer 11, the middle-medium doped second conductivity type semiconductor column region 9, the middle-medium doped first conductivity type semiconductor column 10 and the epitaxial layer in which the super junction structure is located can be formed through multiple times of epitaxial processes, the super junction structure can be formed through ion implantation and multi-step epitaxy, and can also be formed through a method of firstly etching a groove and then filling the groove through epitaxy, but the invention is not limited to this, and any existing process for preparing the super junction structure can be applied to the embodiment.
In the invention, the first type conductivity semiconductor is a P-type semiconductor, and the second type conductivity semiconductor is an N-type semiconductor; or the first conduction type semiconductor is an N-type semiconductor, and the second conduction type semiconductor is a P-type semiconductor.
In summary, the super junction MOSFET device with improved gate capacitance characteristics is provided, a super junction structure is prepared by adopting a variable-doping epitaxial layer, a low-doping region is arranged near a JFET end in a second-type conductive column region, a high-doping region is arranged near a buffer layer end, and a higher-doping thin JFET region is arranged to ensure the current capability and the gate control capability of the device; when the column depletion region is pinched off, the depletion region of the second conductivity type semiconductor above the buffer layer is compressed to prevent the column depletion region from being pinched off, thereby avoiding the formation of a gate-drain capacitor CGDThe distributed coupling capacitance is suddenly reduced, so that the grid-drain capacitance under high drain voltage is higher than that of a conventional structure, the abrupt change phenomenon of the grid-drain capacitance along with the voltage change is alleviated, the switching speed is considered, the EMI (electro-magnetic interference) characteristic of a super-junction device is improved, and the reliability of the device is improved. Therefore, the invention effectively overcomes various defects in the existing super junction technology and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (5)

1. A super junction MOSFET for improving gate capacitance characteristics is characterized by sequentially comprising a source metal layer (1), a JFET (junction field effect transistor) region (6) of a middle-high doped second type conductivity semiconductor, an expansion layer (7) of a depletion region of a middle-low doped second type conductivity semiconductor, a column region (9) of a middle-high doped second type conductivity semiconductor, a compression layer (11) of a depletion region of a middle-high doped second type conductivity semiconductor, a drain region (12) of a high doped second type conductivity semiconductor and a drain metal layer (13) from top to bottom;
a polycrystalline silicon gate electrode (2) is arranged inside a gate insulating oxide layer (3) on the upper surface of a medium-high doped second type conductivity type semiconductor JFET region (6), high-doped first type conductivity type semiconductor body regions (8) are arranged on the left side and the right side of the medium-high doped second type conductivity type semiconductor JFET region (6), and a heavily doped first type conductivity type semiconductor ohmic contact region (5) and a heavily doped second type conductivity type semiconductor source region (4) are arranged on the upper surface inside the high-doped first type conductivity type semiconductor body regions (8); the polycrystalline silicon gate electrode (2) and the highly doped first-type conductivity semiconductor body region (8) and the polycrystalline silicon gate electrode (2) and the highly doped second-type conductivity semiconductor JFET region (6) are isolated by a gate insulating oxide layer (3); the polycrystalline silicon gate electrode (2) is isolated from the source metal layer (1) through a gate insulating oxide layer (3); a highly doped first-type conductivity semiconductor body region (8) is arranged between the heavily doped second-type conductivity semiconductor source region (4) and the middle highly doped second-type conductivity semiconductor JFET region (6); the upper surface of the heavily doped second conduction type semiconductor source region (4) is in contact with the source metal layer (1) and the grid insulation oxide layer (3); the upper part of the heavily doped first conduction type semiconductor ohmic contact region (5) is in contact with the source electrode metal layer (1); the medium-doped first-type conductivity type semiconductor column (10) is positioned between the semiconductor columns of the medium-doped second-type conductivity type semiconductor column region (9), and the medium-doped first-type conductivity type semiconductor column (10) is respectively connected with the high-doped first-type conductivity type semiconductor body region (8) and the high-doped second-type conductivity type semiconductor drain region (12) from top to bottom;
the medium and low doped second type conductivity semiconductor depletion region expansion layer (7) is positioned below the medium and high doped second type conductivity semiconductor JFET region (6) and is connected with the medium doped second type conductivity semiconductor column region (9); the middle-high doped second conductivity type semiconductor depletion region compression layer (11) is positioned above the middle-high doped second conductivity type semiconductor drain region (12) and is connected with the middle-high doped second conductivity type semiconductor column region (9);
the heavy doping, the high doping, the medium doping and the medium-low doping refer to the impurity concentration of semiconductor doping, and on the basis of the impurity concentration of the super-junction MOSFET semiconductor column, the heavy doping is greater than the high doping, the medium doping is greater than the medium doping, and the medium-low doping is greater than the medium doping.
2. The super-junction MOSFET of claim 1, wherein the super-junction MOSFET is made of a semiconductor material selected from the group consisting of silicon, silicon carbide, gallium arsenide, indium phosphide, and silicon germanium.
3. The super junction MOSFET of claim 1, wherein the first conductivity type semiconductor is a P-type semiconductor, and the second conductivity type semiconductor is an N-type semiconductor; or the first type conductivity semiconductor is an N-type semiconductor and the second type conductivity semiconductor is a P-type semiconductor.
4. The super-junction MOSFET of claim 1, wherein the medium doping is a doping having an impurity concentration of between about 1e14cm-3 and 1e16cm-3, the medium and low dopant impurity concentrations are maintained at a similar level to the medium dopant impurity concentration, between about 1% and 90% of the medium dopant impurity concentration, the medium and high dopant impurity concentrations are maintained at a similar level to the medium dopant impurity concentration, between about 2 and 10 times the medium dopant impurity concentration, the high doping is a doping having an impurity concentration 1 to 2 orders of magnitude higher than the medium doping, and the heavy doping is a doping having an impurity concentration 2 orders of magnitude higher than the medium doping.
5. A super junction MOSFET with improved gate capacitance characteristics as claimed in claim 1 or 4, wherein said medium-low doped second conductivity type semiconductor depletion region extension layer (7) is L in thicknesstA elementary charge of q and a semiconductor dielectric constant of
Figure 323930DEST_PATH_IMAGE001
The pinch-off voltage of the super junction device is VpinA concentration N of a middle-low doped semiconductor of the second type conductivity is setlSatisfies the following relationship:
Figure 958567DEST_PATH_IMAGE002
the thickness L of the middle-high doped second conduction type semiconductor depletion region compression layer (11)bThe relation with the half cell width W of the device satisfies the following conditions:
Figure 60515DEST_PATH_IMAGE003
。
CN202210370737.7A 2022-04-11 2022-04-11 Super junction MOSFET with improved gate capacitance characteristics Active CN114464671B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210370737.7A CN114464671B (en) 2022-04-11 2022-04-11 Super junction MOSFET with improved gate capacitance characteristics

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210370737.7A CN114464671B (en) 2022-04-11 2022-04-11 Super junction MOSFET with improved gate capacitance characteristics

Publications (2)

Publication Number Publication Date
CN114464671A CN114464671A (en) 2022-05-10
CN114464671B true CN114464671B (en) 2022-07-01

Family

ID=81418003

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210370737.7A Active CN114464671B (en) 2022-04-11 2022-04-11 Super junction MOSFET with improved gate capacitance characteristics

Country Status (1)

Country Link
CN (1) CN114464671B (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9530844B2 (en) * 2012-12-28 2016-12-27 Cree, Inc. Transistor structures having reduced electrical field at the gate oxide and methods for making same
CN107482061B (en) * 2016-06-08 2020-12-04 深圳尚阳通科技有限公司 Super junction device and manufacturing method thereof
CN108538918A (en) * 2018-04-27 2018-09-14 电子科技大学 A kind of depletion type super-junction MOSFET device and its manufacturing method
CN110416285A (en) * 2019-07-31 2019-11-05 电子科技大学 A kind of superjunction power DMOS device
CN113224164B (en) * 2021-04-21 2022-03-29 电子科技大学 Super junction MOS device
CN113990757B (en) * 2021-10-27 2024-03-26 电子科技大学 MOS device structure and manufacturing method

Also Published As

Publication number Publication date
CN114464671A (en) 2022-05-10

Similar Documents

Publication Publication Date Title
CN111524976B (en) Power MOS device with low grid charge and manufacturing method thereof
CN109920854A (en) MOSFET element
CN104183646A (en) SOI LDMOS device with extending gate structure
CN112382658B (en) Low gate charge device with stepped discrete shield trenches and method of making the same
CN112802906B (en) Separated gate planar MOSFET device with floating gate
CN112164722A (en) Shielded gate MOSFET device with uniformly doped channel and processing technology
CN104992978A (en) Radio frequency LDMOS transistor and manufacture method thereof
CN107564965B (en) Transverse double-diffusion MOS device
CN110828565B (en) Double-channel high-voltage-resistance gallium nitride field effect transistor with P-type buried layer
CN105244376A (en) Enhanced AlGaN/GaN high electron mobility transistor
CN112447822A (en) Semiconductor power device
CN212659542U (en) Semiconductor power device with buried conductive medium channel region split gate structure
CN112802903A (en) Groove gate VDMOS device with improved gate structure
CN114464671B (en) Super junction MOSFET with improved gate capacitance characteristics
CN108511527A (en) Vertical double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof with charge compensation block
CN107546274B (en) LDMOS device with step-shaped groove
CN216435910U (en) Terminal structure of shielded gate MOSFET device
CN106252404B (en) A kind of enhanced MIS HEMT device in longitudinal direction with high K dielectric slot
CN115332338A (en) Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof
CN114725206A (en) SiCVDMOSFET device based on low dielectric constant medium
KR101685572B1 (en) SiC MOSFET for decreasing electric field of bottom oxide and method for manufacturing thereof
CN111969040B (en) Super junction MOSFET
CN111599866A (en) Low-grid charge power MOSFET device with U-shaped separation grid and manufacturing method thereof
CN219513114U (en) 4H-SiC-based superjunction power field effect transistor element
CN212967713U (en) Shielding gate MOSFET device with uniformly doped channel

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant