CN112992895A - Preparation method of GaN-based switch integrated unit and GaN-based switch tube wafer structure - Google Patents

Preparation method of GaN-based switch integrated unit and GaN-based switch tube wafer structure Download PDF

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CN112992895A
CN112992895A CN202110111817.6A CN202110111817A CN112992895A CN 112992895 A CN112992895 A CN 112992895A CN 202110111817 A CN202110111817 A CN 202110111817A CN 112992895 A CN112992895 A CN 112992895A
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gan
well
device layer
based switch
substrate
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CN112992895B (en
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徐敏
张卫
王晨
徐赛生
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Fudan University
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Fudan University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention provides a preparation method of a GaN-based switch integrated unit and a wafer structure of a GaN-based switch tube, wherein the preparation method comprises the following steps: forming a plurality of N wells on the P-type substrate; sequentially extending a plurality of epitaxial layers on the P-type substrate; forming a device layer of each GaN-based switching tube based on the plurality of epitaxial layers; the device layer of the first GaN-based switching tube is formed on the N trap, and the device layer of the second GaN-based switching tube is formed on the P-type substrate outside the N trap; and respectively forming a first substrate connecting part and a second substrate connecting part on the device layer of the first GaN-based switching tube and the device layer of the second GaN-based switching tube. The invention takes the integration requirements of the high-side tube and the low-side tube into consideration, and the consistency of the substrate voltage changes of the high-side tube and the low-side tube into consideration.

Description

Preparation method of GaN-based switch integrated unit and GaN-based switch tube wafer structure
Technical Field
The invention relates to the field of semiconductors, in particular to a preparation method of a GaN-based switch integrated unit and a wafer structure of a GaN-based switch tube.
Background
Voltage variators (e.g. DC-DC transformers) are used in a very wide range of everyday applications. With the increasing use of big data, artificial intelligence, autopilot, and multi-user gaming systems, the market for DC-DC transformers is increasing, such as transformers that are smaller in size, portable, but at the same time higher in power and lower in energy consumption. The traditional power devices represented by Si-based MOSFETs and IGBTs have large device area, high energy consumption, low conversion speed and small bearing voltage, so that the device performance improvement speed can not meet the performance requirements of the rapidly-increased transformer.
The semiconductor material represented by GaN has the characteristics of large forbidden band width, high critical breakdown electric field intensity, high saturated electron drift velocity and the like, and is an ideal semiconductor material in high-voltage, high-frequency and high-power application occasions.
In a GaN-based switching device (specifically, a GaN-based MOSFET, that is, a GaN-based HEMT), a high-concentration two-dimensional electron gas is formed by using AlGaN and a GaN heterojunction, and the device has a small area, a large driving current, and a high conversion speed. In addition, as the structure of the structure is not provided with the source-drain PN junction, the reverse recovery energy consumption is avoided, and the overall energy efficiency is higher. Therefore, GaN-based HEMTs are an important development trend of future power devices.
In some application circuits (e.g., a voltage converter circuit), two field effect transistors (e.g., a high side transistor Q1 (upper tube) and a low side transistor Q2 (lower tube) in fig. 1) need to be connected in series in the device, taking fig. 1 as an example, the high side transistor Q1 and the low side transistor Q2 can be alternately turned on and off under the control of a first PWM signal and a second PWM signal, a drain of the high side transistor Q1 is a power supply Vdc, and a source of the high side transistor Q1 (i.e., at the illustrated SW node) can output a pulse voltage signal with a certain duty ratio, so as to output a voltage, for example, output a dc voltage Vout after being filtered by the filtering module 100.
The field effect transistor controls the opening and closing of a channel by modulating the voltage of a grid end, meanwhile, a drain end is normally electrified, and the voltage drop between a source electrode and a substrate is zero. For the high side tube, the source voltage signal is a pulse signal, and in order to ensure its normal switching, the substrate voltage must be made to follow the source voltage change, so that the voltage drop VSB between the source and the substrate is 0V. For the low side transistor, the substrate voltage is different from that of the high side transistor, and the source is grounded, so the substrate voltage is 0V, and the voltage drop VSB between the source and the substrate is also 0V. In this case, the substrate voltages of the high-side transistor and the low-side transistor are not uniform, and therefore, the high-side transistor and the low-side transistor cannot be easily integrated on the same substrate. Because the GaN-based HEMT conducts electricity by means of two-position electron gas formed by a heterojunction, the device structure of the GaN-based HEMT is a layer of epitaxial structure, and the on-chip integration of double tubes cannot be realized by means of the traditional Si-based device, so that most of the conventional modes adopt a discrete GaN-based switching tube to form the double-tube device.
On the other hand, monolithic integration of the switching tube is desired to be realized in the industry because the monolithic integration can reduce the device size, improve the energy efficiency and save the power consumption.
Therefore, in the prior art, the integration requirements of a high-side tube and a low-side tube of a GaN-based open device and the consistency of substrate voltage changes of the high-side tube and the low-side tube are difficult to be considered.
Disclosure of Invention
The invention provides a preparation method of a GaN-based switch integrated unit and a wafer structure of a GaN-based switch tube, which is used for meeting the integration requirements of a high-side tube and a low-side tube and the consistency of substrate voltage changes of the high-side tube and the low-side tube.
According to a first aspect of the present invention, there is provided a GaN-based switch integrated unit, comprising:
a P-type substrate;
an N well formed on the P-type substrate;
the device layer of the GaN-based switch integrated unit is epitaxially formed on the P-type substrate and comprises a device layer of a first GaN-based switch tube and a device layer of a second GaN-based switch tube; the device layer of the first GaN-based switching tube is formed on the N well; the device layer of the second GaN-based switching tube is formed on the P-type substrate outside the N well; an isolation layer is arranged between the device layer of the second GaN-based switching tube and the device layer of the first GaN-based switching tube;
the first substrate connecting part penetrates through the upper surface of the device layer of the first GaN-based switching tube to the surface of the N well and is electrically connected with the N well;
and the second substrate connecting part penetrates through the device layer of the second GaN-based switching tube.
Optionally, the first GaN-based switching tube is a high-side tube, and the second GaN-based switching tube is a low-side tube.
Optionally, the thickness of the N-well is in the interval range of 1 to 3 μm.
Optionally, the GaN-based switch integrated unit further includes: the second substrate connecting part penetrates through the upper surface of the device layer of the second GaN-based switching tube to the surface of the P-type substrate and is electrically connected with the P-type substrate.
Optionally, the thickness of the P-well is in the interval range of 1 to 5 μm. Optionally, the second substrate connection portion penetrates through the upper surface of the device layer of the second GaN-based switching tube to the surface of the P-type substrate, and is electrically connected to the P-type substrate.
Optionally, the GaN-based switch integrated unit further includes: the P-well is formed on the P-type substrate, the P-well is formed on the P-type substrate outside the N-well, the device layer of the second GaN-based switching tube is formed on the P-well, and the second substrate connecting portion penetrates through the upper surface of the device layer of the second GaN-based switching tube to the surface of the P-well and is electrically connected with the P-well.
Optionally, the thickness of the P-well is in the interval range of 1 to 3 μm.
Optionally, the device layer of the first GaN-based switching tube and the device layer of the second GaN-based switching tube each include an epitaxial layer of the GaN-based switching tube, and a source, a gate, and a drain disposed on the epitaxial layer; and isolation layers are arranged between the source electrode and the grid electrode and between the drain electrode and the grid electrode.
Optionally, the epitaxial layer in the device layer sequentially includes an epitaxial buffer layer, a GaN channel layer, and an AlGaN layer from bottom to top.
Optionally, the bottom of the source and the drain contact the surface of the AlGaN layer; or the bottom of the source electrode and the drain electrode is deep into the AlGaN layer; or the bottom of the source electrode and the drain electrode contacts the surface of the GaN channel layer.
Optionally, the source of the device layer of the first GaN-based switching tube is electrically connected to the first substrate connection part; the source electrode of the second GaN-based switching device layer is electrically connected to the second substrate connecting portion.
Optionally, the gate is made of P-type heavily doped GaN.
Optionally, the P-type substrate is a P-type silicon substrate.
Optionally, the P-well is formed on a (111) plane of the P-type silicon substrate.
According to a second aspect of the present invention, there is provided a method for fabricating a wafer structure of a GaN-based switching tube, comprising:
providing a P-type substrate;
forming a plurality of N wells on the P-type substrate;
sequentially extending a plurality of epitaxial layers on the P-type substrate;
forming a device layer of each GaN-based switch tube based on the plurality of epitaxial layers, and isolating the device layers so as to isolate the device layers of adjacent GaN-based switch integrated units and the device layers of the second GaN-based switch tube and the first GaN-based switch tube of each GaN-based switch integrated unit; the device layer of the first GaN-based switching tube is formed on the N trap, and the device layer of the second GaN-based switching tube is formed on the P-type substrate outside the N trap;
forming a first substrate connecting part and a second substrate connecting part on the device layer of the first GaN-based switching tube and the device layer of the second GaN-based switching tube respectively, wherein the first substrate connecting part penetrates through the upper surface of the device layer of the first GaN-based switching tube to the surface of the N well and is electrically connected with the N well; the second substrate connecting part penetrates through the device layer of the second GaN-based switching tube.
Optionally, forming a plurality of N wells on the P-type substrate includes:
forming a plurality of P wells on the P-type substrate, and forming an N well in each P well.
Optionally, forming a plurality of P wells on the P-type substrate, and forming an N well in each P well, includes:
implanting first ions into a first region on the P-type substrate and activating the first region to form the P well, wherein the area of the first region is determined according to the area required by the first GaN-based switching tube;
and implanting second ions into a second region in the first region and activating to form the N well, wherein the thickness of the N well is smaller than that of the P well.
Optionally, the species of the first ion is any one of the following: boron and boron difluoride, wherein the second ion is any one of the following ions: arsenic and phosphorus.
Optionally, the implantation energies of the first ions and the second ions are both in an interval range of 100KeV to 2 MeV.
Optionally, forming a plurality of N wells on the P-type substrate includes:
and injecting third ions into a third area on the P-type substrate and activating to form the P well.
Optionally, before sequentially extending a plurality of epitaxial layers on the P-type substrate, the method further includes:
and implanting and activating fourth ions into a fourth region outside the third region on the P-type substrate to form the P well.
Optionally, the species of the fourth ion is any one of the following: boron, boron difluoride;
the implantation energy of the fourth ions is in the interval range of 100KeV to 2 MeV.
Optionally, the species of the third ion is any one of the following: arsenic, phosphorus;
the implantation energy of the third ions is in the interval range of 100KeV to 2 MeV.
Optionally, a device layer of each GaN-based switching tube is formed based on the plurality of epitaxial layers and isolated, and the method specifically includes:
manufacturing a grid electrode of each GaN-based switching tube on the epitaxial layers;
etching the epitaxial layers, and depositing an isolation material in the etched groove to form the isolation layer;
and manufacturing a source electrode and a drain electrode of each GaN-based switching tube on the rest epitaxial layer.
Optionally, a first substrate connection portion and a second substrate connection portion are respectively formed on the device layer of the first GaN-based switching tube and the device layer of the second GaN-based switching tube, and the method specifically includes:
for the first GaN-based switch tube, etching a corresponding isolation layer, a device layer and an N well in a first designated area, and filling metal in the etched groove to form a first substrate connecting part;
and for the second GaN-based switch tube, etching a corresponding isolation layer, a corresponding device layer and the P-type substrate or a P-well on the P-type substrate in a second designated area, and filling metal into the etched groove to form the second substrate connecting part.
According to a third aspect of the present invention, there is provided a circuit comprising the GaN-based switch integrated unit according to the first aspect and its alternatives.
Optionally, the circuit is a DC-DC conversion circuit.
Optionally, the GaN-based switch integrated unit is prepared by the preparation method related to the second aspect and the optional aspects thereof.
According to a fourth aspect of the present invention, there is provided an electronic device comprising the circuitry according to the third aspect and alternatives thereof.
In the method for preparing the GaN-based switch integrated unit and the GaN-based switch tube wafer structure provided by the invention, since the P-type silicon substrate forms an N-well, and the device layer of the first GaN-based switching tube (e.g., high-side tube) is located on the N-well, meanwhile, the substrate connection part can respectively lead out the substrate contact of the high-side tube and the low-side tube, the invention avoids or reduces the condition of inconsistent substrate voltage change under the condition of integrating the high-side tube and the low-side tube, the integration requirements of a high-side tube and a low-side tube and the consistency of the voltage changes of the substrates of the high-side tube and the low-side tube are considered, furthermore, energy consumption and speed loss caused by discrete devices are avoided, the fast and effective switching work of a high-side tube and a low-side tube in the GaN-based switch integrated unit is realized, when applied to a DC-DC conversion circuit, it can contribute to high energy efficiency and low power consumption of the DC-DC conversion circuit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of an application scenario of a GaN-based switch in the prior art;
FIG. 2a is a schematic diagram of a portion of a GaN-based switch integrated unit according to an embodiment of the invention;
FIG. 2b is a schematic diagram of a partial structure of a GaN-based switch integrated unit according to an embodiment of the invention;
FIG. 2c is a schematic diagram of a portion of a GaN-based switch integrated unit according to an embodiment of the invention;
FIG. 3a is a schematic diagram of a GaN-based switch integrated unit according to an embodiment of the invention;
FIG. 3b is a schematic structural diagram of a GaN-based switch integrated unit according to an embodiment of the invention;
FIG. 3c is a schematic diagram of a GaN-based switch integrated unit according to an embodiment of the invention;
FIG. 4 is a schematic flow chart illustrating a method for fabricating a wafer structure of a GaN-based switch transistor according to an embodiment of the invention;
FIG. 5 is a flowchart illustrating step S11 according to an embodiment of the present invention;
FIG. 6 is a flowchart illustrating step S12 according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a P-type silicon substrate in an embodiment of the invention;
FIG. 8 is a schematic structural diagram of an embodiment of the present invention after forming an N-well in a P-type silicon substrate;
FIG. 9 is a schematic diagram of the structure after forming a P-well in an N-well in accordance with an embodiment of the present invention;
FIG. 10 is a schematic structural diagram after forming a plurality of epitaxial layers in accordance with an embodiment of the present invention;
FIG. 11 is a schematic structural diagram illustrating a gate after fabrication in accordance with an embodiment of the present invention;
FIG. 12 is a schematic diagram of a structure after forming an isolation layer in accordance with an embodiment of the present invention;
FIG. 13 is a schematic diagram illustrating a structure after source and drain fabrication in accordance with an embodiment of the present invention;
FIG. 14 is a schematic structural view after a substrate connection is formed in an embodiment of the present invention;
fig. 15 is a fourth schematic structural diagram of a GaN-based switch integrated unit according to an embodiment of the invention.
Description of reference numerals:
100-a filtering module;
q1-high side tube;
q2-low side tube;
a 21-P type substrate;
22-N well;
23-P well;
24-a device layer;
241-a buffer layer;
242-GaN channel layer;
243-AlGaN layer;
244-gate;
245-source;
246-drain electrode;
247-p type GaN layer;
25-substrate connection;
26-isolating layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present disclosure does not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item presented before the word covers the element or item listed after the word and its equivalent, but does not exclude other elements or items.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Referring to fig. 2a, fig. 2b, fig. 2c and fig. 3a, fig. 3b and fig. 3c, an embodiment of the invention provides a GaN-based switch integrated unit, including:
a P-type substrate;
an N well 2 formed on the P-type substrate 21;
a device layer 24 of a GaN-based switch integrated unit epitaxially formed on the P-type substrate 21;
a first substrate connection portion (e.g., the right substrate connection portion 25 shown in fig. 2 and 3) penetrating the upper surface of the device layer 24 of the first GaN-based switching tube to the surface of the N-well 22 and electrically connected to the N-well 22;
a second substrate connection (e.g., the left substrate connection 25 shown in FIGS. 2a, 2b, 2c and 3a, 3b, 3 c) extending through the device layer 24 of the second GaN-based switching tube; specifically, in the example shown in fig. 2a and 2b and fig. 3a and 3b, the device layer 24 of the second GaN-based switch tube penetrates through the upper surface of the device layer 24 of the second GaN-based switch tube to the surface of the P-type substrate 21, and is electrically connected to the P-type substrate 21; in the example shown in fig. 2c and 3c, the device layer 24 of the second GaN-based switching tube is formed in the P-well 23, and the second substrate connection portion penetrates through the upper surface of the device layer 24 of the second GaN-based switching tube to the surface of the P-well 23 and is electrically connected to the P-well 23.
In one embodiment, referring to fig. 2a and fig. 3a, the GaN-based switch integrated unit further includes: and a P well 23 formed on the P-type substrate, wherein the N well 22 is formed in the P well 23. Wherein, the N well 22 is located in the P well 23, it can be understood that: the area covered by the N-well 22 along the surface of the substrate falls within the area covered by the P-well 23 along the surface of the substrate, and the thickness of the N-well 22 is smaller than that of the P-well 23. Meanwhile, the surfaces of the N well 22 and the P well 23 are flush with the surface of the P-type substrate 21.
In another embodiment, referring to fig. 2b and fig. 3b, the P-well 23 may not be formed in the GaN-based switch integrated unit.
In another embodiment, referring to fig. 2c and fig. 3c, the P-well 23 is formed on the P-type substrate 21 outside the N-well, and the device layer of the second GaN-based switching transistor is formed on the P-well 23.
Further, the N well and the P well may be understood as well structures formed by ion implantation in the manufacturing method referred to later.
Wherein the device layer 24 of the GaN-based switch integrated unit comprises a device layer of a first GaN-based switch tube (such as the device layer 24 on the right side shown in fig. 2a, 2b, 2c and 3a, 3b and 3 c) and a device layer of a second GaN-based switch tube (such as the device layer 24 on the left side shown in fig. 2a, 2b, 2c and 3a, 3b and 3 c); the device layer of the first GaN-based switching tube is formed on the N-well 22, and specifically, in the examples of fig. 2a and 3a, the device layer of the first GaN-based switching tube is formed on the N-well 22 in the P-well 23, and in the examples of fig. 2b, 2c, 3b, and 3c, the device layer of the first GaN-based switching tube is formed on the single N-well 22;
the device layer of the second GaN-based switching tube is formed on the P-type substrate 21 or the P-type substrate 21, specifically, in the examples of fig. 2a, 2b and 3a, 3b, the device layer of the second GaN-based switching tube is formed on the P-type substrate 21 outside the N-well 22 (and outside the P-well if having the P-well), and in the examples of fig. 2c and 3c, the device layer of the second GaN-based switching tube is formed outside the N-well 22 and on the P-well 23;
an isolation layer is arranged between the device layer of the second GaN-based switching tube and the device layer of the first GaN-based switching tube. The first GaN-based switching tube may be a high-side tube and the second GaN-based switching tube may be a low-side tube.
By way of the through-substrate connection 25, the substrate can be connected to the respective source via the substrate connection 25 after a corresponding design, namely: the source electrode of the device layer of the first GaN-based switching tube is electrically connected to the first substrate connecting part; the source electrode of the second GaN-based switching device layer is electrically connected to the second substrate connection portion, so that a voltage drop of 0V is formed between the source electrode and the substrate.
In the above solution, in the method for manufacturing a wafer structure of a GaN-based switch integrated unit and a GaN-based switch tube provided by the present invention, since the P-type silicon substrate forms an N well, and the device layer of the first GaN-based switch tube (e.g., the high-side tube) is located in the N well, and at the same time, the substrate contacts of the high-side tube and the low-side tube can be respectively led out through the substrate connection portion, the present invention avoids or reduces the situation of inconsistent substrate voltage changes in the case of integrating the high-side tube and the low-side tube, considers the integration requirements of the high-side tube and the low-side tube, and the consistency of the substrate voltage changes of the high-side tube and the low-side tube, thereby avoiding energy consumption and speed loss caused by discrete devices.
In one embodiment, if a P-well and an N-well are formed simultaneously and the N-well is in the P-well (for example, as shown in fig. 2a and 3 a), then: the thickness of the P well is in the interval range of 1-5 μm, and the thickness of the N well is in the interval range of 1-3 μm.
In another embodiment, if only N-well is formed and P-well is not formed (for example, as shown in fig. 2b and 3 b), then: the thickness of the N-well is in the interval range of 1 to 3 μm.
In one embodiment, if a P-well and an N-well are formed simultaneously and the N-well and the P-well are independent from each other (for example, as shown in fig. 2c and 3 c), then: the thickness of the P well is in the interval range of 1-3 μm, and the thickness of the N well is in the interval range of 1-3 μm.
The size of the N-well and the P-well is not limited to the above examples, and the size of the N-well and the P-well can be changed according to the specific structure and the requirement.
In one embodiment, the device layer 24 includes an epitaxial layer (i.e., the device layer of the first GaN-based switch tube and the device layer of the second GaN-based switch tube each include) and a gate electrode 244, a source electrode 245, and a drain electrode 246 disposed on the epitaxial layer; specifically, the gate 244, the source 245, and the drain 246 are disposed on the side of the corresponding epitaxial layer facing away from the P-type substrate (i.e., the upper side shown in fig. 2a, 2b, 2c, 3a, 3b, and 3 c); isolation layers 26 are disposed between the device layers, between the source 245, the gate 244, and the drain 246, and specifically, isolation layers 26 are disposed between the source 245 and the gate 244 and between the drain 246 and the gate 244.
In the embodiments shown in fig. 3a, 3b and 3c, the epitaxial layer in the device layer may include a buffer layer 241, a GaN channel layer 242, and an AlGaN layer 243, each of which may be understood as an epitaxial layer, and the buffer layer 241, the GaN channel layer 242, and the AlGaN layer 243 are sequentially disposed in a direction from bottom to top as shown in the figures.
The source 245, drain 246, and gate 244 referred to above may be provided on the AlGaN layer 243.
The buffer layer 241 may, for example, comprise an AlN buffer layer and/or an AlGaN buffer layer, although other material choices are not excluded.
Further, the AlN buffer layer may have only one AlN layer, or may have stacked AlN, TiN, and AlN layers to form a sandwich structure. By this buffer layer, diffusion of impurities in the well can be blocked. In addition, the buffer layer can be controlled within the range of 20-200nm, the temperature during growth can be controlled within the range of 500-1000 ℃, and diffusion of doping impurities is further inhibited.
The material can be selected at will according to the needs, and the specific size can be changed at will based on the selected material. Meanwhile, in an actual application process, the structure may not be limited to the above example.
In a specific scheme, the grid electrode is made of P-type heavily doped GaN.
In a specific scheme, the P-type substrate is a P-type silicon substrate. And further, in order to avoid substrate leakage, a good GaN layer is grown in a mode of lattice matching with the GaN, and the N well is formed on the (111) surface of the P-type silicon substrate.
Referring to fig. 4, an embodiment of the invention further provides a method for manufacturing a wafer structure of a GaN-based switch tube, which can be applied to manufacture the GaN-based switch tube integrated unit.
The preparation method comprises the following steps:
s11: providing a P-type substrate;
s12: forming a plurality of N wells on the P-type substrate;
s13: sequentially extending a plurality of epitaxial layers on the P-type substrate;
s14: forming a device layer of each GaN-based switch tube based on the plurality of epitaxial layers, and isolating the device layers so as to isolate the device layers of adjacent GaN-based switch integrated units, and the device layer of the second GaN-based switch tube of each GaN-based switch integrated unit from the device layer of the first GaN-based switch tube; the device layer of the first GaN-based switching tube is formed on the N trap, and the device layer of the second GaN-based switching tube is formed on the P-type substrate outside the N trap;
s15: forming a first substrate connecting part and a second substrate connecting part on the device layer of the first GaN-based switching tube and the device layer of the second GaN-based switching tube respectively, wherein the first substrate connecting part penetrates through the upper surface of the device layer of the first GaN-based switching tube to the surface of the N well and is electrically connected with the N well; the second substrate connecting part penetrates through the device layer of the second GaN-based switching tube.
In step S11, if an N-well needs to be formed in a P-well (as shown in fig. 2a and fig. 3 a), then:
step S11 may specifically include: forming a plurality of P wells on the P-type substrate, and forming an N well in each P well.
Referring to fig. 5, the method may specifically include:
s111: implanting first ions into the first region and activating to form the P well,
s112: and implanting second ions into the second region and activating to form the N well, wherein the thickness of the P well is smaller than that of the P well.
In the specific example of the process of step S111 above with reference to fig. 8 to 9, the P-well 23 may be formed by implanting and activating first ions on the P-type substrate 21. The area of its ion implantation (which may be understood as the area of the first region) may be determined according to the specific device design, i.e.: the area of the first region is determined according to the area required for the first GaN-based switching tube (e.g., high side tube). Further, the area is greater than or equal to 1umx1um, and the implanted first ions may be, for example, of any one of the following species: boron B, boron difluoride BF2, etc., the implantation energy may be in the range of 100KeV to 2MeV, the thickness of the P-well formed based on the species and implantation energy may be in the range of 1-5um, and the selected ion species, implantation energy, and thickness may vary based on practical circumstances, and are not limited to the above examples.
In the specific example of the above step S112, with reference to fig. 9 and fig. 10, the second ions may be implanted and activated in the P-well 23 to form the N-well 22, wherein the implantation area (i.e. the area of the second region) is smaller than that of the P-well 23, and the species of the implanted second ions may be any one of the following: arsenic As, phosphorus P, etc., the implantation energy may be in the range of 100KeV to 2MeV, the thickness of the N-well formed based on the species and implantation energy may be in the range of 1-3um, and the selected ion species, implantation energy, and thickness may vary based on practical circumstances, and are not limited to the above examples.
In another embodiment, if the N-well is formed directly on the P-type substrate (as shown in fig. 2b, 2c and fig. 3b, 3 c), then:
step S11 may specifically include: and injecting third ions into a third area on the P-type substrate and activating to form the N well.
The extent of the third region can be understood with reference to the extent of the second region, as described above. The species of the injected third ions may be, for example, any one of: arsenic As, phosphorus P, etc., the implantation energy may be in the range of 100KeV to 2MeV, the thickness of the N-well formed based on the species and implantation energy may be in the range of 1-3um, and the selected ion species, implantation energy, and thickness may vary based on the actual circumstances, but are not limited to the above examples.
Further, in some examples, the method also includes: and injecting fourth ions into a fourth area outside the third area on the P-type substrate and activating to form the P well.
The scope of the fourth region is to be understood with reference to the scope of the first region as described above. The species of the fourth ions to be implanted may be, for example, any one of: boron B, boron difluoride BF2, etc., the implantation energy may be in the range of 100KeV to 2MeV, the thickness of the N-well formed based on the species and implantation energy may be in the range of 1-3um, and the selected ion species, implantation energy, and thickness may vary based on the actual situation, and are not limited to the above examples.
In the above scheme, under the condition of integrating the high-side tube and the low-side tube, the condition of inconsistent substrate voltage changes is avoided or reduced, and the integration requirements of the high-side tube and the low-side tube and the consistency of the substrate voltage changes of the high-side tube and the low-side tube are considered.
In view of the above, it should be noted that the GaN-based HEMT is electrically conductive by using a two-bit electron gas formed by a heterojunction, so that the device structure is a layer-by-layer epitaxial structure, and the on-chip integration of a dual-transistor cannot be performed by using a well structure in a conventional silicon device. At present, most of researches adopt a discrete GaN-based switching tube, and even if the GaN-based switching tube is adopted, the overall performance index of the GaN-based switching tube is greatly improved compared with that of a silicon device. Some researches have been carried out on integrating a GaN-based double tube by using a simple bonding technology, but the controllability is poor, and other reliability problems are introduced; there have been some studies on isolation of a dual-transistor substrate using a silicon-on-insulator substrate, but the process is complicated and the cost is high.
Different from the schemes, the scheme of the embodiment of the invention provides a new idea, namely in the method, firstly, an N well (N-well) is partially processed in a high-side tube region of a substrate (in a partial scheme, the N well (N-well) and a P well (P-well) can be simultaneously processed), then, the epitaxy of a GaN HEMT device is performed, and simultaneously, substrate contacts of an upper tube and a lower tube are respectively led out through a substrate connecting part (sub tap), so that the problem that the voltage changes of the substrates of the high-side tube and the low-side tube are inconsistent is solved, and the monolithic integration of the GaN HEMT dual-tube is realized. Compared with the related schemes in other research directions at present, the scheme of the embodiment of the invention is based on a set of novel GaN-based switching device single-chip integration technology, solves the energy consumption and speed loss caused by the discrete devices in the GaN-based switching device, and realizes the quick and effective switching work of the high-side tube and the low-side tube in the GaN-based switching device.
On the basis, under the condition that the GaN-based switching device formed by the embodiment of the invention is adopted, the DC-DC transformation circuit can help to achieve the aims of high energy efficiency and low power consumption.
In steps S13 and S14, the process is understood with reference to the related art process of forming a device layer on a substrate, and any existing or improved process in the art can be applied to the embodiments of the present invention as an alternative.
Referring to fig. 10 and 11, referring to step S13, an MOCVD method or other epitaxial methods may be used to form each epitaxial layer according to device design requirements, where each epitaxial layer may be, for example, a buffer layer 241 (e.g., an AlGaN buffer layer), a GaN channel layer 242, an AlGaN layer 243, and a P-type GaN layer 247 that are sequentially stacked, and when each layer is epitaxial, the growth temperature may be controlled between 500C and 1000C to suppress diffusion of dopant impurities.
In one embodiment, referring to fig. 6, step S14 may include:
s141: manufacturing a grid electrode of each GaN-based switching tube on the epitaxial layers;
s142: etching the epitaxial layers, and depositing an isolation material in the etched groove to form the isolation layer;
s143: and manufacturing a source electrode and a drain electrode of each GaN-based switching tube on the rest epitaxial layer.
Referring to fig. 11, in step S141, a gate may be patterned and etched based on the pattern (e.g., etching the P-type GaN layer 247), and then a gate metal contact is made to form a corresponding gate.
Referring to fig. 12, in step S142, the isolation layer may be patterned, and etched (e.g., each epitaxial layer is etched) based on the pattern, and then an isolation material is deposited to form a corresponding isolation layer.
Referring to fig. 13, in step S143, a source and a drain may be patterned and metal contacts of the source and the drain may be made based on the pattern to form a corresponding source and a corresponding drain.
In one embodiment, referring to fig. 7, step S15 specifically includes:
s151: for the first GaN-based switch tube, etching a corresponding isolation layer, a device layer and an N well in a first designated area, and filling metal in the etched groove to form the first substrate connecting part;
s152: and for the second GaN-based switch tube, etching a corresponding isolation layer, a corresponding device layer and the P-type substrate or a P-well on the P-type substrate in a second designated area, and filling metal into the etched groove to form the second substrate connecting part.
The substrate connection portion region may be etched within the N well range, and etched to a position below the N well surface (the upper surface shown in the figure), for example, RIE (Reactive Ion Etching) may be used to etch the substrate connection portion region to a required thickness, and then, a metal Deposition process may be used to fill metal in the etched groove, where the metal Deposition process may be PVD (Physical Vapor Deposition) or other metal filling processes. Etching of the substrate joint region within the P-well region can be accomplished with reference to similar processes.
Embodiments of the present invention also provide a circuit including a GaN-based switch integrated unit according to the above alternatives.
The circuit may be a DC-DC conversion circuit.
The embodiment of the invention also provides an electronic device and a circuit related to the alternative scheme.
In summary, in the method for manufacturing the wafer structure of the GaN-based switch integrated unit and the GaN-based switch tube provided by the invention, since the P-type silicon substrate forms an N-well, and the device layer of the first GaN-based switching tube (e.g., high-side tube) is located on the N-well, meanwhile, the substrate connection part can respectively lead out the substrate contact of the high-side tube and the low-side tube, the invention avoids or lightens the condition of inconsistent substrate voltage change under the condition of integrating the high-side tube and the low-side tube, the integration requirements of the high-side tube and the low-side tube and the consistency of the substrate voltage changes of the high-side tube and the low-side tube are considered, furthermore, energy consumption and speed loss caused by discrete devices are avoided, the fast and effective switching work of a high-side tube and a low-side tube in the GaN-based switch integrated unit is realized, when applied to a DC-DC conversion circuit, it can contribute to high energy efficiency and low power consumption of the DC-DC conversion circuit.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (29)

1. A GaN-based switch integrated unit, comprising:
a P-type substrate;
an N well formed on the P-type substrate;
the device layer of the GaN-based switch integrated unit is epitaxially formed on the P-type substrate and comprises a device layer of a first GaN-based switch tube and a device layer of a second GaN-based switch tube; the device layer of the first GaN-based switching tube is formed on the N well; the device layer of the second GaN-based switching tube is formed on the P-type substrate outside the N well; an isolation layer is arranged between the device layer of the second GaN-based switching tube and the device layer of the first GaN-based switching tube;
the first substrate connecting part penetrates through the upper surface of the device layer of the first GaN-based switching tube to the surface of the N well and is electrically connected with the N well;
and the second substrate connecting part penetrates through the device layer of the second GaN-based switching tube.
2. The GaN-based switch integrated unit of claim 1, wherein the first GaN-based switch transistor is a high-side transistor and the second GaN-based switch transistor is a low-side transistor.
3. The GaN-based switch integrated unit of claim 1, wherein the thickness of the N-well is in the interval range of 1 to 3 μ ι η.
4. The GaN-based switch integrated unit of any of claims 1 to 3, further comprising: and the second substrate connecting part penetrates through the upper surface of the device layer of the second GaN-based switching tube to the surface of the P-type substrate and is electrically connected with the P-type substrate.
5. The GaN-based switch integrated unit of claim 4, wherein the thickness of the P-well is in the interval range of 1 to 5 μm.
6. The GaN-based switch integrated unit according to any of claims 1 to 3, wherein the second substrate connection portion penetrates through an upper surface of the device layer of the second GaN-based switch tube to the surface of the P-type substrate and is electrically connected to the P-type substrate.
7. The GaN-based switch integrated unit of any of claims 1 to 3, further comprising: the P-well is formed on the P-type substrate, the P-well is formed on the P-type substrate outside the N-well, the device layer of the second GaN-based switching tube is formed on the P-well, and the second substrate connecting portion penetrates through the upper surface of the device layer of the second GaN-based switching tube to the surface of the P-well and is electrically connected with the P-well.
8. The GaN-based switch integrated unit of claim 7, wherein the thickness of the P-well is in the interval range of 1 to 3 μm.
9. The GaN-based switch integrated unit according to any of claims 1 to 3, wherein the device layer of the first GaN-based switch tube and the device layer of the second GaN-based switch tube each comprise an epitaxial layer of the GaN-based switch tube and a source, a gate and a drain disposed on the epitaxial layer; and isolation layers are arranged between the source electrode and the grid electrode and between the drain electrode and the grid electrode.
10. The GaN-based switch integrated unit of claim 9, wherein the epitaxial layer in the device layer comprises an epitaxial buffer layer, a GaN channel layer, and an AlGaN layer in sequence from bottom to top.
11. The GaN-based switch integrated unit of claim 10, wherein the bottom of the source and the drain are in contact with the surface of the AlGaN layer; or the bottom of the source electrode and the drain electrode extends into the AlGaN layer; or the bottom of the source electrode and the drain electrode contacts the surface of the GaN channel layer.
12. The GaN-based switch integrated unit of claim 9, wherein the source of the device layer of the first GaN-based switch tube is electrically connected to the first substrate connection portion; the source electrode of the second GaN-based switching device layer is electrically connected to the second substrate connecting portion.
13. The GaN-based switch integrated unit of claim 9, wherein the gate is made of P-type heavily doped GaN.
14. The GaN-based switch integrated unit of any of claims 1 to 3, wherein the P-type substrate is a P-type silicon substrate.
15. The GaN-based switch integrated unit of claim 14, wherein the P-well is formed on a (111) plane of the P-type silicon substrate.
16. A preparation method of a wafer structure of a GaN-based switch tube is characterized by comprising the following steps:
providing a P-type substrate;
forming a plurality of N wells on the P-type substrate;
sequentially extending a plurality of epitaxial layers on the P-type substrate;
forming a device layer of each GaN-based switch tube based on the plurality of epitaxial layers, and isolating the device layers so as to isolate the device layers of adjacent GaN-based switch integrated units, and the device layer of the second GaN-based switch tube of each GaN-based switch integrated unit from the device layer of the first GaN-based switch tube; the device layer of the first GaN-based switching tube is formed on the N trap, and the device layer of the second GaN-based switching tube is formed on the P-type substrate outside the N trap;
forming a first substrate connecting part and a second substrate connecting part on the device layer of the first GaN-based switching tube and the device layer of the second GaN-based switching tube respectively, wherein the first substrate connecting part penetrates through the upper surface of the device layer of the first GaN-based switching tube to the surface of the N well and is electrically connected with the N well; the second substrate connecting part penetrates through the device layer of the second GaN-based switching tube.
17. The method of claim 16, wherein forming N-wells on the P-type substrate comprises:
forming a plurality of P wells on the P-type substrate, and forming an N well in each P well.
18. The method of claim 17,
forming a plurality of P wells on the P-type substrate, and forming an N well in each P well, comprising:
implanting first ions into a first region on the P-type substrate and activating the first region to form the P well, wherein the area of the first region is determined according to the area required by the first GaN-based switching tube;
and implanting second ions into a second region in the first region and activating to form the N well, wherein the thickness of the N well is smaller than that of the P well.
19. The method according to claim 18, wherein the species of the first ion is any one of: boron and boron difluoride, wherein the second ion is any one of the following ions: arsenic, phosphorus;
the implantation energy of the first ions and the second ions is in the range of 100KeV to 2 MeV.
20. The method of claim 16, wherein forming N-wells on the P-type substrate comprises:
and injecting third ions into a third area on the P-type substrate and activating to form the N well.
21. The method of claim 20, further comprising, prior to sequentially epitaxially growing a plurality of epitaxial layers on the P-type substrate:
and injecting fourth ions into a fourth region outside the third region on the P-type substrate and activating to form the P well.
22. The method according to claim 21, wherein the species of the fourth ion is any one of: boron, boron difluoride;
the implantation energy of the fourth ions is in the interval range of 100KeV to 2 MeV.
23. The method according to claim 20, wherein the species of the third ion is any one of: arsenic, phosphorus;
the implantation energy of the third ions is in the interval range of 100KeV to 2 MeV.
24. The production method according to any one of claims 16 to 23,
forming a device layer of each GaN-based switching tube based on the plurality of epitaxial layers, and isolating, specifically comprising:
manufacturing a grid electrode of each GaN-based switching tube on the epitaxial layers;
etching the epitaxial layers, and depositing an isolation material in the etched groove to form the isolation layer;
and manufacturing a source electrode and a drain electrode of each GaN-based switching tube on the rest epitaxial layer.
25. The production method according to any one of claims 16 to 23,
forming a first substrate connecting part and a second substrate connecting part on the device layer of the first GaN-based switch tube and the device layer of the second GaN-based switch tube respectively, specifically comprising:
for the first GaN-based switch tube, etching a corresponding isolation layer, a device layer and an N well in a first designated area, and filling metal in the etched groove to form a first substrate connecting part;
and for the second GaN-based switch tube, etching a corresponding isolation layer, a corresponding device layer and the P-type substrate or a P-well on the P-type substrate in a second designated area, and filling metal into the etched groove to form the second substrate connecting part.
26. A circuit comprising the GaN-based switch integrated unit of any one of claims 1 to 15.
27. The circuit of claim 26, wherein the GaN-based switch integrated unit is fabricated by the fabrication method of claims 15 to 24.
28. The circuit of claim 27, wherein the circuit is a DC-DC converter circuit.
29. An electronic device comprising the circuit of any of claims 26 to 28.
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