CN115132726A - Structure and manufacturing method of fast recovery power device and electronic equipment - Google Patents
Structure and manufacturing method of fast recovery power device and electronic equipment Download PDFInfo
- Publication number
- CN115132726A CN115132726A CN202211072298.8A CN202211072298A CN115132726A CN 115132726 A CN115132726 A CN 115132726A CN 202211072298 A CN202211072298 A CN 202211072298A CN 115132726 A CN115132726 A CN 115132726A
- Authority
- CN
- China
- Prior art keywords
- type
- layer
- epitaxial layer
- arc
- type region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000011084 recovery Methods 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 52
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 35
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 35
- 230000005669 field effect Effects 0.000 claims description 29
- 235000012239 silicon dioxide Nutrition 0.000 claims description 26
- 239000000377 silicon dioxide Substances 0.000 claims description 26
- 238000005468 ion implantation Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 238000004364 calculation method Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 9
- 229910052796 boron Inorganic materials 0.000 description 7
- 238000002513 implantation Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000007740 vapor deposition Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 108091006146 Channels Proteins 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- -1 boron ions Chemical class 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Thyristors (AREA)
Abstract
A structure, a manufacturing method and electronic equipment of a fast recovery power device belong to the technical field of semiconductors, and comprise a P-type layer, an N-type epitaxial layer, an arc-shaped groove, a first P-type region and a second P-type region; the P-type layer is positioned on the upper surface of the N-type epitaxial layer; the arc-shaped groove is hollowed out of the P-type layer and is positioned on the upper surface of the N-type epitaxial layer; the first P-type area is positioned below the arc-shaped groove; the second P-type area is arranged below the side face of the arc-shaped groove and is positioned on the upper surface of the P-type area; the upper part of the side surface of the arc-shaped groove with the doping concentration of the second P-type region being greater than that of the first P-type region is connected with the N-type epitaxial layer; therefore, the reverse voltage withstanding capability of the fast recovery power device is improved and the anti-surge capability is improved while the forward starting voltage is increased.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a structure of a fast recovery power device, a manufacturing method of the fast recovery power device and electronic equipment.
Background
The fast recovery diode is generally formed by epitaxy of a PIN structure, and under the application of a service life control technology of global carriers or local carriers, the service life of the carriers is reduced, so that the diode has the characteristic of fast recovery. The diode is usually used in parallel with an Insulated Gate Bipolar Transistor (IGBT), the turn-on loss of the IGBT is usually increased by the peak current generated in the reverse recovery process of the fast recovery diode, and the Gate voltage of the IGBT is affected by the low softness caused by poor control of the epitaxial buffer layer. Generally, the higher the forward turn-on voltage of a fast recovery diode using global carrier lifetime control, i.e., the lower the anode injection efficiency, the smaller the reverse peak current, the smaller the influence on the IGBT, but the loss of the fast recovery diode increases at this time.
Hybrid PIN/Schottky Diode (MPS), because of the integration of the Schottky structure and the PIN structure, the anode injection efficiency is reduced without increasing the forward turn-on voltage, and the conditions for manufacturing a fast recovery Diode with low forward turn-on voltage, low reverse peak current and high softness are provided, but since the Schottky junction has large leakage without good electric field shielding, in order to obtain a good electric field shielding effect, a high-concentration P junction needs to be prepared, the Schottky junction region is exhausted, and the anode injection efficiency is increased at the same time, so that it is difficult to prepare a high-voltage MPS fast recovery Diode.
Therefore, the related fast recovery power device needs to prepare a high-concentration P junction to exhaust a Schottky junction region and improve the anode injection efficiency, so that the low forward starting voltage cannot be kept, and the fast recovery power device is resistant to reverse high voltage and has strong anti-surge capability.
Disclosure of Invention
The application aims to provide a structure of a fast recovery power device, a manufacturing method of the fast recovery power device and electronic equipment, and aims to solve the problems that a related fast recovery power device cannot resist reverse high voltage and has strong anti-surge capacity while keeping low forward starting voltage.
The embodiment of the application provides a structure of a fast recovery power device, which comprises:
a P-type layer and an N-type epitaxial layer; the P-type layer is positioned on the upper surface of the N-type epitaxial layer;
hollowing out the P-type layer and an arc-shaped groove located on the upper surface of the N-type epitaxial layer;
the first P-type region is positioned below the arc-shaped groove;
the second P-type region is arranged below the side face of the arc-shaped groove and is positioned on the upper surface of the P-type region; the doping concentration of the second P-type region is greater than that of the first P-type region;
and the upper part of the side surface of the arc-shaped groove is connected with the N-type epitaxial layer.
In one embodiment, the method further comprises the following steps:
and the third P-type region is positioned on the lower surface of the arc-shaped groove and is arranged on the upper surface of the first P-type region.
In one embodiment, the N-type epitaxial layer is a low-doped N-type epitaxial layer, the first P-type region is a low-doped first P-type region, the second P-type region is a high-doped second P-type region, the third P-type region is a high-doped third P-type region, and the P-type layer is a low-doped P-type layer.
In one embodiment, the arc-shaped trench is filled with metal, a first metal layer is arranged on the upper surface of the P-type layer, and a second metal layer is arranged on the lower surface of the N-type epitaxial layer.
In one embodiment, the fast recovery power device comprises a fast recovery diode and a junction field effect transistor; the first P-type region and the second P-type region are anodes of the fast recovery diode, the N-type epitaxial layer below the first P-type region is a cathode of the fast recovery diode, the P-type layer and the second P-type region are gates of the junction field effect transistor, the N-type epitaxial layer above the side surface of the arc-shaped groove is a drain electrode of the junction field effect transistor, and the N-type epitaxial layer below the first P-type region is a source electrode of the junction field effect transistor; and the grid electrode of the junction field effect transistor and the drain electrode of the junction field effect transistor are connected in common.
The embodiment of the present application further provides a manufacturing method of a fast recovery power device, where the manufacturing method includes:
forming an N-type epitaxial layer;
forming a hard mask on the upper surface of the N-type epitaxial layer;
wet etching the N-type epitaxial layer to form a convex groove;
ion implantation is carried out on the lower surface of the convex groove to form a first P-type area;
ion implantation is carried out below the side face of the convex groove to form a second P-type area;
removing the hard mask plate to form an arc-shaped groove;
forming a side wall mask on the side surface of the arc-shaped groove;
and implanting ions on the upper surface of the N-type epitaxial layer to form a P-type layer.
In one embodiment, the ion implantation on the upper surface of the N-type epitaxial layer to form a P-type layer specifically includes:
ion implantation is carried out on the upper surface of the N-type epitaxial layer and the lower surface of the arc-shaped groove to form a P-type layer and a third P-type area; the P-type layer is positioned on the upper surface of the N-type epitaxial layer, and the third P-type region is positioned on the lower surface of the arc-shaped groove and is arranged on the upper surface of the first P-type region.
In one embodiment, the ion implantation under the side surface of the convex trench to form the second P-type region specifically includes:
performing ion implantation at a preset angle to form a highly doped second P-type region below the side face of the convex groove; wherein the preset angle is obtained by the following calculation formula: α = arctan (a/(B + C)); a is the width of the convex groove, B is the thickness of the hard mask, C is the depth of the convex groove, and alpha is the preset angle.
In one embodiment, the forming of the sidewall mask on the side surface of the arc-shaped trench specifically includes:
forming a silicon dioxide mask layer on the upper surface of the N-type epitaxial layer and the upper surface of the arc-shaped groove;
and removing the upper surface of the silicon dioxide mask layer and reserving the silicon dioxide mask layer on the side surface of the arc-shaped groove to form a side wall mask.
In one embodiment, after the ion implantation on the upper surface of the N-type epitaxial layer to form a P-type layer, the method further includes:
and filling metal in the arc-shaped groove, forming a first metal layer on the upper surface of the P-type layer, and forming a second metal layer on the lower surface of the N-type epitaxial layer.
In one embodiment, the forming a hard mask on the upper surface of the N-type epitaxial layer includes:
forming a first silicon nitride layer on the upper surface of the N-type epitaxial layer;
forming a silicon dioxide layer on the upper surface of the first silicon nitride layer;
forming a second silicon nitride layer on the upper surface of the silicon dioxide layer;
removing part of the first silicon nitride layer, part of the silicon dioxide layer and part of the second silicon nitride layer to form a columnar trench;
forming a third silicon nitride layer on the upper surface of the second silicon nitride layer and the lower surface of the columnar groove;
and etching back the third silicon nitride layer to expose the N-type epitaxial layer on the lower surface of the columnar trench.
The embodiment of the application also provides electronic equipment, and the electronic equipment comprises the structure of the fast recovery power device.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the first P-type region and the second P-type region form the anode of the fast recovery diode, the N-type epitaxial layer below the first P-type region forms the cathode of the fast recovery diode, the P-type layer and the second P-type region form the gate of the junction field effect transistor, the N-type epitaxial layer above the side surface of the arc-shaped groove forms the drain of the junction field effect transistor, and the N-type epitaxial layer below the first P-type region forms the source of the junction field effect transistor; on one hand, the arc-shaped groove enables the first P-type region with low doping concentration to have a larger area, the second P-type region with high doping concentration reduces forward starting voltage, the first P-type region with large area and low doping concentration improves anti-surge capability, and therefore the anti-surge capability is improved while the forward starting voltage is increased; on the other hand, when the fast recovery power device is forward biased, the PN junction in the junction field effect transistor is forward biased, the channel is widened, the on-resistance is reduced, the forward starting voltage is further reduced, and when the fast recovery power device is reverse biased, the PN junction in the junction field effect transistor is reverse biased, the channel is narrowed, the on-resistance is increased, and the reverse voltage withstanding capability of the fast recovery power device is improved.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts.
Fig. 1 is a schematic structural diagram of a structure of a fast recovery power device according to an embodiment of the present application;
fig. 2 is a schematic diagram illustrating an N-type epitaxial layer formed in a method for manufacturing a fast recovery power device according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram illustrating a hard mask formed in a manufacturing method of a fast recovery power device according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram illustrating the formation of a convex trench in the method for manufacturing a fast recovery power device according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram illustrating the formation of a first P-type region in the method for manufacturing a fast recovery power device according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram illustrating the formation of a second P-type region in the method for manufacturing a fast recovery power device according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram illustrating a method for removing a hard mask in a manufacturing method of a fast recovery power device according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram illustrating the formation of a sidewall mask in the method for manufacturing a fast recovery power device according to an embodiment of the present disclosure;
fig. 9 is a schematic diagram illustrating a P-type layer formed in a method for manufacturing a fast recovery power device according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Fig. 1 illustrates a module structure of a fast recovery power device provided in an embodiment of the present invention, and for convenience of description, only the portions related to the embodiment of the present invention are illustrated, and the details are as follows:
the structure of the fast recovery power device comprises a P type layer 11, an N type epitaxial layer 12, an arc-shaped groove 13, a first P type region 14 and a second P type region 15.
The P-type layer 11 is positioned on the upper surface of the N-type epitaxial layer 12; the arc-shaped groove 13 is hollowed out of the P-type layer 11 and is positioned on the upper surface of the N-type epitaxial layer 12; the first P-type region 14 is located below the arc-shaped groove 13; the second P-type region 15 is arranged below the side surface of the arc-shaped groove 13 and is positioned on the upper surface of the P-type region; the side surface of the arc-shaped groove 13 with the doping concentration of the second P type region 15 being greater than that of the first P type region 14 is connected with the N type epitaxial layer 12.
By way of example and not limitation, a third P-type region 16 is located at the lower surface of the arc-shaped trench 13 and disposed at the upper surface of the first P-type region 14. Wherein the doping concentration of the third P-type region 16 is greater than the doping concentration of the first P-type region 14.
It is worth emphasizing that the N-type epitaxial layer 12 is a low-doped N-type epitaxial layer 12, the first P-type region 14 is a low-doped first P-type region 14, the second P-type region 15 is a high-doped second P-type region 15, the third P-type region 16 is a high-doped third P-type region 16, and the P-type layer 11 is a low-doped P-type layer 11.
Since the first P-type region 14 with low doping concentration is located below the arc-shaped trench 13, the first P-type region 14 with low doping concentration has a larger area, and the first P-type region 14 with low doping concentration reduces reverse recovery current, so that the anti-surge capability is improved and the reverse recovery current is reduced.
In specific implementation, the fast recovery power device comprises a fast recovery diode and a junction field effect transistor; the first P type region 14 and the second P type region 15 are anodes of fast recovery diodes, the N type epitaxial layer 12 below the first P type region 14 is a cathode of the fast recovery diode, the P type layer 11 and the second P type region 15 are grids of a junction field effect transistor, the N type epitaxial layer 12 above the side face of the arc-shaped groove 13 is a drain electrode of the junction field effect transistor, and the N type epitaxial layer 12 below the first P type region 14 is a source electrode of the junction field effect transistor; wherein, the grid of the junction field effect transistor and the drain electrode of the junction field effect transistor are connected in common. So that the fast recovery power device comprises a fast recovery diode and a junction field effect transistor connected in parallel.
The arc-shaped trench 13 is filled with metal, a first metal layer is disposed on the upper surface of the P-type layer 11, and a second metal layer is disposed on the lower surface of the N-type epitaxial layer 12.
Filling metal in the arc-shaped groove 13, and arranging a first metal layer on the upper surface of the P-type layer 11 to serve as an anode electrode of the fast recovery power device; and forming a metal layer on the lower surface of the epitaxial layer to be used as a cathode electrode of the fast recovery power device.
Corresponding to an embodiment of a fast recovery power device, the invention also provides an embodiment of a manufacturing method of the fast recovery power device.
A method for manufacturing a fast recovery power device comprises steps 401 to 406.
In step 401, an N-type epitaxial layer 12 is formed, as shown in fig. 2.
In step 402, as shown in fig. 3, a hard mask 20 is formed on the upper surface of the N-type epitaxial layer 12.
In one embodiment, step 402 includes steps A1 through F1.
In step a1, a first silicon nitride layer is formed on the upper surface of N type epitaxial layer 12.
A first silicon nitride layer may be formed on the upper surface of the N-type epitaxial layer 12 by a vapor deposition or sputtering process. The thickness of the first silicon nitride layer may be 0.1 μm to 0.3 μm.
In step B1, a silicon dioxide layer is formed on the upper surface of the first silicon nitride layer.
A silicon dioxide layer may be formed on the upper surface of the first silicon nitride layer by a vapor deposition or sputtering process. The thickness of the silicon dioxide layer may be 1 μm to 5 μm.
In step C1, a second silicon nitride layer is formed on the upper surface of the silicon dioxide layer.
The second silicon nitride layer may be formed on the upper surface of the silicon dioxide layer by a vapor deposition or sputtering process. The thickness of the second silicon nitride layer may be 0.1 μm to 0.3 μm.
In step D1, a portion of the first silicon nitride layer, a portion of the silicon dioxide layer, and a portion of the second silicon nitride layer are removed to form a pillar trench.
And removing part of the first silicon nitride layer, part of the silicon dioxide layer and part of the second silicon nitride layer by dry etching to form the columnar trench.
In step E1, a third silicon nitride layer is formed on the upper surface of the second silicon nitride layer and the lower surface of the pillar trench.
The third silicon nitride layer may be formed on the upper surface of the second silicon nitride layer and the lower surface of the pillar-shaped trench by a process of vapor deposition, sputtering, or the like. The thickness of the third silicon nitride layer may be 0.2 μm to 0.5 μm.
In step F1, the third silicon nitride layer is etched back to expose the N-type epitaxial layer 12 at the lower surface of the columnar trench.
The third silicon nitride layer is maskless etched to expose the N-type epitaxial layer 12 at the lower surface of the pillar trench.
In step 403, as shown in fig. 4, the N-type epitaxial layer 12 is wet etched to form the convex trenches 30.
And wet etching the N-type epitaxial layer 12 by using the hard mask 20 as a mask to form the convex grooves 30. Wherein, the N-type epitaxial layer is etched by a wet method to be 2-4 mu m. The raised trenches 30 partially suspend the hard mask 20.
In step 404, as shown in fig. 5, a first P-type region 14 is formed on the lower surface of the convex trench 30 by ion implantation.
In step 404, the ion implantation is performed by conventional boron ion implantation, which may be performed at a dose of 1e12 to 9e12 and at an energy of 20Kev to 120 Kev.
At this time, the direction of ion implantation is perpendicular to the lower surface of the convex trench 30. The first P-type region 14 is formed as a low doped first P-type region 14.
After the step 404, annealing may be performed at 1050 ℃ to 1200 ℃ for 100 minutes to 600 minutes, the boron ions implanted in the step 404 and the N-type epitaxial layer 12 form a PN junction, the boron concentration at the bottom plane of the convex trench 30 is high and decreases to the abrupt PN junction, the boron annealing temperature and time need to be matched, and the N-type channel region of 1 μm to 2 μm is retained, that is, the N-type channel region is maintained above the side wall of the convex trench 30.
In step 405, as shown in fig. 6, a second P-type region 15 is formed by ion implantation under the side of the convex trench 30.
In one embodiment, the ion implantation is performed at a predetermined angle to form the highly doped second P-type region 15 under the side surface of the convex trench 30.
Wherein, the preset angle is obtained by the following calculation formula: α ≦ arctan (A/(B + C)); a is the width of the convex groove 30, B is the thickness of the hard mask 20, C is the depth of the convex groove 30, and α is a predetermined angle.
In step 405, the ion implantation concentration may be 1e13 to 9e15, and the implantation energy may be 20KeV to 120KeV, so as to obtain an implantation region in which the lower portion of the sidewall is concentrated by the high-concentration boron ions, and due to the suspended hard mask 20, the upper portion of the sidewall of the convex trench 30 is not affected by the ion implantation, and remains N-type.
In step 406, the hard mask 20 is removed to form the arc-shaped trench 13, as shown in FIG. 7.
In step 407, as shown in fig. 8, a sidewall mask 40 is formed on the side surface of the arc-shaped trench 13.
In one embodiment, step 407 includes steps A3 through B3.
In step a3, a silicon dioxide mask layer is formed on the upper surface of the N-type epitaxial layer 12 and the upper surface of the arc-shaped trench 13.
The silicon dioxide mask layer may have a thickness of 1 μm to 1.5 μm.
A silicon dioxide mask layer may be formed on the upper surface of the N-type epitaxial layer 12 and the upper surface of the arc-shaped trench 13 by a vapor deposition or sputtering process.
In step B3, the upper surface of the silicon dioxide mask layer is removed and the silicon dioxide mask layer on the side surfaces of the arc-shaped trenches 13 remains to form the sidewall mask 40.
The upper surface of the mask layer is etched without a mask until the N-type epitaxial layer is exposed and the silicon dioxide mask layer on the side surface of the arc-shaped trench 13 is remained to form a sidewall mask 40.
In step 408, as shown in fig. 9, ion implantation is performed on the upper surface of the N-type epitaxial layer 12 to form the P-type layer 11.
By way of example and not limitation, ion implantation is performed on the upper surface of the N-type epitaxial layer 12 and the lower surface of the arc-shaped trench 13 to form the P-type layer 11 and the third P-type region 16; the P-type layer 11 is located on the upper surface of the N-type epitaxial layer 12, and the third P-type region 16 is located on the lower surface of the arc-shaped trench 13 and is disposed on the upper surface of the first P-type region 14.
In step 408, a conventional boron ion implantation may be performed, wherein the implantation dose is 1e12 to 5e12, the energy is 20Kev to 200Kev, a planar implantation is formed, and since the sidewall of the arc-shaped trench 13 is protected by silicon dioxide, the boron ions implanted on the high sidewall and the planar implantation are activated through a low temperature anneal at 9500 ℃ to 1150 ℃ for 10 minutes to 40 minutes, so as to form the low-doped P-type layer 11 on the upper surface of the N-type epitaxial layer 12 and the high-doped third P-type region 16 on the lower surface of the arc-shaped trench 13.
In a specific implementation, after step 408, step 409 may be further included.
In step 409, the arc-shaped trench 13 is filled with metal, a first metal layer is formed on the upper surface of the P-type layer 11, and a second metal layer is formed on the lower surface of the N-type epitaxial layer 12.
Notably, the metal layer can be gold or palladium.
The embodiment of the invention comprises a P type layer, an N type epitaxial layer, an arc groove, a first P type area and a second P type area; the P-type layer is positioned on the upper surface of the epitaxial layer; the arc-shaped groove is hollowed out of the P-type layer and is positioned on the upper surface of the N-type epitaxial layer; the first P-type area is positioned below the arc-shaped groove; the second P-type area is arranged below the side face of the arc-shaped groove and is positioned on the upper surface of the P-type area; the upper part of the side surface of the arc-shaped groove with the doping concentration of the second P-type region being greater than that of the first P-type region is connected with the N-type epitaxial layer; the first P-type region and the second P-type region form the anode of the fast recovery diode, the N-type epitaxial layer below the first P-type region forms the cathode of the fast recovery diode, the P-type layer and the second P-type region form the gate of the junction field effect transistor, the N-type epitaxial layer above the side surface of the arc-shaped groove forms the drain of the junction field effect transistor, and the N-type epitaxial layer below the first P-type region forms the source of the junction field effect transistor; on one hand, the arc-shaped groove enables the first P-type region with low doping concentration to have a larger area, the second P-type region with high doping concentration reduces forward starting voltage, the first P-type region with large area and low doping concentration improves anti-surge capability, and therefore the anti-surge capability is improved while the forward starting voltage is increased; on the other hand, when the fast recovery power device is forward biased, the PN junction in the junction type field effect transistor is forward biased, the channel is widened, the on resistance is reduced, the forward starting voltage is further reduced, and when the fast recovery power device is reverse biased, the PN junction in the junction type field effect transistor is reverse biased, the channel is narrowed, the on resistance is increased, and the reverse withstand voltage capability of the fast recovery power device is improved.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (12)
1. A structure of a fast recovery power device, comprising:
a P-type layer and an N-type epitaxial layer; the P-type layer is positioned on the upper surface of the N-type epitaxial layer;
hollowing out the P-type layer and an arc-shaped groove which is positioned on the upper surface of the N-type epitaxial layer;
the first P-type region is positioned below the arc-shaped groove;
the second P-type region is arranged below the side face of the arc-shaped groove and is positioned on the upper surface of the P-type region; the doping concentration of the second P-type region is greater than that of the first P-type region;
and the upper part of the side surface of the arc-shaped groove is connected with the N-type epitaxial layer.
2. The structure of a fast recovery power device according to claim 1, further comprising:
and the third P-type region is positioned on the lower surface of the arc-shaped groove and is arranged on the upper surface of the first P-type region.
3. The structure of a fast recovery power device of claim 2, wherein the N-type epitaxial layer is a low doped N-type epitaxial layer, the first P-type region is a low doped first P-type region, the second P-type region is a high doped second P-type region, the third P-type region is a high doped third P-type region, and the P-type layer is a low doped P-type layer.
4. The structure of a fast recovery power device according to claim 1, wherein the arc-shaped trench is filled with a metal, a first metal layer is disposed on the upper surface of the P-type layer, and a second metal layer is disposed on the lower surface of the N-type epitaxial layer.
5. The structure of a fast recovery power device according to claim 1, wherein the fast recovery power device comprises a fast recovery diode and a junction field effect transistor; the first P-type region and the second P-type region are anodes of the fast recovery diode, the N-type epitaxial layer below the first P-type region is a cathode of the fast recovery diode, the P-type layer and the second P-type region are gates of the junction field effect transistor, the N-type epitaxial layer above the side surface of the arc-shaped groove is a drain electrode of the junction field effect transistor, and the N-type epitaxial layer below the first P-type region is a source electrode of the junction field effect transistor; and the grid electrode of the junction field effect transistor is connected with the drain electrode of the junction field effect transistor in common.
6. A method of fabricating a fast recovery power device, the method comprising:
forming an N-type epitaxial layer;
forming a hard mask on the upper surface of the N-type epitaxial layer;
wet etching the N-type epitaxial layer to form a convex groove;
ion implantation is carried out on the lower surface of the convex groove to form a first P-type area;
ion implantation is carried out below the side face of the convex groove to form a second P-type area;
removing the hard mask plate to form an arc-shaped groove;
forming a side wall mask on the side surface of the arc-shaped groove;
and implanting ions on the upper surface of the N-type epitaxial layer to form a P-type layer.
7. The method for manufacturing a fast recovery power device according to claim 6, wherein the step of performing ion implantation on the upper surface of the N-type epitaxial layer to form a P-type layer is specifically as follows:
ion implantation is carried out on the upper surface of the N-type epitaxial layer and the lower surface of the arc-shaped groove to form a P-type layer and a third P-type region; the P-type layer is positioned on the upper surface of the N-type epitaxial layer, and the third P-type region is positioned on the lower surface of the arc-shaped groove and is arranged on the upper surface of the first P-type region.
8. The method according to claim 6, wherein the ion implantation under the side surface of the convex trench to form the second P-type region is specifically:
performing ion implantation at a preset angle to form a highly doped second P-type region below the side face of the convex groove; wherein the preset angle is obtained by the following calculation formula: α = arctan (a/(B + C)); a is the width of the convex groove, B is the thickness of the hard mask, C is the depth of the convex groove, and alpha is the preset angle.
9. The method for manufacturing a fast recovery power device according to claim 6, wherein the forming of the sidewall mask on the side surface of the arc-shaped trench is specifically:
forming a silicon dioxide mask layer on the upper surface of the N-type epitaxial layer and the upper surface of the arc-shaped groove;
and removing the upper surface of the silicon dioxide mask layer and reserving the silicon dioxide mask layer on the side surface of the arc-shaped groove to form a side wall mask.
10. The method for manufacturing a fast recovery power device according to claim 6, further comprising, after the ion implantation on the upper surface of the N-type epitaxial layer to form a P-type layer:
and filling metal in the arc-shaped groove, forming a first metal layer on the upper surface of the P-type layer, and forming a second metal layer on the lower surface of the N-type epitaxial layer.
11. The method according to claim 6, wherein the forming a hard mask on the upper surface of the N-type epitaxial layer comprises:
forming a first silicon nitride layer on the upper surface of the N-type epitaxial layer;
forming a silicon dioxide layer on the upper surface of the first silicon nitride layer;
forming a second silicon nitride layer on the upper surface of the silicon dioxide layer;
removing part of the first silicon nitride layer, part of the silicon dioxide layer and part of the second silicon nitride layer to form a columnar trench;
forming a third silicon nitride layer on the upper surface of the second silicon nitride layer and the lower surface of the columnar groove;
and etching back the third silicon nitride layer to expose the N-type epitaxial layer on the lower surface of the columnar trench.
12. An electronic device characterized in that it comprises the structure of a fast recovery power device according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211072298.8A CN115132726B (en) | 2022-09-02 | 2022-09-02 | Structure and manufacturing method of fast recovery power device and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211072298.8A CN115132726B (en) | 2022-09-02 | 2022-09-02 | Structure and manufacturing method of fast recovery power device and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115132726A true CN115132726A (en) | 2022-09-30 |
| CN115132726B CN115132726B (en) | 2022-11-29 |
Family
ID=83387088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211072298.8A Active CN115132726B (en) | 2022-09-02 | 2022-09-02 | Structure and manufacturing method of fast recovery power device and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115132726B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115295414A (en) * | 2022-10-08 | 2022-11-04 | 深圳芯能半导体技术有限公司 | Silicon-based diode manufacturing method, silicon-based diode and diode device |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101366124A (en) * | 2005-12-27 | 2009-02-11 | 美商科斯德半导体股份有限公司 | Ultrafast recovery diode |
| CN101976687A (en) * | 2010-10-21 | 2011-02-16 | 电子科技大学 | Fast recovery metal oxide semiconductor diode with low power consumption |
| US20110089483A1 (en) * | 2008-06-30 | 2011-04-21 | Freescale Semiconductor, Inc. | Method of forming a power semiconductor device and power semiconductor device |
| CN102820294A (en) * | 2011-06-03 | 2012-12-12 | 飞兆半导体公司 | Integration of superjunction MOSFET and diode |
| CN102969350A (en) * | 2012-12-07 | 2013-03-13 | 株洲南车时代电气股份有限公司 | Trench gate IGBT (Insulated Gate Bipolar Transistor) chip |
| CN103579345A (en) * | 2012-07-30 | 2014-02-12 | 万国半导体股份有限公司 | High voltage field balanced mosfet |
| CN109192787A (en) * | 2018-07-19 | 2019-01-11 | 东南大学 | A kind of groove type anode fast recovery diode and manufacturing method with the control of the two poles of the earth Schottky |
| US20190067491A1 (en) * | 2017-06-22 | 2019-02-28 | Maxpower Semiconductor Inc. | Vertical Rectifier with Added Intermediate Region |
| CN109979936A (en) * | 2017-12-28 | 2019-07-05 | 无锡华润上华科技有限公司 | A kind of integrated-semiconductor device and electronic device |
| CN111081759A (en) * | 2019-12-10 | 2020-04-28 | 深圳第三代半导体研究院 | Enhanced silicon carbide MOSFET device and manufacturing method thereof |
| CN113707723A (en) * | 2021-10-26 | 2021-11-26 | 北京世纪金光半导体有限公司 | Semiconductor device based on pseudo channel and manufacturing method thereof |
| CN114975602A (en) * | 2022-07-29 | 2022-08-30 | 深圳芯能半导体技术有限公司 | High-reliability IGBT chip and manufacturing method thereof |
-
2022
- 2022-09-02 CN CN202211072298.8A patent/CN115132726B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101366124A (en) * | 2005-12-27 | 2009-02-11 | 美商科斯德半导体股份有限公司 | Ultrafast recovery diode |
| US20110089483A1 (en) * | 2008-06-30 | 2011-04-21 | Freescale Semiconductor, Inc. | Method of forming a power semiconductor device and power semiconductor device |
| CN101976687A (en) * | 2010-10-21 | 2011-02-16 | 电子科技大学 | Fast recovery metal oxide semiconductor diode with low power consumption |
| CN102820294A (en) * | 2011-06-03 | 2012-12-12 | 飞兆半导体公司 | Integration of superjunction MOSFET and diode |
| CN103579345A (en) * | 2012-07-30 | 2014-02-12 | 万国半导体股份有限公司 | High voltage field balanced mosfet |
| CN102969350A (en) * | 2012-12-07 | 2013-03-13 | 株洲南车时代电气股份有限公司 | Trench gate IGBT (Insulated Gate Bipolar Transistor) chip |
| US20190067491A1 (en) * | 2017-06-22 | 2019-02-28 | Maxpower Semiconductor Inc. | Vertical Rectifier with Added Intermediate Region |
| CN109979936A (en) * | 2017-12-28 | 2019-07-05 | 无锡华润上华科技有限公司 | A kind of integrated-semiconductor device and electronic device |
| CN109192787A (en) * | 2018-07-19 | 2019-01-11 | 东南大学 | A kind of groove type anode fast recovery diode and manufacturing method with the control of the two poles of the earth Schottky |
| CN111081759A (en) * | 2019-12-10 | 2020-04-28 | 深圳第三代半导体研究院 | Enhanced silicon carbide MOSFET device and manufacturing method thereof |
| CN113707723A (en) * | 2021-10-26 | 2021-11-26 | 北京世纪金光半导体有限公司 | Semiconductor device based on pseudo channel and manufacturing method thereof |
| CN114975602A (en) * | 2022-07-29 | 2022-08-30 | 深圳芯能半导体技术有限公司 | High-reliability IGBT chip and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115295414A (en) * | 2022-10-08 | 2022-11-04 | 深圳芯能半导体技术有限公司 | Silicon-based diode manufacturing method, silicon-based diode and diode device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115132726B (en) | 2022-11-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5787853B2 (en) | Power semiconductor device | |
| JP5989652B2 (en) | Improved Schottky rectifier | |
| CN110504310B (en) | RET IGBT with self-bias PMOS and manufacturing method thereof | |
| US9018698B2 (en) | Trench-based device with improved trench protection | |
| US8264036B2 (en) | Power semiconductor device with low on-state voltage and method of manufacturing the same | |
| CN111211168B (en) | RC-IGBT chip and manufacturing method thereof | |
| CN114300543B (en) | Electron extraction type freewheeling diode device and preparation method thereof | |
| JP7403401B2 (en) | semiconductor equipment | |
| US8860025B2 (en) | Semiconductor device and method for manufacturing the semiconductor device | |
| CN116153991B (en) | Dual-trench-gate RC-IGBT and preparation method thereof | |
| CN113838918B (en) | Super-junction IGBT device structure with carrier concentration enhancement and manufacturing method | |
| CN111430453A (en) | RC-IGBT chip with good reverse recovery characteristic and manufacturing method thereof | |
| CN113345807A (en) | Semiconductor device preparation method | |
| CN115132726B (en) | Structure and manufacturing method of fast recovery power device and electronic equipment | |
| CN113451397A (en) | RC-IGBT device and preparation method thereof | |
| CN114220870A (en) | Omnidirectional Schottky contact trench type semiconductor device and manufacturing method thereof | |
| JP2011003727A (en) | Semiconductor device, and method of manufacturing the same | |
| CN116759424A (en) | Self-aligned trench type silicon carbide hybrid diode structure and preparation method thereof | |
| CN115117149B (en) | Fast recovery diode based on wet etching process and preparation method thereof | |
| CN115295414B (en) | Silicon-based diode manufacturing method, silicon-based diode and diode device | |
| CN115172445B (en) | Structure and manufacturing method of fast recovery power device and electronic equipment | |
| CN115440794A (en) | Silicon carbide power device | |
| CN217544626U (en) | Shielding grid power device capable of fast reverse recovery | |
| KR102463180B1 (en) | Semiconductor device and method manufacturing the same | |
| JP2024013911A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |