CN102969350A - Trench gate IGBT (Insulated Gate Bipolar Transistor) chip - Google Patents
Trench gate IGBT (Insulated Gate Bipolar Transistor) chip Download PDFInfo
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- CN102969350A CN102969350A CN2012105209245A CN201210520924A CN102969350A CN 102969350 A CN102969350 A CN 102969350A CN 2012105209245 A CN2012105209245 A CN 2012105209245A CN 201210520924 A CN201210520924 A CN 201210520924A CN 102969350 A CN102969350 A CN 102969350A
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- trench gate
- igbt chip
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- type igbt
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 31
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Abstract
Description
Technical field
The present invention relates to a kind of semiconductor IGBT(Insulted Gate Bipolar Transistor, insulated gate bipolar transistor) chip structure, especially relate to a kind of trench gate type igbt chip structure with dual hole barrier effect.
Background technology
Igbt (IGBT) has that on-state voltage drop is low, current capacity is large, input impedance is high, fast response time and the simple characteristics of control, is widely used in industry, information, new forms of energy, medical science, traffic, military affairs and aviation field.In order to reduce the conduction voltage drop of IGBT, people adopt trench gate structure, and raceway groove from laterally becoming vertically, has been eliminated R in the conducting resistance JFETImpact.Dwindled simultaneously the cellular size, greatly improved cellular density, the raceway groove overall width of each chip increases, and has reduced channel resistance.On the other hand, because the polysilicon gate area increases, reduce distributed resistance, be conducive to improve switching speed.Be conventional trench gate IGBT as shown in Figure 1, comprise emitter 1, gate pole 2, P-trap 3, N drift region 4, N buffering area 5 and collector electrode 6.
The IGBT of a new generation is towards high power density more, high workload junction temperature more, and the future development of low-power consumption more, and well-known, there are contradictory relation in conduction voltage drop Vceon and the turn-off power loss of IGBT.Because the conductivity modulation effect of IGBT after all, be the large conductivity modulation effect of injection efficiency energy enhance device when conducting, reduce conduction voltage drop, yet when turn-offing, it is compound that a large amount of minority carriers needs the longer time to finish, and increased turn-off power loss.In order to improve this contradictory relation, people are devoted to the injection efficiency of IGBT is studied, and reduce on the one hand the hole injection efficiency of IGBT collector electrode (anode), improve on the other hand the electron injection efficiency of emitter (negative electrode).Can improve well the conduction voltage drop of IGBT and the tradeoff of turn-off power loss like this.At present, for trench gate IGBT, mainly contain the method for following several change emitters (negative electrode) electron injection efficiency:
The first structure is IEGT(Injection Enhanced Gate Transistor as shown in Figure 2, electron injection enhancement gate pole transistor) structure.Because the cellular of IGBT is parallel-connection structure, the emitter of its each cellular also is in parallel.The emitter of cellular is carried out selectivity do not draw (not being fully) and carry out parallel connection, just formed like this a hole accumulation region below the emitter of not drawing, correspondingly, the injection of electronics just has been enhanced.This structure is invented in 1993 by Toshiba, and further improves in 1998.
The second structure as shown in Figure 3, Mitsubishi is on the basis of IGBT, by the change (width, N+ source area and P+ collector area) of cellular having been proposed the structure of similar IEGT.The cellular width of this structure is several times of normal IGBT cellular, be provided with the N+ source area between two trench gate in single cellular, the doping content lower (P-) of corresponding below, this zone collector area is to reach electron injection enhancement effect (IE-effect).Can be described as by to the change of IGBT cellular to reach the effect of IEGT.
Foregoing various technology has all strengthened the conductivity modulation effect of IGBT to a certain extent, thereby reduced conduction voltage drop, but these schemes all are only to have single hole barrier effect (only have the potential barrier blocking effect or only have the physical barriers effect).Yet in order further to improve the power density of IGBT, working junction temperature and long-term reliability need to continue optimization and reduce the conduction voltage drop of IGBT and the tradeoff of turn-off power loss, realize lower power consumption.For this reason, need to continue the structure of research and improvement trench gate IGBT to realize this purpose.
Summary of the invention
The purpose of this invention is to provide a kind of trench gate type igbt chip, improved the power density of igbt chip, working junction temperature, and the reliability of long-term work, improved simultaneously the conductivity modulation effect of igbt chip to reduce conduction voltage drop, do not improve again simultaneously the injection efficiency of the few son in hole, thereby optimize and reduced the conduction voltage drop of igbt chip and the tradeoff of turn-off power loss, realized lower power consumption.
In order to realize the foregoing invention purpose, the present invention specifically provides a kind of technic relization scheme of trench gate type igbt chip, a kind of trench gate type igbt chip, comprise at least one cellular, cellular comprises: the collector electrode metal electrode that is arranged in order, P+ collector area, N-drift region, P-base, P+ ohmic contact regions, N+ source area, gate oxide, polysilicon gate, emitter metal electrode and gate metal electrode, and the emitter metal electrode that is arranged on P+ ohmic contact regions top.The polysilicon gate of trench gate type igbt chip adopts trench gate structure.Trench gate type igbt chip also comprises N-type charge carrier buried regions, and N-type charge carrier buried regions comprises the first N-type charge carrier buried regions, and the first N-type charge carrier buried regions is positioned at the below of P-base.
In order to realize the foregoing invention purpose, the present invention also specifically provides the technic relization scheme of another trench gate type igbt chip, comprise at least one cellular, cellular comprises: the collector electrode metal electrode that is arranged in order, P+ collector area, N-drift region, P-base, P+ ohmic contact regions, N+ source area, gate oxide, polysilicon gate, emitter metal electrode and gate metal electrode, and the emitter metal electrode that is arranged on P+ ohmic contact regions top.The polysilicon gate of trench gate type igbt chip adopts trench gate structure.Trench gate type igbt chip also comprises N-type charge carrier buried regions, and N-type charge carrier buried regions comprises the second N-type charge carrier buried regions, and the second N-type charge carrier buried regions is positioned at the below of gate oxide of the polysilicon gate bottom of channel shaped.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, N-type charge carrier buried regions also comprises the first N-type charge carrier buried regions, and the first N-type charge carrier buried regions is positioned at the below of P-base.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, trench gate type igbt chip also comprises dielectric buried layer, and dielectric buried layer is positioned at the periphery, below of P-base, with the intersection of the first N-type charge carrier buried regions.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, trench gate type igbt chip also comprises dielectric buried layer, and dielectric buried layer is positioned at the below of the first N-type charge carrier buried regions, nestles up the first N-type charge carrier buried regions setting.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the doping content of N-type charge carrier buried regions is 8E15/cm 3～2E16/cm 3
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the junction depth of N-type charge carrier buried regions is 0.5um～2um.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the width of the first N-type charge carrier buried regions is identical with the width of P-base.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the width of the second N-type charge carrier buried regions is identical with the width of polysilicon gate.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the shape that the first N-type charge carrier buried regions is overlooked on the direction in chip front side is identical with the shape of P-base.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the shape that the second N-type charge carrier buried regions is overlooked on the direction in chip front side is identical with the shape of polysilicon gate.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the first N-type charge carrier buried regions is overlooked from chip front side in single cellular scope and is shaped as bar shaped or square or regular hexagon or circle or triangle or arbitrary polygon on the direction.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the second N-type charge carrier buried regions is overlooked from chip front side in single cellular scope and is shaped as bar shaped or square or regular hexagon or circle or triangle or arbitrary polygon on the direction.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, trench gate type igbt chip also comprises N resilient coating district, and N resilient coating district is positioned between N-drift region and the P+ collector area.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the backing material of trench gate type igbt chip is the semiconductor material with wide forbidden band that comprises Si semi-conducting material or SiC or GaN or diamond.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the doping content of backing material is 8E12/cm 3～5E14/cm 3
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the thickness of backing material is 60um～750um.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the material of dielectric buried layer is for comprising SiO 2Or nitrogen oxide is at interior insulating material.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, dielectric buried layer is positioned at the first N-type charge carrier buried regions.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the thickness of dielectric buried layer is 0.1um～1.5um.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the gate oxide noncontact of dielectric buried layer and polysilicon gate bottom.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the spacing between dielectric buried layer and the gate oxide is 0.2um～1um.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the even thickness setting of dielectric buried layer.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the shape of dielectric buried layer is identical with the shape that the first N-type charge carrier buried regions is overlooked on the direction in chip front side.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, dielectric buried layer is overlooked in chip front side in single cellular scope and is shaped as bar shaped or square or regular hexagon or circle or triangle or arbitrary polygon on the direction.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, dielectric buried layer is set to a plurality ofly overlook the combination that direction is shaped as the figure of vertical bar or horizontal stripe or circle or arbitrary polygon from chip front side in single cellular.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, a plurality of figures of dielectric buried layer in single cellular are the combination of an identical figure.
Further improvement as the another kind of trench gate type of the present invention igbt chip technical scheme is in contact with one another between a plurality of figures of dielectric buried layer in single cellular.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the thick 0.2um～1.5um of thickness at the Thickness Ratio middle part of two ends of dielectric buried layer.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, two ends of dielectric buried layer or wherein any one end be provided with downward termination.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the middle part of dielectric buried layer is provided with a plurality of downward terminations.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the thickness of the termination of dielectric buried layer is identical or not identical.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the width of the termination of dielectric buried layer is identical or not identical.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, the spacing between the termination of dielectric buried layer is identical or not identical.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, when trench gate type igbt chip comprises plural cellular, be provided with the first N-type charge carrier buried regions at all cellulars or the part cellular of trench gate type igbt chip.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, when trench gate type igbt chip comprises plural cellular, be provided with the second N-type charge carrier buried regions at all cellulars or the part cellular of trench gate type igbt chip.
As the further improvement of the another kind of trench gate type of the present invention igbt chip technical scheme, when trench gate type igbt chip comprises plural cellular, be provided with dielectric buried layer at all cellulars or the part cellular of trench gate type igbt chip.
By implementing the technical scheme of a kind of trench gate type of the invention described above igbt chip, have following technique effect:
The present invention proposes a kind of trench gate igbt chip structure with dual hole barrier effect, can be simultaneously potential barrier be played near the hole the IGBT emitter and stop effect with physical barriers.Compare with substance blocking effect structure, this chip structure can improve the hole concentration of IGBT emitter near zone widely.Correspondingly, greatly improved the electron injection efficiency at this place, thereby further strengthened the conductivity modulation effect of IGBT drift region, made the conduction voltage drop of IGBT less, final more excellent conduction voltage drop and the tradeoff of turn-off power loss of obtaining.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural representation of a kind of conventional trench gate type IGBT of prior art.
Fig. 2 is the transistorized structural representation of a kind of electron injection enhancement gate pole of prior art.
Fig. 3 is the structural representation of a kind of similar electron injection enhancement gate pole transistor structure devices of prior art.
Fig. 4 is the longitudinal profile structural representation of single cellular in a kind of embodiment of trench gate type igbt chip of the present invention.
Fig. 5 is the plan structure schematic diagram of N-type charge carrier buried regions in the single cellular of a kind of embodiment of trench gate type igbt chip of the present invention.
Fig. 6 is the plan structure schematic diagram of N-type charge carrier buried regions in a plurality of cellulars of a kind of embodiment of trench gate type igbt chip of the present invention.
Fig. 7 is the plan structure schematic diagram of N-type charge carrier buried regions in a plurality of cellulars of the another kind of embodiment of trench gate type igbt chip of the present invention.
Fig. 8 is the plan structure schematic diagram of N-type charge carrier buried regions in a plurality of cellulars of the third embodiment of trench gate type igbt chip of the present invention.
Fig. 9 is the plan structure schematic diagram of dielectric buried layer in the single cellular of a kind of embodiment of trench gate type igbt chip of the present invention.
Figure 10 is the plan structure schematic diagram of dielectric buried layer in a plurality of cellulars of a kind of embodiment of trench gate type igbt chip of the present invention.
Figure 11 is the plan structure schematic diagram of dielectric buried layer in a plurality of cellulars of the another kind of embodiment of trench gate type igbt chip of the present invention.
Figure 12 is the longitudinal profile structural representation of the single cellular of the another kind of embodiment of trench gate type igbt chip of the present invention.
Figure 13 is the plan structure schematic diagram of the single cellular medium of the another kind of embodiment of trench gate type igbt chip of the present invention buried regions.
Figure 14 is the cross-sectional view of the single cellular medium of a kind of embodiment of trench gate type igbt chip of the present invention buried regions.
Figure 15 is the longitudinal profile structural representation of the single cellular of the third embodiment of trench gate type igbt chip of the present invention.
Figure 16 is the conduction voltage drop contrast schematic diagram of the present invention and the conventional trench gate type of prior art IGBT.
Among the figure: 1-emitter, 2-gate pole, 3-P-trap, 4-N drift region, the 5-N buffering area, 6-collector electrode, 10-N-drift region, 11-N resilient coating district, the 12-P+ collector area, 13-P-base, 14-P+ ohmic contact regions, the 15-N+ source area, 16-the first N-type charge carrier buried regions, 17-the second N-type charge carrier buried regions, the 20-gate oxide, 21-dielectric buried layer, 30-polysilicon gate, 40-collector electrode metal electrode, 41-emitter metal electrode, 42-gate metal electrode.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is a part of embodiment of the present invention, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
To shown in the accompanying drawing 16, provided the specific embodiment of a kind of trench gate type of the present invention igbt chip such as accompanying drawing 4, the invention will be further described below in conjunction with the drawings and specific embodiments.
The cross-sectional view of single cellular in a kind of embodiment of trench gate type igbt chip of the present invention as shown in Figure 12, trench gate type igbt chip generally includes a plurality of cellulars, adopts the insulated gate bipolar transistor of this chip structure to have dual hole barrier effect.Technical scheme shown in the accompanying drawing 12 is: a kind of trench gate type igbt chip, comprise at least one cellular, cellular comprises: collector electrode metal electrode 40, P+ collector area 12, N-drift region 10, P-base 13, P+ ohmic contact regions 14, N+ source area 15, gate oxide 20, polysilicon gate 30, emitter metal electrode 41 and gate metal electrode 42.Collector electrode metal electrode 40, P+ collector area 12, N-drift region 10, P-base 13, P+ ohmic contact regions 14, N+ source area 15, gate oxide 20, polysilicon gate 30 and gate metal electrode 42 are arranged in order from bottom to up.The top of P+ ohmic contact regions 14 is provided with emitter metal electrode 41.The polysilicon gate 30 of insulated gate bipolar transistor (IGBT) chip further adopts trench gate structure.The first N-type charge carrier buried regions 16 is set below the P-base 13 of the single cellular of trench gate type igbt chip, and/or the second N-type charge carrier buried regions 17 is set, and at the intersection of P-base 13 and the first N-type charge carrier buried regions 16 dielectric buried layer 21 is set below polysilicon gate 30.When adopting the IGBT conducting of structure of the present invention, the potential barrier that near the hole the IGBT emitter is subject to N-type charge carrier buried regions stops, and the dual barrier effect of the physical barriers of dielectric buried layer 21.Therefore, improved widely the hole concentration of IGBT emitter near zone, correspondingly improved the electron injection efficiency at this place, thereby further strengthened the conductivity modulation effect of IGBT drift region near this end of emitter, make the conduction voltage drop of IGBT less, final more excellent conduction voltage drop and the tradeoff of turn-off power loss of obtaining.
The dual hole barrier principle that trench gate type igbt chip of the present invention adopts is: when the IGBT forward conduction, be injected into the minority carrier hole of N-drift region 10 from the P+ collector area 12 at IGBT back, can be by N-drift region 10 near P-base 13 motions (being extracted by P-base 13) the IGBT emitter.When arriving N-type charge carrier buried regions, because the barrier effect of potential barrier, holoe carrier is stopped, gathers near N-type charge carrier buried regions, has correspondingly increased electron injection efficiency.After the hole sees through N-type charge carrier buried regions, also continue to be subject to the physical barriers of dielectric buried layer 21, proceed to gather, further increase electron injection efficiency.Because the hole is subject to dual stopping, can form more and gather, electron injection efficiency is just larger, and conductivity modulation effect is just stronger.
In the cutaway view as shown in Figure 12, igbt chip is followed successively by collector electrode metal electrode 40, P+ collector area 12, N resilient coating district 11(from top to bottom can be had, if having, then vertical pressure-resistance structure of device is SPT, Soft-Punch Through, soft punch-through, also claim FS, field stop, electric field cut-off structure, perhaps LPT, Low-Punch Through, weak punch-through, perhaps TPT, Thin-Punch through, thin punch-through etc.Can not have yet, if do not have, then vertical pressure-resistance structure of device is NPT, Non-Punch through, non-punch-through), N-drift region 10, N-type charge carrier buried regions (comprising the first N-type charge carrier buried regions 16 and the second N-type charge carrier buried regions 17), dielectric buried layer 21, P-base 13, P+ ohmic contact regions 14, N+ source area 15, gate oxide 20, polysilicon gate 30, emitter metal electrode 41 and gate metal electrode 42.Wherein, this that is provided with emitter metal electrode 41 and gate metal electrode 42 simultaneously is the front of trench gate type igbt chip of the present invention, and be provided with collector electrode metal electrode 40 this simultaneously be the reverse side of trench gate type igbt chip.
As shown in Figure 8, cellular a only has the first N-type charge carrier buried regions 16, and cellular b does not have the first N-type charge carrier buried regions 16 and the second N-type charge carrier buried regions 17, and cellular c only has the second N-type charge carrier buried regions 17, existing the first N-type charge carrier buried regions 16 has again the second N-type charge carrier buried regions 17 among the cellular d.Here only take the hexagon cellular as example, also applicable to the cellular of other shapes.
The backing material of trench gate type igbt chip of the present invention can be common Si semi-conducting material or the wide bandgap semiconductor materials such as SiC, GaN and diamond.The doping content of backing material is 8E12/cm 3～5E14/cm 3Thickness is 60um～750um.
Shown in a kind of embodiment of accompanying drawing 12, the trench gate type igbt chip structure with dual hole barrier effect adopts the combination of N-type charge carrier buried regions and dielectric buried layer 21.Specific as follows:
1, N-type charge carrier buried regions
(A1) N-type charge carrier buried regions comprises first and second two parts, first's (the first N-type charge carrier buried regions 16) is positioned at the below of P-base 13, and second portion (the second N-type charge carrier buried regions 17) is positioned at the below of gate oxide 20 of polysilicon gate 30 bottoms of channel shaped.As shown in Figure 4, these two parts can have simultaneously, also can only have one of them.
(A2) on the basis of A1, the first N-type charge carrier buried regions 16 and/or the second N-type charge carrier buried regions 17 can arrange each cellular of IGBT, and also can select arbitrarily N(N is integer, the cellular of 1≤N≤igbt chip sum) individual cellular arranges.
(A3) doping content of the first N-type charge carrier buried regions 16 and/or the second N-type charge carrier buried regions 17 is 8E15/cm 3～2E16/cm 3, the concentration of the first N-type charge carrier buried regions 16 and/or the second N-type charge carrier buried regions 17 can be identical, also can be different.
(A4) junction depth of the first N-type charge carrier buried regions 16 and/or the second N-type charge carrier buried regions 17 is 0.5um～2um, and the junction depth of the first N-type charge carrier buried regions 16 and/or the second N-type charge carrier buried regions 17 can be identical, also can be different.
(A5) width of the width of the first N-type charge carrier buried regions 16 and P-base 13 (shown in accompanying drawing 4,12,15 chip longitudinal sectional drawing) is identical, and the width of the second N-type charge carrier buried regions 17 is identical with the width of polysilicon gate 30.Need to prove that because polysilicon gate 30 is almost identical with the width of gate oxide 20, generally about 0.1um, therefore from accompanying drawing, the width of the second N-type charge carrier buried regions 17 and the width of gate oxide 20 also are basic identical to the thickness that gate oxidation is 20 layers.
(A6) shown in accompanying drawing 5,6 and 7, the shape of the first N-type charge carrier buried regions 16 and the shape of P-base 13 (are overlooked direction overlooking on the direction, from facing down of igbt chip) identical, the shape of the second N-type charge carrier buried regions 17 and the shape of polysilicon gate 30 overlook on the direction identical.Particularly, the first N-type charge carrier buried regions 16 and/or the second N-type charge carrier buried regions 17 can be bar shaped or square or regular hexagon or circle or triangle or other polygons (vertical view as shown in accompanying drawing 5, accompanying drawing 6 and accompanying drawing 7 there is shown bar shaped, square and regular hexagon).If the shape of P-base 13 is square, the first N-type charge carrier buried regions 16 also is square; If the shape of P-base 13 is regular hexagons, then the first N-type charge carrier buried regions 16 also is regular hexagon; If the shape of P-base 13 is other shapes, the shape of the first N-type charge carrier buried regions 16 is also identical with it.Shown in accompanying drawing 5 and 12, the width L1 of the first N-type charge carrier buried regions 16 equals the width L4 of P-base 13, and the width L2 of the second N-type charge carrier buried regions 17 equals the width L5 of polysilicon gate 30.
2, dielectric buried layer 21:
(B1) material of dielectric buried layer 21 is SiO 2, the insulating material such as nitrogen oxide.
(B2) dielectric buried layer 21 is positioned at the below of P-base 13 and the intersection of the first N-type charge carrier buried regions 16.
(B3) thickness of dielectric buried layer 21 is 0.1um～1.5um, is positioned at the first N-type charge carrier buried regions 16.
(B4) as shown in Figure 12, the two ends of dielectric buried layer 21 do not contact with the gate oxide of trench gate 20, and spacing is 0.2um～1um.
(B5) shape of dielectric buried layer 21 is identical with the shape of the first N-type charge carrier buried regions 16, particularly, can be bar shaped or square or regular hexagon or circle or triangle or other polygons (vertical view as shown in accompanying drawing 9, accompanying drawing 10 and accompanying drawing 11 there is shown bar shaped, square and regular hexagon).
(B6) as shown in Figure 13, the shape of dielectric buried layer 21 can also be: be a plurality of vertical bars or horizontal stripe or circle or arbitrary polygon in single cellular.Can be repeated by a kind of figure of shape to arrange, also can be the combination setting of the figure of various shape.Do not contact (spacing in the B4 requirement) with gate oxide 20 as long as guarantee the edge of dielectric buried layer 21, can contact between dielectric buried layer 21 figures and the figure, can not contact yet.
(B7) as shown in Figure 14, on the basis of (B6), the thickness of dielectric buried layer 21 can evenly arrange, and also can inhomogeneously arrange.Be specially: from its cutaway view, the thick 0.2um～1.5um of thickness in the middle of the Thickness Ratio at two ends (setting is not up considered down in the termination) can arrange downward termination in two ends, can also only downward termination be set at one end, a plurality of downward terminations can also be set in the centre.The thickness of each termination can be identical, also can be not identical.The width of each termination can be identical, also can be not identical.Spacing between the termination can be identical, also can be not identical.Such shape is stronger to the blocking effect in hole.
In addition, dielectric buried layer 21 also can carry out the selectivity setting, namely can dielectric buried layer 21 all be set to all cellulars, also can dielectric buried layer 21 be set to the part cellular, can be with reference to the selectivity setting of aforesaid the first N-type charge carrier buried regions 16 and/or the second N-type charge carrier buried regions 17.
As shown in Figure 15, as another kind of execution mode, trench gate type IGBT structure with dual hole barrier effect it is also contemplated that the information such as the associated shape of N-type charge carrier buried regions and dielectric buried layer 21, concentration, thickness the same (comprising the possible situation of aforesaid institute), just on the lengthwise position dielectric buried layer 21 is displaced downwardly to the first N-type charge carrier buried regions 16 below, nestle up the first N-type charge carrier buried regions 16 and arrange.Shown in accompanying drawing 9 and 12, in single cellular, the width of dielectric buried layer 21 is L3.
As shown in Figure 16, be the trench gate type IGBT(D line of routine), only have the trench gate type IGBT(C line of N-type charge carrier buried regions), only have the trench gate type IGBT(B line of dielectric buried layer 21) and trench gate type IGBT(A line with dual hole barrier effect) the contrast of conduction voltage drop.Can find out that the conduction voltage drop with trench gate type IGBT of dual hole barrier effect is significantly reduced.
The present invention proposes a kind of trench gate type IGBT structure with dual hole barrier effect, utilizes the potential barrier of N-type charge carrier buried regions to stop, and the physical barriers of dielectric buried layer 21.Dual hole barrier effect is so that near the hole concentration the IGBT emitter improves greatly, and the conductivity modulation effect in the N-drift region 10 of IGBT strengthens greatly, thereby greatly reduces the conduction voltage drop of IGBT.The present invention goes out to send the enhancing conductivity modulation effect from improving IGBT emitter electron injection efficiency, thereby when reducing the IGBT forward voltage drop, and what impact turn-off time of IGBT is not had.In addition, dielectric buried layer 21 can be arranged on the PN junction place between P-base 13 and the N-type charge carrier buried regions, has reduced as much as possible relevant ghost effect.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Although the present invention discloses as above with preferred embodiment, yet is not to limit the present invention.Any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, any simple modification of above embodiment being done according to technical spirit of the present invention, be equal to replacements, equivalence changes and modify, all still belong in the scope that technical solution of the present invention protects.
Claims (38)
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| CN105633139A (en) * | 2016-03-23 | 2016-06-01 | 无锡新洁能股份有限公司 | IGBT device with carrier storage structure and manufacturing method of IGBT device |
| CN110504311A (en) * | 2019-08-29 | 2019-11-26 | 电子科技大学 | A kind of IGBT with short-circuit self-shield ability |
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| CN110504311A (en) * | 2019-08-29 | 2019-11-26 | 电子科技大学 | A kind of IGBT with short-circuit self-shield ability |
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| CN102969350B (en) | 2016-04-20 |
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