JP2024013911A - semiconductor equipment - Google Patents

Abstract

The present invention provides a semiconductor device with reduced switching loss. A semiconductor device 100 including a transistor section and a diode section 80, in which the diode section is provided in a first conductivity type region 11 provided on a front surface 21 of a semiconductor substrate 10 and above the semiconductor substrate. The semiconductor substrate 10 includes a Schottky junction electrode which is connected to the first conductivity type region 11 by Schottky junction, and a plurality of trench portions 30 provided on the front surface 21 of the semiconductor substrate 10 . The Schottky junction electrode forms a Schottky junction with a first conductivity type region provided in the mesa section 81 between the plurality of trench sections, and the trench depth of the plurality of trench sections is Dt, and the trench depth between the plurality of trench sections is Dt. When the mesa width in the mesa portion is Wm, Dt/Wm≧2 is satisfied. [Selection diagram] Figure 1B

Description

The present invention relates to a method for manufacturing a semiconductor device.

Patent Document 1 describes providing a PN diode having an RFC (Relaxed Field of Cathode) structure.
[Prior art documents]
[Patent document]
Patent Document 1: Japanese Patent Application Publication No. 2016-195271 Patent Document 2: Japanese Patent Application Publication No. 2016-225345

A semiconductor device with reduced switching loss is provided.

In a first aspect of the present invention, there is provided a semiconductor device including a diode section, wherein the diode section includes a first conductivity type region provided on a front surface of a semiconductor substrate and a first conductivity type region provided above the semiconductor substrate. The present invention provides a semiconductor device comprising: a Schottky junction electrode that is Schottky-junctioned with the first conductivity type region; and a plurality of trench portions provided on a front surface of the semiconductor substrate. The Schottky junction electrode may form a Schottky junction with the first conductivity type region provided in a mesa section between the plurality of trench sections. A trench depth Dt of the plurality of trench portions and a mesa width Wm of a mesa portion between the plurality of trench portions may satisfy Dt/Wm≧2.

The above semiconductor device may include a cathode region provided on the back surface of the semiconductor substrate. The cathode region includes a first cathode portion of a first conductivity type having a higher doping concentration than the first conductivity type region, and a second cathode portion provided adjacent to the first cathode portion on the back surface of the semiconductor substrate. and a conductive type second cathode portion.

In any of the above semiconductor devices, the doping concentration of the first conductivity type region may be 1E12 cm ^-3 or more and 2E14 cm ^-3 or less.

Any of the above semiconductor devices may include a first conductivity type drift region provided above the cathode region in the semiconductor substrate. The first conductivity type region may be the drift region extending to the front surface of the semiconductor substrate.

In any of the above semiconductor devices, the doping concentration of the first cathode portion may be 1E13 cm ^-3 or more and 1E20 cm ^{-3 or} less.

In any of the above semiconductor devices, the doping concentration of the second cathode portion may be 1E13 cm ^-3 or more and 1E18 cm ^{-3 or} less.

In any of the above semiconductor devices, the first cathode portion and the second cathode portion may be provided alternately at a predetermined pitch on the back surface of the semiconductor substrate. A pitch between the first cathode part and the second cathode part may be 0.5 μm or more and 50.0 μm or less.

In any of the above semiconductor devices, the plurality of trench portions at both ends of the mesa portion that are Schottky-contacted with the Schottky junction electrode may be set to the potential of the Schottky junction electrode.

In any one of the semiconductor devices described above, the plurality of trench portions at both ends of the mesa portion that are Schottky-junctioned with the Schottky junction electrode may be set to a gate potential.

In any one of the above semiconductor devices, the semiconductor substrate is located on the back surface side of the semiconductor substrate with respect to the center in the depth direction of the semiconductor substrate, and is located on the back surface side of the semiconductor substrate rather than the cathode region in the depth direction of the semiconductor substrate. A buffer region of the first conductivity type may be provided on the surface side.

Any of the above semiconductor devices may include a transistor section. The transistor section is provided on the front surface of the semiconductor substrate, and includes a first conductivity type emitter region having a higher doping concentration than the first conductivity type region, and a second conductivity type emitter region provided below the emitter region. The semiconductor device may include a conductive type base region and a second conductive type collector region provided on the back surface of the semiconductor substrate and having a higher doping concentration than the base region.

In any of the above semiconductor devices, the transistor section and the diode section may each include a plurality of trench sections on the front surface of the semiconductor substrate.

In any of the above semiconductor devices, the transistor section may include a boundary section provided adjacent to the diode section. The boundary portion may include a second conductivity type contact region having a higher doping concentration than the base region on the front surface of the semiconductor substrate.

In any of the above semiconductor devices, the transistor section may include a boundary section provided adjacent to the diode section. The boundary portion may include the first conductivity type region on the front surface of the semiconductor substrate.

In any of the above semiconductor devices, the collector region below the boundary portion may be provided adjacent to the first cathode portion.

Note that the above summary of the invention does not list all the features of the invention. Furthermore, subcombinations of these features may also constitute inventions.

An example of a top view of the semiconductor device 100 is shown. An example of the aa' cross section in FIG. 1A is shown. 7 is a top view of a modification of the semiconductor device 100. FIG. A bb' cross section of a modification of the semiconductor device 100 is shown. 7 is a top view of a modification of the semiconductor device 100. FIG. FIG. 5 is a cross-sectional view of a semiconductor device 500 according to a comparative example. An example of the voltage waveform of the diode section 80 is shown. An example of the current waveform of the diode section 80 is shown. It is a graph of a linear scale showing the electrical characteristics of a PN diode. 1 is a graph on a logarithmic scale showing electrical characteristics of a PN diode. FIG. 3 is a diagram showing a current waveform during reverse recovery of a PN diode. FIG. 3 is a diagram showing a voltage waveform during reverse recovery of a PN diode. 7 is a graph showing potential energy of a diode section 80. FIG. The withstand voltage of a Schottky barrier diode as a comparative example is shown. The breakdown voltage of the Schottky barrier diode of the example is shown. 7 is a diagram showing the dependence of the breakdown voltage of the diode section 80 on the mesa width. FIG.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all combinations of features described in the embodiments are essential to the solution of the invention.

In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper" and the other side is referred to as "lower". Among the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The "up" and "down" directions are not limited to the gravitational direction or the direction in which the semiconductor device is mounted.

In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes only specify the relative positions of the components and do not limit specific directions. For example, the Z axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are directions opposite to each other. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and the -Z-axis.

In this specification, orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and the Y-axis. Further, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, a direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as a horizontal direction.

In this specification, when the term "same" or "equal" is used, it may also include the case where there is an error due to manufacturing variations or the like. The error is, for example, within 10%.

In this specification, the conductivity type of the doped region doped with impurities is described as P type or N type. In this specification, an impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N-type conductivity type or a semiconductor exhibiting a P-type conductivity type.

In this specification, when described as P+ type or N+ type, it means that the doping concentration is higher than P type or N type, and when described as P− type or N− type, it means that the doping concentration is higher than P type or N type. It means that the concentration is low. Further, in this specification, when it is described as P++ type or N++ type, it means that the doping concentration is higher than that of P+ type or N+ type. Similarly, when it is described as N--type or P--type, it means that the doping concentration is lower than that of P-type or N-type.

FIG. 1A shows an example of a top view of the semiconductor device 100. The semiconductor device 100 of this example is a semiconductor chip including a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). The transistor section 70 of this example includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80.

The transistor section 70 is a region obtained by projecting the collector region 22 provided on the back side of the semiconductor substrate 10 onto the top surface of the semiconductor substrate 10. The collector area 22 will be described later. The transistor section 70 includes a transistor such as an IGBT.

The diode section 80 is a region obtained by projecting a cathode region 82 provided on the back surface of the semiconductor substrate 10 onto the top surface of the semiconductor substrate 10 . Cathode region 82 has a first conductivity type. The cathode region 82 in this example is of N+ type, for example. The diode section 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10 .

In FIG. 1A, a region around the chip end, which is the edge side of the semiconductor device 100, is shown, and other regions are omitted. For example, an edge termination structure may be provided in the negative side region in the Y-axis direction of the semiconductor device 100 of this example. The edge termination structure alleviates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure includes, for example, a guard ring, a field plate, a resurf, or a combination thereof. Note that in this example, for convenience, the edge on the negative side in the Y-axis direction will be described, but the same applies to other edges of the semiconductor device 100.

The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, or the like. The semiconductor substrate 10 of this example is a silicon substrate.

The semiconductor device 100 of this example includes, on the front surface 21 of the semiconductor substrate 10, a gate trench section 40, a dummy trench section 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17. Equipped with. The front surface 21 will be described later. Further, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

Emitter electrode 52 is provided above gate trench section 40 , dummy trench section 30 , emitter region 12 , base region 14 , contact region 15 , and well region 17 . Further, the gate metal layer 50 is provided above the gate trench portion 40 and the well region 17.

Emitter electrode 52 and gate metal layer 50 are formed of a material containing metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al) or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 is made of a metal such as aluminum (Al), or a metal such as aluminum-silicon alloy (AlSi), aluminum-silicon-copper alloy (AlSiCu), or aluminum-copper alloy (AlCu). May be formed of an alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal made of titanium, a titanium compound, cobalt, a cobalt compound, nickel, a nickel compound, etc. below a region made of aluminum or the like. Emitter electrode 52 and gate metal layer 50 are provided separately from each other.

Emitter electrode 52 and gate metal layer 50 are provided above semiconductor substrate 10 with interlayer insulating film 38 in between. The interlayer insulating film 38 is omitted in FIG. 1A. A contact hole 54, a contact hole 55, and a contact hole 56 are provided through the interlayer insulating film 38.

Contact hole 55 connects gate metal layer 50 and a gate conductive portion within transistor section 70 . A plug made of tungsten or the like may be formed inside the contact hole 55.

The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion within the dummy trench portion 30 . A plug made of tungsten or the like may be formed inside the contact hole 56.

The connecting portion 25 electrically connects the front surface electrode such as the emitter electrode 52 or the gate metal layer 50 and the semiconductor substrate 10 . In one example, connection portion 25 is provided between gate metal layer 50 and gate conductive portion. The connecting portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. The connection portion 25 in this example is polysilicon (N+) doped with N-type impurities. The connecting portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portion 40 of this example includes two extending portions 41 that extend along a stretching direction (Y-axis direction in this example) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction. It may have a connecting portion 43 that connects the two extending portions 41.

It is preferable that at least a portion of the connecting portion 43 is formed in a curved shape. By connecting the ends of the two extended portions 41 of the gate trench portion 40, electric field concentration at the end portions of the extended portions 41 can be alleviated. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

The dummy trench section 30 is a trench section electrically connected to the emitter electrode 52. Like the gate trench section 40, the dummy trench sections 30 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The dummy trench section 30 of this example may have a U-shape on the front surface 21 of the semiconductor substrate 10, similarly to the gate trench section 40. That is, the dummy trench portion 30 may have two extending portions 31 extending along the extending direction and a connecting portion 33 connecting the two extending portions 31.

The transistor section 70 of this example has a structure in which two gate trench sections 40 and three dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 of this example has the gate trench section 40 and the dummy trench section 30 at a ratio of 2:3. For example, the transistor section 70 has one extended portion 31 between two extended portions 41 . Further, the transistor section 70 has two extended portions 31 adjacent to the gate trench section 40 .

However, the ratio of the gate trench section 40 to the dummy trench section 30 is not limited to this example. The ratio of the gate trench section 40 to the dummy trench section 30 may be 1:1 or 2:4. Further, the transistor section 70 may have all the trench sections as the gate trench section 40 and may not have the dummy trench section 30.

The well region 17 is a second conductivity type region provided closer to the front surface 21 of the semiconductor substrate 10 than a drift region 18 described later. The well region 17 is an example of a well region provided on the edge side of the semiconductor device 100. The well region 17 is, for example, P-type. The well region 17 is formed in a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench section 40 and the dummy trench section 30. Some regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 17 . The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extending direction may be covered with the well region 17 .

Contact hole 54 is formed above emitter region 12 and contact region 15 in transistor section 70 . Contact hole 54 is not provided above well region 17 provided at both ends in the Y-axis direction. In this way, one or more contact holes 54 are formed in the interlayer insulating film. One or more contact holes 54 may be provided extending in the stretching direction.

Contact hole 54 is provided above first conductivity type region 11 in diode section 80 . Contact hole 54 is provided above contact region 15 at boundary portion 90 . None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction.

The mesa portion 71 is a mesa portion provided adjacent to the trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10 . The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and is a portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. good. The extending portion of each trench portion may be one trench portion. That is, the area sandwiched between the two extended parts may be used as the mesa part.

Mesa portion 71 is provided adjacent to at least one of dummy trench portion 30 and gate trench portion 40 in transistor portion 70 . Mesa portion 71 includes well region 17 , emitter region 12 , base region 14 , and contact region 15 on front surface 21 of semiconductor substrate 10 . In mesa portion 71, emitter regions 12 and contact regions 15 are provided alternately in the extending direction.

The base region 14 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10 . The base region 14 is, for example, P-type. The base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 at both ends of the mesa portion 71 in the Y-axis direction. Note that FIG. 1A shows only one end of the base region 14 in the Y-axis direction.

The emitter region 12 is provided on the front surface 21 of the semiconductor substrate 10 and has a higher doping concentration than the first conductivity type region 11. Emitter region 12 is a region of a first conductivity type that has a higher doping concentration than drift region 18 . The emitter region 12 in this example is of N+ type, for example. An example of a dopant in emitter region 12 is arsenic (As). Emitter region 12 is provided on front surface 21 of mesa portion 71 in contact with gate trench portion 40 . The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. Emitter region 12 is also provided below contact hole 54 .

Further, the emitter region 12 may or may not be in contact with the dummy trench portion 30. The emitter region 12 in this example is in contact with the dummy trench section 30.

Contact region 15 is a second conductivity type region having a higher doping concentration than base region 14 . The contact region 15 in this example is of P+ type, for example. The contact region 15 in this example is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions with the mesa portion 71 in between to the other. The contact region 15 may or may not be in contact with the gate trench section 40 or the dummy trench section 30. Contact region 15 in this example contacts dummy trench section 30 and gate trench section 40 . Contact region 15 is also provided below contact hole 54 .

The boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80. Boundary portion 90 may not include emitter region 12. In one example, the trench portion of the boundary portion 90 is the dummy trench portion 30. The boundary portion 90 in this example is arranged such that both ends thereof in the X-axis direction serve as the dummy trench portions 30 .

The mesa portion 91 is provided at the boundary portion 90. Mesa portion 91 has contact region 15 on front surface 21 of semiconductor substrate 10 . The mesa portion 91 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

The mesa portion 81 is provided in a region of the diode portion 80 sandwiched between adjacent dummy trench portions 30 . The mesa portion 81 has a first conductivity type region 11 on the front surface 21 of the semiconductor substrate 10 . The mesa portion 81 of this example has the base region 14 and the well region 17 on the negative side in the Y-axis direction.

The first conductivity type region 11 is provided on the front surface 21 of the semiconductor substrate 10 . The first conductivity type region 11 has a first conductivity type. The first conductivity type region 11 in this example forms a Schottky junction with the emitter electrode 52 . The first conductivity type region 11 has a doping concentration that allows a Schottky junction with the emitter electrode 52. The doping concentration of the first conductivity type region 11 may be 1E12 cm ^-3 or more and 2E14 cm ^-3 or less. The first conductivity type region 11 may be a drift region 18 .

The emitter electrode 52 forms a Schottky junction with the first conductivity type region 11 provided in the mesa portion between the plurality of trench portions. The emitter electrode 52 in this example forms a Schottky junction with the first conductivity type region 11 provided in the mesa portion 81 .

Although the first conductivity type region 11 in this example is provided in the mesa portion 81, it may be provided in the mesa portion 91. Although the emitter region 12 is provided in the mesa portion 71, it may not be provided in the mesa portion 81 and the mesa portion 91. Although the contact region 15 is provided in the mesa portion 71 and the mesa portion 91, it may not be provided in the mesa portion 81.

FIG. 1B shows an example of the aa' cross section in FIG. 1A. The aa' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70. The semiconductor device 100 of this example includes a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the aa' cross section. Emitter electrode 52 is formed above semiconductor substrate 10 and interlayer insulating film 38 .

Drift region 18 is a first conductivity type region provided in semiconductor substrate 10 . The drift region 18 in this example is of N-- type, for example. Drift region 18 may be a region in semiconductor substrate 10 that remains without other doped regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

The buffer region 20 is located closer to the back surface 23 of the semiconductor substrate 10 than the center in the depth direction of the semiconductor substrate 10, and is located closer to the front surface 21 of the semiconductor substrate 10 than the cathode region 82 in the depth direction of the semiconductor substrate 10. This is a region of the first conductivity type provided on the side. The buffer region 20 in this example is provided closer to the back surface 23 of the semiconductor substrate 10 than the drift region 18 is. The buffer region 20 in this example is of N- type, for example. The doping concentration of buffer region 20 is higher than the doping concentration of drift region 18 . The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type.

Collector region 22 is provided below buffer region 20 in transistor section 70 . Collector region 22 is provided on back surface 23 of semiconductor substrate 10 and is a second conductivity type region having a higher doping concentration than base region 14 . The collector region 22 in this example is of P+ type, for example.

Collector electrode 24 is formed on back surface 23 of semiconductor substrate 10 . Collector electrode 24 is formed of a conductive material such as metal.

Base region 14 is a second conductivity type region provided above drift region 18 . Base region 14 may be provided below emitter region 12 . Base region 14 is provided in contact with gate trench portion 40 . The base region 14 may be provided in contact with the dummy trench section 30.

Emitter region 12 is provided between base region 14 and front surface 21 . Emitter region 12 is provided in contact with gate trench portion 40 . The emitter region 12 may or may not be in contact with the dummy trench portion 30.

The accumulation region 16 is a first conductivity type region provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18 is. The storage region 16 in this example is of N- type, for example. The storage region 16 is provided in the transistor section 70 and is not provided in the diode section 80. However, the storage region 16 may be provided in both the transistor section 70 and the diode section 80. The storage area 16 may be omitted.

The storage region 16 may be provided in contact with the gate trench portion 40 . The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. The dose of ion implantation into the storage region 16 may be 1.0E11 cm ^-2 or more and 5.0E13 cm ^-2 or less. By providing the accumulation region 16, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage of the transistor section 70 can be reduced. Note that E means a power of 10, and for example, 1.0E12 cm ⁻² means 1.0×10 ¹² cm ⁻² . A profile obtained by implanting multiple times may be applied by changing the implantation energy, or a profile broad in the depth direction may be applied to the trench groove by oblique rotational implantation.

One or more gate trench sections 40 and one or more dummy trench sections 30 are provided on the front surface 21. Each trench portion is provided from the front surface 21 to the drift region 18. In a region where at least one of emitter region 12, base region 14, contact region 15, and storage region 16 is provided, each trench portion also passes through these regions and reaches drift region 18. The trench portion penetrating the doping region is not limited to manufacturing in the order in which the doping region is formed and then the trench portion is formed. A structure in which a doping region is formed between the trench sections after the trench section is formed is also included in the structure in which the trench section penetrates the doping region.

The gate trench portion 40 includes a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench and inside the gate insulating film 42 . The gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10. Gate conductive portion 44 is formed of a conductive material such as polysilicon. Gate trench portion 40 is covered with interlayer insulating film 38 on front surface 21 .

The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side with the gate insulating film 42 in between in the depth direction of the semiconductor substrate 10 . When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that is in contact with the gate trench.

The dummy trench section 30 may have the same structure as the gate trench section 40. The dummy trench section 30 includes a dummy trench formed on the front surface 21 side, a dummy insulating film 32, and a dummy conductive section 34. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and inside the dummy insulating film 32 . The dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10. The dummy trench portion 30 is covered with an interlayer insulating film 38 on the front surface 21 .

The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Similarly, the contact hole 55 and the contact hole 56 may be provided to penetrate the interlayer insulating film 38.

Emitter electrode 52 is provided above semiconductor substrate 10 and has a Schottky junction with first conductivity type region 11 . Emitter electrode 52 is an example of a Schottky junction electrode. The emitter electrode 52 forms a Schottky junction with the first conductivity type region 11 provided in the mesa portion between the plurality of trench portions. In this example, the plurality of trench portions at both ends of the mesa portion that is Schottky-connected to the Schottky junction electrode are set to the potential of the Schottky junction electrode. The potential of the Schottky junction electrode may be an emitter potential. In this example, the dummy trench sections 30 at both ends of the mesa section 81 are set to the emitter potential. The dummy trench portions 30 at both ends of the mesa portion 91 may be set to an emitter potential.

The first lifetime control region 151 is a region in which a lifetime killer is intentionally formed by implanting impurities into the semiconductor substrate 10 or the like. In one example, the first lifetime control region 151 is formed by implanting helium into the semiconductor substrate 10. By providing the first lifetime control region 151, it is possible to reduce turn-off time and suppress tail current, thereby reducing loss during switching.

Lifetime killers are career recombination centers. The lifetime killer may be a lattice defect. For example, the lifetime killer may be a vacancy, a double vacancy, a composite defect of these and an element constituting the semiconductor substrate 10, or a dislocation. Further, the lifetime killer may be a rare gas element such as helium or neon, or a metal element such as platinum. Electron beams may be used to form lattice defects.

The lifetime killer concentration is the recombination center concentration of carriers. The lifetime killer concentration may be the concentration of lattice defects. For example, the lifetime killer concentration may be the concentration of vacancies such as vacancies and double vacancies, the composite defect concentration of these vacancies and elements constituting the semiconductor substrate 10, or the concentration of dislocations. It's good to be there. Further, the lifetime killer concentration may be a chemical concentration of a rare gas element such as helium or neon, or a chemical concentration of a metal element such as platinum.

The first lifetime control region 151 is provided closer to the back surface 23 than the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10 . The first lifetime control area 151 in this example is provided in the buffer area 20. The first lifetime control region 151 of this example is provided on the entire surface of the semiconductor substrate 10 in the XY plane, and can be formed without using a mask. The first lifetime control region 151 may be provided in a part of the semiconductor substrate 10 in the XY plane. The dose of impurities for forming the first lifetime control region 151 may be 0.5E10 cm ^-2 or more and 1.0E13 cm -2 or less, or 5.0E10 cm ^{-2 or} more and 5.0E11 cm ^-2 or less. There may be.

Further, the first lifetime control region 151 in this example is formed by injection from the back surface 23 side. Thereby, the influence on the front surface 21 side of the semiconductor device 100 can be avoided. For example, the first lifetime control region 151 is formed by irradiating helium from the back surface 23 side. Here, whether the first lifetime control region 151 is formed by injection from the front surface 21 side or from the back surface 23 side can be determined by the SR method or leakage current measurement. This can be determined by acquiring the state of the face 21 side.

Contact region 15 is provided above base region 14 in mesa portion 91 . Contact region 15 is provided in mesa portion 91 in contact with dummy trench portion 30 . In other cross sections, the contact region 15 may be provided on the front surface 21 of the mesa portion 71.

The first conductivity type region 11 is provided above the cathode region 82 in the semiconductor substrate 10 . The first conductivity type region 11 in this example is a drift region 18 extending to the front surface 21 of the semiconductor substrate 10 . Although the first conductivity type region 11 in this example is the drift region 18, it may be a region different from the drift region 18. That is, the first conductivity type region 11 may have a different doping concentration than the drift region 18.

The first conductivity type region 11 may be provided in the mesa portion 81 so as to extend from one trench portion to the other adjacent trench portion. The first conductivity type region 11 may be provided extending from one trench portion to the other adjacent trench portion on the front surface 21 . The mesa portion 81 provided with the first conductivity type region 11 does not need to be provided with the emitter region 12, the contact region 15, and the storage region 16.

Cathode region 82 is provided on back surface 23 of semiconductor substrate 10 . Cathode region 82 is provided below buffer region 20 in diode section 80 . The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is provided below the boundary portion 90 in this example. The cathode region 82 of this example has a first cathode section 181 and a second cathode section 182.

The first cathode portion 181 is a first conductivity type region having a higher doping concentration than the first conductivity type region 11 . In one example, the first cathode section 181 is of N+ type.

The second cathode section 182 is a second conductivity type region provided adjacent to the first cathode section 181 on the back surface 23 of the semiconductor substrate 10 . That is, the second cathode section 182 may be in direct contact with the first cathode section 181. In one example, the second cathode portion 182 is of P+ type.

The doping concentration of the first cathode portion 181 may be greater than or equal to 1E13 cm ^-3 and less than or equal to 1E20 cm ^-3 . The doping concentration of the second cathode portion 182 may be greater than or equal to 1E13 cm ^-3 and less than or equal to 1E18 cm ^-3 . The first cathode part 181 may be formed by ion-implanting a P-type dopant in an ion implantation process for forming the second cathode part 182 and then counter-implanting it with an N-type dopant. On the other hand, the second cathode part 182 may be formed by ion-implanting an N-type dopant during the ion implantation process for forming the first cathode part 181 and then counter-implanting the ion-implant with a P-type dopant.

The first cathode part 181 and the second cathode part 182 are arranged so as to form a boundary in contact with each other. The first cathode section 181 and the second cathode section 182 may be arranged alternately in any direction. The first cathode portions 181 and the second cathode portions 182 of this example are arranged alternately in the trench arrangement direction (for example, the X-axis direction), but are alternately arranged in the trench extension direction (for example, the Y-axis direction). Good too. The first cathode section 181 and the second cathode section 182 may be arranged in a stripe shape when viewed from above. One of the first cathode section 181 and the second cathode section 182 may be formed in a dot shape.

The first cathode portions 181 and the second cathode portions 182 are alternately provided on the back surface 23 of the semiconductor substrate 10 at a predetermined pitch P1. The pitch P1 is between the center of the first cathode part 181 in the repeating direction of the first cathode part 181 and the second cathode part 182 (in this example, the X-axis direction) and the repeating direction of the first cathode part 181 and the second cathode part 182. This is the distance from the center of the second cathode section 182 in the X-axis direction (in this example). The first cathode portion 181 and the second cathode portion 182 are different from the X-axis direction. The pitch P1 in this example is 0.5 μm or more and 50.0 μm or less.

The trench depth Dt is the depth from the front surface 21 to the lower end of the trench portion. The trench depth Dt may be the same or different between the dummy trench section 30 and the gate trench section 40. In one example, the trench depth Dt is 5 μm.

The mesa width Wm is the width of the mesa portion in the trench arrangement direction. The mesa width Wm may be the same or different in the mesa portion 71, the mesa portion 81, and the mesa portion 91. In one example, the mesa width Wm is 1 μm.

The trench depth Dt and the mesa width Wm may satisfy Dt/Wm≧2. The trench depth Dt and the mesa width Wm may satisfy Dt/Wm≧5. By increasing the ratio of the trench depth Dt to the mesa width Wm, the breakdown voltage of the diode section 80 having a Schottky junction can be improved, as will be described later.

The first lifetime control region 151 is provided in both the transistor section 70 and the diode section 80. Thereby, the semiconductor device 100 of this example can speed up recovery in the diode section 80 and further reduce switching loss.

The second lifetime control region 152 is provided closer to the front surface 21 than the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10 . The second lifetime control area 152 in this example is provided in the drift area 18. The second lifetime control region 152 is provided in both the transistor section 70 and the diode section 80. The second lifetime control region 152 may be formed by implanting impurities from the front surface 21 side, or may be formed by implanting impurities from the back surface 23 side. The second lifetime control region 152 is provided at the diode section 80 and the boundary section 90, and may not be provided at a part of the transistor section 70.

The second lifetime control region 152 may be formed by any method among the methods for forming the first lifetime control region 151. The elements, doses, etc. for forming the first lifetime control region 151 and the second lifetime control region 152 may be the same or different.

The semiconductor device 100 of this example can reduce the anode peak current and shorten the reverse recovery time. Thereby, diode loss Err can be reduced.

FIG. 2A is a top view of a modification of the semiconductor device 100. The semiconductor device 100 of this example has a structure of the boundary portion 90 that is different from the example of FIG. 1A. In this example, points that are different from the example shown in FIG. 1A will be particularly explained.

The boundary portion 90 has a first conductivity type region 11 on the front surface 21 of the semiconductor substrate 10 . The first conductivity type region 11 in this example is the drift region 18.

The diode section 80 of this example has a plurality of gate trench sections 40. All trench portions of the diode portion 80 may be the gate trench portions 40. The diode section 80 of this example has a dummy trench section 30 near the boundary section 90.

A gate trench portion 40 set to the gate potential may be provided at both ends of the mesa portion 81 that is in Schottky contact with the emitter electrode 52 . By providing the gate trench portion 40 in the diode portion 80, as will be described later, it is possible to suppress an increase in potential energy near the Schottky junction and improve the reverse recovery breakdown voltage of the Schottky barrier diode.

FIG. 2B shows a bb' cross section of a modified example of the semiconductor device 100. The bb' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70. In this example, points that are different from the example shown in FIG. 1B will be particularly explained.

The boundary portion 90 includes a first conductivity type region 11 on the front surface 21 . The diode section 80 may include a first cathode section 181 on the back surface 23 corresponding to the mesa section 81 adjacent to the mesa section 91 . That is, the collector region 22 may be adjacent to the first cathode section 181. However, the collector region 22 may be adjacent to the second cathode section 182. The collector region 22 below the boundary portion 90 may be provided adjacent to the first cathode portion 181 . That is, the collector region 22 below the boundary portion 90 may be in direct contact with the first cathode portion 181.

The first conductivity type region 11 in this example is sandwiched between a plurality of adjacent gate trench sections 40 . The first conductivity type region 11 may be provided extending from one gate trench section 40 to the other gate trench section 40 in the mesa section 81 .

FIG. 3 is a top view of a modification of the semiconductor device 100. The semiconductor device 100 of this example includes a diode section 80 but does not include a transistor section 70. The diode section 80 of this example includes a plurality of dummy trench sections 30, but may also include a gate trench section 40. The semiconductor device 100 of this example includes an anode electrode 53 as a Schottky junction electrode. The dummy trench portion 30 may be set to an anode potential as the potential of the Schottky junction electrode.

The anode electrode 53 is formed of a material containing metal. At least a part of the anode electrode 53 is made of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi), aluminum-silicon-copper alloy (AlSiCu), or aluminum-copper alloy (AlCu). It may be formed by The anode electrode 53 may have a barrier metal made of titanium, a titanium compound, cobalt, a cobalt compound, nickel, a nickel compound, etc. below a region made of aluminum or the like.

FIG. 4 is a cross-sectional view of a semiconductor device 500 according to a comparative example. The semiconductor device 500 includes a PN diode section 580. The PN diode section 580 has an anode region 510 on the front surface 21 and a cathode region 520 and an N- type region 530 on the back surface 23. In order to speed up the forward flow of the diode in the PN diode section 580, it is necessary to form an anode region 510 with a lower concentration, but it is not possible to achieve a sufficiently low doping concentration by simply controlling the ion implantation conditions. may be difficult.

FIG. 5A shows an example of a voltage waveform of the diode section 80. This example shows the voltage waveform of the diode section 80 when the transistor section 70 is turned on. The vertical axis indicates the forward voltage VA [V] of the diode section 80, and the horizontal axis indicates time [s].

FIG. 5B shows an example of a current waveform of the diode section 80. The vertical axis indicates forward current IA [A] of the diode section 80, and the horizontal axis indicates time [s]. This example shows the current waveform of the diode section 80 when the transistor section 70 is turned on.

PND1 is a PN diode having a predetermined diode area A. PND1 has an RFC structure with pitch P1 of 5 μm. The RFC structure refers to a structure having an N-type cathode portion and a P-type cathode portion in the cathode region.

SBD1 is a Schottky barrier diode whose diode area is smaller than that of PND1. For example, the diode area of SBD1 is 0.004A. The SBD1 has an RFC structure with a pitch P1 of 5 μm.

SBD2 is a Schottky barrier diode with a smaller diode area than PND1, but has a non-RFC structure. A diode with a non-RFC structure does not have a P-type region in the cathode region, but has an N-type region over the entire surface. The diode area of SBD2 is 0.004A, which is the same as SBD1.

In either example, the slopes of the voltage waveforms in FIG. 5A are adjusted to be substantially the same, and the current waveforms corresponding to the conditions are shown in FIG. 5B. With a Schottky barrier diode, even if the diode area is smaller than that of a PN diode, it is possible to obtain an IV waveform equivalent to that of a PN diode. That is, the Schottky barrier diode allows the same current to flow through a smaller diode area than the PN diode.

FIG. 6A is a linear scale graph showing the electrical characteristics of a PN diode. FIG. 6B is a graph on a logarithmic scale showing the electrical characteristics of a PN diode. The vertical axis indicates forward current IA, and the horizontal axis indicates forward voltage VA [V].

PND1 has an RFC structure with pitch P1 of 5 μm. PND2 has an RFC structure with pitch P1 of 50 μm. PND3 is a diode with non-RFC structure. PND1 and PND2 have an RFC structure, and have improved current rise than PND3, which has a non-RFC structure. PND1 can suppress the current at high current by making the pitch of the RFC structure smaller than that of PND2.

Since the diode section has an RFC structure, more current can flow due to the PNP bipolar effect than in the case of a non-RFC structure. Furthermore, the current rise is improved due to the effect of the PNP bipolar RFC structure. Since the diode section has an RFC structure, it is possible to increase the series resistance and suppress the current at high current times. By narrowing the pitch P1 of the RFC structure, series resistance can be increased and current flowing at high current times can be suppressed. As the pitch P1 of the RFC structure becomes narrower, the region where a depletion layer is formed at the PN boundary becomes larger, and thus the series resistance of the diode section becomes larger.

FIG. 7A is a diagram showing a current waveform during reverse recovery of a PN diode. In this example, the current waveforms of the diodes PND1 to PND3 are compared. PND1 to PND3 have the same predetermined diode area A. The conditions for PND1 to PND3 may be the same as the conditions for PND1 to PND3 shown in FIGS. 6A and 6B.

PND1 and PND2 can suppress anode peak current by having an RFC structure. Moreover, by making the pitch P1 of the RFC structure smaller than that of PND2, PND1 can increase series resistance and further suppress anode peak current. This makes it possible to shorten the reverse recovery time of the diode section and reduce diode loss Err.

FIG. 7B is a diagram showing a voltage waveform during reverse recovery of the PN diode. In this example, the current waveforms of the diodes PND1 to PND3 are compared. PND1 to PND3 have the same predetermined diode area A.

Since PND1 and PND2 have an RFC structure, the forward voltage of the diode portion can be changed in a shorter time. Further, in PND1, by making the pitch P1 of the RFC structure smaller than in PND2, the forward voltage of the diode portion can be changed in a shorter time. By providing the RFC structure with the small pitch P1 in this way, it is possible to shorten the reverse recovery time of the diode section and reduce the diode loss Err.

FIG. 8 is a graph showing the potential energy of the diode section 80. The diode section 80 of this example has the gate trench section 40.

The solid line indicates the distribution of potential energy at the center of the mesa portion 81 sandwiched between the gate trench portions 40. The center of the mesa portion 81 may be the center of the mesa portion 81 in the trench arrangement direction (ie, the X-axis direction). The broken line indicates the distribution of potential energy at the center of the gate trench portion 40. The center of the gate trench portion 40 may be the center of the gate trench portion 40 in the trench arrangement direction (namely, the X-axis direction). In the mesa portion 81 sandwiched between the gate trench portions 40, even if a voltage is applied to the cathode electrode, there is little influence on the Schottky junction portion of the diode portion 80. Thereby, it is possible to suppress an increase in potential energy near the Schottky junction and improve the reverse recovery withstand voltage of the diode section 80.

FIG. 9 shows the breakdown voltage of a Schottky barrier diode as a comparative example. The diode section of this example does not have multiple trench sections. Therefore, the Schottky barrier diode of the comparative example has a low breakdown voltage of 10 V or less due to the influence of the voltage applied by the cathode electrode.

FIG. 10 shows the withstand voltage of the Schottky barrier diode of the example. The Schottky barrier diode of this example has a Schottky junction in a mesa section sandwiched between a plurality of gate trench sections 40. As a result, it has a higher breakdown voltage than the comparative example shown in FIG. The Schottky barrier diode of this example may have a breakdown voltage of 1000V or more.

FIG. 11 is a diagram showing the dependence of the breakdown voltage of the diode section 80 on the mesa width. The vertical axis shows forward current, and the horizontal axis shows forward voltage. In the four embodiments, the trench depth to mesa width ratio Dt/Wm is different. This example shows simulation results using four types of conditions: Dt/Wm=1.375, Dt/Wm=2.75, Dt/Wm=5, and Dt/Wm=11.

In any of the embodiments, by having a Schottky junction sandwiched between a plurality of gate trench sections 40, the reverse breakdown voltage characteristics can be improved. By setting Dt/Wm to 2 or more, leakage current can be suppressed while maintaining breakdown voltage. Further, by setting Dt/Wm to 5 or more, it is possible to further suppress leakage current and improve breakdown voltage.

As described above, by including the Schottky barrier diode whose barrier barrier is smaller than that of the PN diode, the semiconductor device 100 can improve the forward flow of the diode and speed up the forward bias operation. Furthermore, by having the RFC structure, the semiconductor device 100 can reduce the anode peak current and suppress switching loss.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the range described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the embodiments described above. It is clear from the claims that such modifications or improvements may be included within the technical scope of the present invention.

The order of execution of each process, such as the operation, procedure, step, and stage in the apparatus, system, program, and method shown in the claims, specification, and drawings, is specifically defined as "before" or "before". It should be noted that they can be implemented in any order unless the output of the previous process is used in the subsequent process. Even if the claims, specifications, and operational flows in the drawings are explained using "first," "next," etc. for convenience, this does not mean that it is essential to carry out the operations in this order. It's not a thing.

DESCRIPTION OF SYMBOLS 10... Semiconductor substrate, 11... First conductivity type region, 12... Emitter region, 14... Base region, 15... Contact region, 16... Accumulation region, 17... Well Region, 18... Drift region, 20... Buffer region, 21... Front surface, 22... Collector region, 23... Back surface, 24... Collector electrode, 25... Connection 30... Dummy trench part, 31... Extension part, 32... Dummy insulating film, 33... Connection part, 34... Dummy conductive part, 38... Interlayer insulating film , 40... Gate trench portion, 41... Extension portion, 42... Gate insulating film, 43... Connection portion, 44... Gate conductive portion, 50... Gate metal layer, 52... - Emitter electrode, 53... Anode electrode, 54... Contact hole, 55... Contact hole, 56... Contact hole, 70... Transistor part, 71... Mesa part, 80... Diode part, 81... Mesa part, 82... Cathode region, 90... Boundary part, 91... Mesa part, 100... Semiconductor device, 151... First lifetime control area, 152 ... second lifetime control region, 181 ... first cathode section, 182 ... second cathode section, 500 ... semiconductor device, 510 ... anode region, 520 ... cathode region, 530 ...N-type region, 580...PN diode section

Claims (15)

A semiconductor device including a diode section,
The diode section is
a first conductivity type region provided on the front surface of the semiconductor substrate;
a Schottky junction electrode provided above the semiconductor substrate and Schottky-junctioned with the first conductivity type region;
a plurality of trench portions provided on the front surface of the semiconductor substrate;
Equipped with
The Schottky junction electrode makes a Schottky junction with the first conductivity type region provided in a mesa section between the plurality of trench sections,
A semiconductor device in which a trench depth Dt of the plurality of trench portions and a mesa width Wm of a mesa portion between the plurality of trench portions satisfy Dt/Wm≧2. comprising a cathode region provided on the back surface of the semiconductor substrate,
The cathode region is
a first cathode portion of a first conductivity type having a higher doping concentration than the first conductivity type region;
a second cathode portion of a second conductivity type provided adjacent to the first cathode portion on the back surface of the semiconductor substrate;
The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the doping concentration of the first conductivity type region is 1E12 cm ^-3 or more and 2E14 cm ^-3 or less. The semiconductor substrate includes a first conductivity type drift region provided above the cathode region,
The semiconductor device according to claim 2, wherein the first conductivity type region is the drift region provided extending to the front surface of the semiconductor substrate. The semiconductor device according to claim 2, wherein the doping concentration of the first cathode portion is 1E13 cm ^-3 or more and 1E20 cm ^-3 or less. The semiconductor device according to claim 2, wherein the doping concentration of the second cathode portion is 1E13 cm ^-3 or more and 1E18 cm ^-3 or less. The first cathode portion and the second cathode portion are provided alternately at a predetermined pitch on the back surface of the semiconductor substrate,
The semiconductor device according to claim 2, wherein a pitch between the first cathode portion and the second cathode portion is 0.5 μm or more and 50.0 μm or less. 3 . The semiconductor device according to claim 1 , wherein the plurality of trench portions at both ends of the mesa portion that are Schottky-connected to the Schottky junction electrode are set to the potential of the Schottky junction electrode. The semiconductor device according to claim 1 , wherein the plurality of trench portions at both ends of the mesa portion that are Schottky-junctioned with the Schottky junction electrode are set to a gate potential. A groove provided on the back surface side of the semiconductor substrate with respect to the center in the depth direction of the semiconductor substrate, and on the front surface side of the semiconductor substrate rather than the cathode region in the depth direction of the semiconductor substrate. The semiconductor device according to claim 2, comprising a buffer region of one conductivity type. Equipped with a transistor section,
The transistor section includes:
an emitter region of a first conductivity type provided on the front surface of the semiconductor substrate and having a higher doping concentration than the first conductivity type region;
a base region of a second conductivity type provided below the emitter region;
The semiconductor device according to claim 2 , further comprising a second conductivity type collector region provided on the back surface of the semiconductor substrate and having a higher doping concentration than the base region. The semiconductor device according to claim 11, wherein the transistor section and the diode section each include a plurality of trench sections on the front surface of the semiconductor substrate. The transistor section includes a boundary section adjacent to the diode section,
The semiconductor device according to claim 11 , wherein the boundary portion includes a second conductivity type contact region having a higher doping concentration than the base region on the front surface of the semiconductor substrate. The transistor section includes a boundary section adjacent to the diode section,
The semiconductor device according to claim 11 , wherein the boundary portion has the first conductivity type region on the front surface of the semiconductor substrate. The semiconductor device according to claim 14, wherein the collector region below the boundary portion is provided adjacent to the first cathode portion.

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