CN111627983A - Groove type SiC device - Google Patents
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- CN111627983A CN111627983A CN202010472712.9A CN202010472712A CN111627983A CN 111627983 A CN111627983 A CN 111627983A CN 202010472712 A CN202010472712 A CN 202010472712A CN 111627983 A CN111627983 A CN 111627983A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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Abstract
The invention relates to the technical field of semiconductors, in particular to a groove type SiC device. In the groove type SiC device, a gate electrode is arranged on the side wall in the groove; disposing a source electrode at a center within the trench; a p + region is arranged at the bottom of the groove; the gate electrode at the inner side wall of the groove is isolated from the source electrode at the center in the groove through a medium; the source electrode at the center in the groove is electrically connected with the source electrode on the table top; and the p + region at the bottom of the groove is electrically connected with the source electrode at the center in the groove. And a p + region is arranged at the bottom of the groove and electrically connected with the source electrode. The p + region at the bottom of the groove can effectively shield an electric field at the position of the gate dielectric, so that the reliability of the gate dielectric can be improved, and the gate-drain capacitance can be reduced. The p + region is electrically connected with the source electrode, so that an avalanche current loop can be well provided, and the avalanche capability of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a groove type SiC device.
Background
At present, the cell density of the trench MOSFET can be made larger than that of the planar structure SiC MOSFET, and the channel of the trench MOSFET is on crystal planes perpendicular to the (0001) plane, such as (11-20) planes, which have higher channel mobility than the (0001) plane, compared to the high resistance due to the low channel mobility of the planar structure MOSFET in the (0001) plane, i.e., the silicon plane. Therefore, the trench MOSFET exhibits a lower specific on-resistance and a higher current density than the planar MOSFET, and is considered as a structure of a next-generation SiC MOSFET.
A conventional trench SiC MOSFET device structure is shown in fig. 1. A gate electrode is disposed within the trench. The p-base region and the medium on the side wall form an MOS gate structure, and when the gate voltage is greater than the threshold voltage, the p-base region on the side wall is inverted to form a conductive channel. However, electric field concentration is easily formed at the bottom of the gate trench, particularly at the point a, due to SiO near the interface2The medium electric field is about 3 times that of SiC, and the critical electric field of SiC is about 10 times that of silicon, so reliability problems are more likely to occur in SiC devices. How to avoid electric field concentration at the bottom of the gate trench is an important issue.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a groove type SiC device and a manufacturing method thereof, which aim to solve the technical problems in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a groove type SiC device.A gate electrode is arranged on the side wall in a groove; disposing a source electrode at a center within the trench; a p + region is arranged at the bottom of the groove; the gate electrode at the inner side wall of the groove is isolated from the source electrode at the center in the groove through a medium; the source electrode at the center in the groove is electrically connected with the source electrode on the table top; and the p + region at the bottom of the groove is electrically connected with the source electrode at the center in the groove.
As a further technical scheme, the device sequentially comprises the following components from bottom to top: the n + SiC substrate, the n + buffer layer, the n-drift layer, the n JFET layer and the P layer; respectively implanting ions at intervals into the P layer active region to form an n + region and a P + region on the mesa, wherein the depth of the P + region on the mesa is greater than that of the n + region and the P + region is electrically connected with the P base region; and etching the P layer to form a U-shaped groove, forming a P + region at the bottom of the groove through ion implantation, and forming a conductive JFET (junction field effect transistor) region between the P + regions at the bottom of the groove below the P base region.
As a further technical scheme, a p + region is arranged in the whole region of the bottom of the groove; and forming an ohmic contact above the p + region at the bottom of the groove and electrically connected with the source electrode at the center in the groove.
As a further technical scheme, a p + region is formed around the bottom of the trench, and an n region is formed in the center of the bottom of the trench; forming an ohmic contact above the p + region at the bottom of the trench; a schottky contact is formed at the bottom of the trench over the n-region while making an electrical connection to the source electrode at the center within the trench.
As a further technical scheme, the side wall in the groove is provided with a gate medium.
As a further technical solution, an interlayer dielectric is disposed between the gate electrode at the inner side wall of the trench and the source electrode at the center in the trench, and the cross section of the interlayer dielectric is an elbow shape.
As a further technical scheme, the thickness of the interlayer medium is not less than 0.2 um.
As a further technical scheme, ohmic contacts are formed above the p + region and the n + region on the table-board and are electrically connected with the source electrode on the table-board.
As a further technical scheme, the depth of the n + region on the table top is larger than 0.2um, and the depth of the p + region on the table top is larger than the n + region.
As a further technical scheme, the doping concentration of the p + region at the bottom of the trench is more than 1e18cm-3。
By adopting the technical scheme, the invention has the following beneficial effects:
the invention provides a groove type SiC device, wherein a gate electrode is arranged on the side wall in a groove, a source electrode is arranged at the center of the groove, the gate and the source are isolated by a medium, and the source electrode is electrically connected with the source electrode on a table board. And a p + region is arranged at the bottom of the groove and electrically connected with the source electrode. The p + region at the bottom of the groove can effectively shield an electric field at the position of the gate dielectric, so that the reliability of the gate dielectric can be improved, and the gate-drain capacitance can be reduced. The p + region is electrically connected with the source electrode, so that an avalanche current loop can be well provided, and the avalanche capability of the device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic structural diagram of a conventional trench type SiC MOSFET device;
fig. 2 is a trench structure SiC MOSFET device provided by an embodiment of the present invention;
fig. 3 is a trench structure SiC MOSFET device for an integrated schottky diode according to another embodiment of the present invention;
fig. 4 is a schematic structural diagram of a SiC epitaxial material structure provided in an embodiment of the present invention;
FIG. 5 is a schematic diagram of an embodiment of the present invention providing n + and p + regions formed by partially spaced ion implantation in the active region;
FIG. 6 is a schematic diagram of bottom implantation after trench etching according to an embodiment of the present invention;
fig. 7 is a schematic diagram of polysilicon and a gate-source isolation dielectric according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of a metalized and passivated substrate according to an embodiment of the present invention.
Icon: a 1-n + SiC substrate; a 2-n + buffer layer; a 3-n-drift layer; 4-a gate electrode; a 5-n + region; a 6-p + region; a 7-p + region; 8-JFET area; 9-ohm; 10-schottky; an 11-nJFET layer; a 12-p layer; 13-a trench; a 14-p base region; 15-a gate dielectric; 16-an interlayer dielectric; 17-Pad metal; 18-Pad metal; 19-passivation layer.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation. The method of the present invention is applicable to various SiC field effect transistors such as MOSFET, IGBT, etc., and the following description will be given taking SiC MOSFET as an example.
Example one
As shown in fig. 2, the present embodiment provides a trench structure SiC MOSFET device.
The embodiment comprises an n + SiC substrate 1, an n + buffer layer 2, an n-drift layer 3, a p + buried layer, an n CS (current spreading) layer, a p base region 14 and a p + region 6/n + region 5 from bottom to top in sequence. A conductive JFET region 8 is formed between the p + regions 7 below the p-base region 14. And a gate dielectric 15, a passivation layer 19, a gate electrode, a source electrode and a bottom drain electrode on the SiC surface. The gate electrode 4 is arranged on the side wall in the groove 13, the source electrode is arranged at the center of the groove 13, the gate source and the gate source are isolated by a medium, and the source electrode in the groove 13 is electrically connected with the source electrode on the table board. The depth of the trench 13 is larger than that of the p-well, the p + region 7 is at the bottom of the trench 13, and the doping concentration is larger than 1e18cm-3And an electrical connection is made to the source through ohmic 9 contact at the bottom of trench 13. The p + region 7 can shield an electric field at the bottom of the trench 13 and also shield an electric field of the p base region 14 on the mesa, so that the p base region 14 is prevented from being penetrated.
The partial region on the mesa is a p + region 6, and the depth of the p + region 6 is not less than n + region 5 and is electrically connected with a p base region 14. And ohmic 9 contact is formed between the p + region 6 and the n + region 5, and the p + region and the n + region are connected with source metal. The p base region 14 is electrically connected to both the source and the p + region 7 at the bottom of the trench 13 by the separate p + regions 6 in these different cells, and the n + region 5 forms an electrical short with the p base region 14. The placement of the p + region 6 on the mesa in this manner, unlike conventional methods, allows the mesa size to be made smaller, i.e., greater cell density. The doping concentration of the JFET region 8 between the p + regions 7 at the bottom of the trench 13 is higher than that of the CS layer, so that the resistance at the JFET region 8 can be effectively reduced. The CS layer is deeper than the p + region.
Example two
With reference to fig. 3, a second embodiment provides a trench SiC device integrated with a schottky diode, which is another technical solution added to the first embodiment, and the technical features disclosed in the first embodiment are also applicable to the second embodiment, and the technical features disclosed in the first embodiment are not described again.
In this embodiment, the bottom of trench 13 does not form p + region 7 at all, but rather p + region 7 is formed around the center, which is still n region 5. Ohmic 9 contacts are formed over the p + regions 7 and schottky 10 contacts are formed over the n regions 5 while connecting to the source electrodes. This forms a schottky diode integrated trench SiC device.
EXAMPLE III
As shown in fig. 4, an n + buffer layer 2, an n-drift layer 3, an nJFET layer 11(nCS layer), and a p layer 12 are sequentially epitaxially grown on a conductive n + SiC substrate. The concentration thickness of the n-drift layer 3 is determined by the voltage-resistant design of the device, and the concentration is generally greater than 1e14cm-3And the thickness is more than 5 um. The thickness of the n CS layer is larger than 0.5um, and the concentration is larger than that of the drift layer. The thickness of the p-layer 12 is greater than 0.5um, and the concentration is generally between 1e15-5e17cm-3, depending on the designed gate threshold voltage.
As shown in fig. 5, n + region 5 and p + region 6 are formed by ion implantation at intervals in the active region, the ion implanted by n + may be N, P ions, and the ion implanted by p + region 6 may be Al or B ions. The depth of the n + region 5 is greater than 0.2um, the depth of the p + region 6 is greater than or equal to the depth of the n + region 5, and connection with the p base region 14 is formed. The thickness of the p layer 12 and the depth of the n + region 5 are designed such that the remaining p layer 12 forms a p-base region 14 with a thickness greater than 0.3 um.
As shown in fig. 6, the trench 13 is etched to form a U-shaped trench. The depth of trench 13 is greater than the depth of p-base region 14 to ensure the formation of a channel. Growing a dielectric layer on the whole SiC surface by isotropic method, such as LPCVD SiO2And the thickness is more than 100 nm. Anisotropic etching to remove mesa and bottom of trench 13And media, the media of the remaining sidewalls. A vertical ion implantation, such as Al, B, is performed to form p + region 7 at the bottom of trench 13. The thickness of the dielectric depends on the tilt angle of the trench 13 and the divergence angle of the ion implantation so that the sidewalls are protected from being implanted during ion implantation, protecting the performance of the channel. And removing the medium after injection and cleaning. Then high-temperature activation annealing is carried out, and sacrificial oxidation is carried out. The high temperature activation annealing and the sacrificial oxidation not only can form a smoother structure at the bottom of the trench 13, but also can remove a damage layer caused by etching on the side wall. In this step, the junction termination of the device is also etched and implanted. The junction termination structure may be a field limiting ring, JTE, or a combination of the two.
As shown in fig. 7, a gate dielectric 15 is grown by thermal oxidation. Growing SiO with a size larger than 30nm in the environment of 1100-1500 ℃ by using a dry-oxygen thermal oxidation method2Layer of NO or N2O or POCl3And (4) annealing after growth in the environment, and passivating the interface trap. And growing in-situ doped polysilicon by an LPCVD (low pressure chemical vapor deposition) method to fill the groove 13 and carrying out etching planarization. The polysilicon at the center of the trench 13 is etched and a short thermal oxidation of the polysilicon is performed. The thickness of the polysilicon electrode at the finally remained side wall is not less than 0.5 um. The interlayer dielectric 16 is grown by LPCVD to isolate the gate source electrode. The thickness of the medium is not less than 0.5 um.
As shown in fig. 8, ohmic 9 contacts are made on the mesa between the interlayer dielectric 16 at the bottom of the trench 13 and on the backside. And etching a window at the gate electrode pressing block. Electrode metal, Ti/Al, or Ti/W/Al, Ti/TiN/Al, Ti/Au, Ti/Ag, Ti/TiN/Cu, etc., is deposited to form the bulk metal of the gate and source, respectively (Pad metal 18). And thick briquetting metal is manufactured on the back surface. Finally, a passivation layer 19 is applied to the front side.
In another embodiment, ohmic 9 contact is made on the back side on the p + region 7 between the mesa and the interlayer dielectric 16 at the bottom of the trench 13, while ohmic 9 contact is not made on the n region at the center of the trench 13. And etching a window at the gate electrode pressing block. Electrode metal, Ti/Al, or Ti/W/Al, Ti/TiN/Al, Ti/Au, Ti/Ag, Ti/TiN/Cu, etc., are deposited to form the bulk metal of the gate and source, respectively, and to form the Schottky 10 contacts at the bottom of the trench 13. And performing RTA annealing treatment to improve the contact performance of the Schottky 10 at the bottom of the trench 13. The back side is coated with thick compact metal (Pad metal 17). Finally, a passivation layer 19 is applied to the front side.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A trench type SiC device is characterized in that,
providing a gate electrode at a sidewall within the trench;
disposing a source electrode at a center within the trench;
a p + region is arranged at the bottom of the groove;
the gate electrode at the inner side wall of the groove is isolated from the source electrode at the center in the groove through a medium; the source electrode at the center in the groove is electrically connected with the source electrode on the table top; and the p + region at the bottom of the groove is electrically connected with the source electrode at the center in the groove.
2. The trench SiC device of claim 1 comprising, in order from bottom to top: the n + SiC substrate, the n + buffer layer, the n-drift layer, the n JFET layer and the P layer;
respectively implanting ions at intervals into the P layer active region to form an n + region and a P + region on the mesa, wherein the depth of the P + region on the mesa is greater than that of the n + region and the P + region is electrically connected with the P base region;
and etching the P layer to form a U-shaped groove, forming a P + region at the bottom of the groove through ion implantation, and forming a conductive JFET (junction field effect transistor) region between the P + regions at the bottom of the groove below the P base region.
3. The trench SiC device of claim 1 wherein the entire area of the trench bottom is provided with a p + region; and forming an ohmic contact above the p + region at the bottom of the groove and electrically connected with the source electrode at the center in the groove.
4. The trench type SiC device of claim 1 wherein the trench bottom forms a p + region around its periphery and an n region in its center; forming an ohmic contact above the p + region at the bottom of the trench; a schottky contact is formed at the bottom of the trench over the n-region while making an electrical connection to the source electrode at the center within the trench.
5. The trench SiC device of claim 1 wherein the sidewalls within the trench are provided with a gate dielectric.
6. The trench SiC device of claim 1 wherein an interlayer dielectric is disposed between the gate electrode at the trench inner sidewall and the source electrode at the trench inner center, the interlayer dielectric having an angled cross-section.
7. The trench SiC device of claim 6 wherein the thickness of the interlayer dielectric is not less than 0.2 um.
8. The trench SiC device of claim 1 wherein ohmic contacts are formed over the p + and n + regions on the mesa to make electrical connection to the source electrode on the mesa.
9. The trench SiC device of claim 1 wherein the n + region on the mesa has a depth greater than 0.2um and the p + region on the mesa has a depth greater than the n + region.
10. The trench type SiC device of claim 1 wherein the p + region at the bottom of the trench has a doping concentration greater than 1e18cm-3。
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023110988A1 (en) * | 2021-12-15 | 2023-06-22 | Robert Bosch Gmbh | Method for producing a power finfet, and power finfet |
| WO2023165242A1 (en) * | 2022-03-02 | 2023-09-07 | 华为数字能源技术有限公司 | Sic mosfet and preparation method therefor, and integrated circuit |
Citations (4)
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| WO2023165242A1 (en) * | 2022-03-02 | 2023-09-07 | 华为数字能源技术有限公司 | Sic mosfet and preparation method therefor, and integrated circuit |
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