CN217086575U

CN217086575U - Silicon carbide groove type MOSFET

Info

Publication number: CN217086575U
Application number: CN202220388695.5U
Authority: CN
Inventors: 王中健; 曹远迎
Original assignee: Chengdu Gongcheng Semiconductor Co ltd
Current assignee: Chengdu Gongcheng Semiconductor Co ltd
Priority date: 2022-02-25
Filing date: 2022-02-25
Publication date: 2022-07-29
Anticipated expiration: 2032-02-25

Abstract

The utility model discloses a carborundum slot type MOSFET, include: the silicon carbide epitaxial layer is etched with a groove, an oxide layer grows on the surface of the groove, a grid polycrystalline silicon electrode is arranged on the oxide layer, and the silicon carbide epitaxial layer is provided with a source electrode injection region and an accumulation layer which is connected with the silicon carbide epitaxial layer and the source electrode injection region; a blocking injection layer is also arranged between the silicon carbide epitaxial layer and the source injection region; the source electrode injection region is covered with a source electrode metal electrode; an insulating layer is arranged between the source metal electrode and the grid polycrystalline silicon electrode, a pressure-resistant injection region is arranged between the source metal electrode and the silicon carbide epitaxial layer, and the pressure-resistant injection region is positioned at the outer sides of the source injection region and the blocking injection layer, so that the problem of low channel mobility in the prior art is solved, the channel mobility can be improved when the silicon carbide epitaxial layer is applied, and the on-resistance is obviously reduced.

Description

Silicon carbide groove type MOSFET

Technical Field

The utility model relates to a semiconductor field, concretely relates to carborundum slot type MOSFET.

Background

Silicon carbide-based semiconductor devices benefit from the high thermal conductivity and high frequency properties of silicon carbide and are ideally suited for use at high temperatures and frequencies. In addition, the high critical field characteristics of silicon carbide enable the silicon carbide power device to have higher doping concentration and thinner drift layer thickness compared with the conventional silicon device under the same voltage application condition, thereby realizing lower on-resistance. The silicon carbide MOSFET has low switching loss and reverse recovery, and is very suitable for the application requirements of power electronics.

The existing planar gate silicon carbide MOSFET structure has larger unit spacing and high cost. SiO of planar gate silicon carbide MOSFET structure ₂ The channel mobility at the interface/SiC interface is low and the corresponding on-resistance is large. The conventional inversion MOSFET has the advantages that the channel mobility is not high in an accumulation state, the channel resistance is not low in the accumulation state MOSFET, and the on-resistance still has a reduced space.

SUMMERY OF THE UTILITY MODEL

The utility model provides a carborundum slot type MOSFET has solved the low problem of channel mobility that prior art exists, can improve channel mobility when it is used, and on-resistance is showing and is reducing.

In order to solve the technical problem, the utility model provides a following technical scheme:

a silicon carbide trench MOSFET comprising: a silicon carbide substrate and a silicon carbide epitaxial layer grown on the silicon carbide substrate,

a groove is etched on the silicon carbide epitaxial layer, an oxide layer grows on the surface of the groove, a grid polycrystalline silicon electrode is arranged on the oxide layer, and a source electrode injection region and an accumulation layer connecting the silicon carbide epitaxial layer and the source electrode injection region are arranged on the silicon carbide epitaxial layer; the thickness of the accumulation layer is 50nm-150 nm;

a blocking injection layer is also arranged between the silicon carbide epitaxial layer and the source injection region;

the source electrode injection region is covered with a source electrode metal electrode;

an insulating layer is arranged between the source metal electrode and the grid polycrystalline silicon electrode, a voltage-resistant injection region is arranged between the source metal electrode and the silicon carbide epitaxial layer, and the voltage-resistant injection region is positioned at the outer sides of the source injection region and the blocking injection layer;

the doping types of the silicon carbide substrate, the silicon carbide epitaxial layer, the source electrode injection region and the accumulation layer are a first conductivity type, and the doping types of the voltage-resistant injection region and the blocking injection layer are a second conductivity type.

According to the scheme, a groove is etched on a silicon carbide epitaxial layer, an oxide layer grows on the surface of the groove, a grid polycrystalline silicon electrode is arranged on the oxide layer to form a grid region of an MOSFET, and the on-off of a device is controlled. And positive voltage is applied to the grid polysilicon electrode to open the device. Electrons enter the device from the source injection region, an electron channel is formed near the accumulation layer, and conduction is formed through the silicon carbide epitaxial layer and the silicon carbide substrate. The existence of the accumulation layer can reduce the channel resistance, thereby greatly reducing the on-resistance. The blocking injection layer is used for keeping the MOSFET to be a normally-closed device, and the blocking injection layer and the silicon carbide epitaxial layer form a Pin structure to increase reverse voltage resistance. The withstand voltage injection region is also used to increase the reverse withstand voltage.

The first conductivity type may be N or P.

Preferably, the bottom of the groove is provided with a gate protection region for preventing a device from being penetrated when the gate voltage is too high

Preferably, the doping type of the gate protection region is the second conductivity type.

Preferably, the back surface of the silicon carbide substrate is covered with a drain metal electrode.

Preferably, the doping concentration and type of the silicon carbide substrate are N +, the doping concentration and type of the silicon carbide epitaxial layer are N-, the doping concentration and type of the source injection region are N +, and the doping concentration and type of the accumulation layer are N-.

Preferably, the doping concentration and type of the blocking injection layer are P, and the doping concentration and type of the withstand voltage injection region are P +.

Preferably, the doping concentration and type of the gate protection region are P +.

Compared with the prior art, the utility model, have following advantage:

compared with the planar gate MOSFET structure which is dominant in the commercial production market at present, the trench gate MOSFET design can realize smaller unit spacing, the channel mobility of the gate oxide surface is 2-3 times higher than that of the conventional planar gate silicon carbide MOSFET structure, and the on-resistance is obviously reduced.

Meanwhile, the existence of the accumulation layer can reduce the channel resistance, thereby greatly reducing the on-resistance. In addition, the accumulation layer can enable the electronic channel to be far away from the surface of the gate oxide when the device is switched on, and the problems of high on-resistance and reliability caused by the quality level of the gate oxide are solved. Meanwhile, the distribution area of the accumulation layer is less than 50%, and the threshold voltage and the reverse voltage resistance of the device are ensured.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

fig. 1 is a schematic structural diagram of the present invention.

Reference numbers and corresponding part names in the drawings:

101. a silicon carbide substrate; 102. a silicon carbide epitaxial layer; 103. a source injection region; 104. a voltage-resistant injection region; 105. blocking the injection layer; 106. a gate protection region; 107. an oxide layer; 108. a gate polysilicon electrode; 109. an accumulation layer; 110. an insulating layer; 111. a source metal electrode; 112. and a drain metal electrode.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in detail with reference to the following embodiments, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not intended as limitations of the present invention.

Example 1

As shown in fig. 1, a silicon carbide trench MOSFET, taking the first conductivity type as N and the second conductivity type as P as an example, includes: the MOSFET comprises a silicon carbide substrate 101 and a silicon carbide epitaxial layer 102 grown on the silicon carbide substrate 101, wherein the doping concentration and type of the substrate are N +, the doping concentration and type of the epitaxial layer are N-, a drain metal electrode 112 covers the back of the silicon carbide substrate 101 to form a drain region of the MOSFET; a groove is etched on the silicon carbide epitaxial layer 102, an oxide layer 107 grows on the surface of the groove, a grid polysilicon electrode 108 is arranged on the oxide layer 107 to form a grid region of the MOSFET, the on-off of the device is controlled, and the on-off of the device can be realized by applying positive pressure on the grid polysilicon electrode 108; the bottom of the trench is provided with a gate protection region 106, the gate protection region 106 can prevent a device from being penetrated when the gate voltage is too high, and the doping concentration and the type of the device are P +. The silicon carbide epitaxial layer 102 is provided with a source injection region 103 and an accumulation layer 109 connecting the silicon carbide epitaxial layer 102 and the source injection region 103, the doping concentration and type of the source injection region 103 are N +, the doping concentration and type of the accumulation layer 109 are N-, the thickness of the accumulation layer 109 is 50nm-150nm, and the existence of the accumulation layer 109 can reduce the channel resistance, thereby greatly reducing the on-resistance. In addition, the accumulation layer 109 can also enable an electron channel to be far away from the surface of the gate oxide when the device is turned on, so that the problems of high on-resistance and reliability caused by the quality level of the gate oxide are avoided. A blocking injection layer 105 is further arranged between the silicon carbide epitaxial layer 102 and the source injection region 103, the doping concentration and type of the blocking injection layer 105 are P, the blocking injection layer 105 and the silicon carbide epitaxial layer 102 form a Pin structure to increase reverse withstand voltage, and the blocking injection layer 105 and the silicon carbide epitaxial layer are used for keeping the MOSFET to be a normally closed device; the source injection region 103 is covered with a source metal electrode 111; an insulating layer 110 is provided between the source metal electrode 111 and the gate polysilicon electrode 108.

A voltage-resistant injection region 104 is arranged between the source metal electrode 111 and the silicon carbide epitaxial layer 102, and the voltage-resistant injection region 104 is positioned outside the source injection region 103 and the blocking injection layer 105; the doping concentration and type of the withstand voltage implanting region 104 are P +. The withstand voltage injection region 104 is used to increase a reverse withstand voltage.

In this embodiment, the MOSFET is a normally-off MOSFET, and the device can be turned on by applying a positive voltage to the gate polysilicon electrode 108 during operation. Electrons enter the device from the source metal electrode 111 through the source injection region 103, form an electron channel in the vicinity of the accumulation layer 109, and are conducted through the silicon carbide epitaxial layer 102, the silicon carbide substrate 101, and the drain metal electrode 112.

Example 2

The difference between this embodiment and embodiment 1 is that the first conductivity type is P, and the second conductivity type is N, that is, the conductivity types of the silicon carbide substrate 101, the silicon carbide epitaxial layer 102, the source implantation region 103, and the accumulation layer 109 are P type; the conductivity type of the blocking injection layer 105 and the voltage-resistant injection region 104 is N type; preferably, the doping concentration and type of the silicon carbide substrate 101 are P +, the doping concentration and type of the silicon carbide epitaxial layer 102 are P +, the doping concentration and type of the source implant region 103 are P +, the doping concentration and type of the accumulation layer 109 are P +, the doping concentration and type of the gate protection region 106 are N +, the doping concentration and type of the blocking implant layer 105 are N, and the doping concentration and type of the voltage-resistant implant region 104 are N +.

The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only the embodiments of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A silicon carbide trench MOSFET comprising: a silicon carbide substrate (101) and a silicon carbide epitaxial layer (102) grown on the silicon carbide substrate (101),

a groove is etched on the silicon carbide epitaxial layer (102), an oxide layer (107) grows on the surface of the groove, a grid polycrystalline silicon electrode (108) is arranged on the oxide layer (107), and a source injection region (103) and an accumulation layer (109) for connecting the silicon carbide epitaxial layer (102) and the source injection region (103) are arranged on the silicon carbide epitaxial layer (102);

a blocking injection layer (105) is also arranged between the silicon carbide epitaxial layer (102) and the source injection region (103);

the source injection region (103) is covered with a source metal electrode (111), an insulating layer (110) is arranged between the source metal electrode (111) and the grid polycrystalline silicon electrode (108), a voltage-resistant injection region (104) is arranged between the source metal electrode (111) and the silicon carbide epitaxial layer (102), and the voltage-resistant injection region (104) is positioned on the outer sides of the source injection region (103) and the blocking injection layer (105);

the doping types of the silicon carbide substrate (101), the silicon carbide epitaxial layer (102), the source electrode injection region (103) and the accumulation layer (109) are a first conductivity type, and the doping types of the voltage-resistant injection region (104) and the blocking injection layer (105) are a second conductivity type.

2. A silicon carbide trench MOSFET as claimed in claim 1 wherein the trench bottom is provided with a gate protection region (106).

3. A silicon carbide trench MOSFET as claimed in claim 2 wherein the gate guard region (106) is doped of the second conductivity type.

4. A silicon carbide trench MOSFET as claimed in claim 1 wherein the back side of the silicon carbide substrate (101) is covered with a drain metal electrode (112).

5. A silicon carbide trench MOSFET as claimed in claim 1 wherein the thickness of the accumulation layer (109) is in the range 50nm to 150 nm.

6. The silicon carbide trench MOSFET of claim 1 wherein the silicon carbide substrate (101) has a doping concentration and type of N +, the silicon carbide epitaxial layer (102) has a doping concentration and type of N-, the source implant region (103) has a doping concentration and type of N +, and the accumulation layer (109) has a doping concentration and type of N-.

7. The silicon carbide trench MOSFET of claim 1, wherein the blocking implant layer (105) is doped with a dopant concentration and type of P.

8. The silicon carbide trench MOSFET of claim 1, wherein the voltage implant region (104) is doped P + with a dopant concentration and type.

9. The silicon carbide trench MOSFET of claim 3, wherein the gate protection region (106) has a doping concentration and type of P +.