CN116913973B - Trench silicon carbide MOSFET with optimized current capability - Google Patents
Trench silicon carbide MOSFET with optimized current capability Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 199
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 199
- 239000002184 metal Substances 0.000 claims abstract description 62
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims description 133
- 239000000758 substrate Substances 0.000 claims description 51
- 239000011229 interlayer Substances 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000005553 drilling Methods 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 238000002203 pretreatment Methods 0.000 claims 1
- 239000002131 composite material Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000000969 carrier Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000005215 recombination Methods 0.000 description 4
- 230000006798 recombination Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000002441 reversible effect Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000013021 overheating Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 101100491259 Oryza sativa subsp. japonica AP2-2 gene Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000002301 combined effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The invention provides a trench silicon carbide MOSFET with optimized current capability, which relates to the technical field of MOSFET devices and aims to achieve higher current under the same power limit, wherein a first P-type silicon carbide buried layer is positioned on the left shoulder of an N-type silicon carbide epitaxial layer; the first gate oxide layer is connected with the first P-type silicon carbide buried layer, and the N-type silicon carbide epitaxial layer boss is connected; the first polysilicon is positioned on the first gate oxide layer; the second P-type silicon carbide buried layer is positioned at the right shoulder of the N-type silicon carbide epitaxial layer; the second gate oxide layer is connected with the second P-type silicon carbide buried layer and connected with the N-type silicon carbide epitaxial layer boss; the second polysilicon is positioned on the second gate oxide layer; the P-type silicon carbide base region is arranged on the N-type silicon carbide epitaxial layer, and the P-type silicon carbide base region, the first gate oxide layer and the second gate oxide layer are connected; and a source region layer, a medium and a metal layer are arranged on the P-type silicon carbide base region. The invention has the advantage of improving the overcurrent capacity on the premise of not influencing the switching loss of the device.
Description
Technical Field
The invention relates to the technical field of MOSFET devices, in particular to a trench silicon carbide MOSFET with optimized current capability.
Background
Compared with Si materials, the SiC material has the advantages of high breakdown field strength (4X 106V/cm), high carrier saturation drift speed (2X 107 cm/s), high heat conductivity, good heat stability and the like, so that the SiC material is particularly suitable for high-power, high-voltage, high-temperature and radiation-resistant electronic devices. SiC VDMOS is a device that is more commonly used in SiC power devices, and has better frequency characteristics and lower switching loss than a bipolar device because SiC VDMOS has no charge storage effect. Meanwhile, the wide forbidden band of the SiC material enables the working temperature of the SiC VDMOS to be 300 ℃.
Under the conventional design, the common silicon carbide MOFET body diode has poor performance, larger conduction loss and larger reverse recovery current, therefore, the invention integrates the gate control diode on the basis of the silicon carbide trench MOSFET, and utilizes an inversion channel to carry out third quadrant output in a unipolar conduction mode. But the silicon carbide MOSFET of monolithically integrated gated diode has the disadvantage of insufficient over-current robustness. For body diodes, excessive composite current can cause channel overheating damage; the MOSFET itself, the combined effect of device surface overheating and hot carrier injection in a short circuit condition, damages the gate oxide. The integrated gate control diode can greatly reduce the static power consumption and the dynamic power consumption of the body diode, and the parasitic PIN diode can enter a bipolar conduction mode when suffering from surge current, so that the capability of resisting the surge current is improved. However, as the withstand voltage of the silicon carbide power device is higher and higher, the drift region is thicker and thicker, so that more and more minority carriers are combined in the drift region to form a composite current in the bipolar conducting process, and the composite current is borne by the channel of the gate control diode, so that the reliability of the gate oxide layer of the gate control diode is greatly reduced. In order to alleviate the problem, a parallel PNP BJT is integrated for the grid-controlled diode to replace the original PIN diode, so that when surge current arrives, an emitter junction of the PNP BJT is forward biased, a collector junction is reverse biased, and the PNP BJT enters a conducting state, and because the concentration of a base region is far lower than that of a collector region, a depletion region expands towards the base region, the thickness of an effective base region is reduced, the recombination of minority carriers in the base region is reduced, namely the generation of composite current is reduced, the current density of a channel region in the surge state is relieved, and the surge current resistance of the body diode is improved. In addition, siC MOSFETs are unipolar devices in which the drift region resistance is too high at high temperatures and high currents to withstand sustained high currents.
It is therefore a highly desirable problem to be able to achieve higher currents with the same power limit.
Disclosure of Invention
It is an object of the present invention to provide a current capability optimized trench silicon carbide MOSFET that can achieve higher currents with the same power limitations.
The embodiment of the invention is realized by the following technical scheme:
The trench silicon carbide MOSFET with optimized current capability comprises a back metal, a mixed substrate layer, an N-type silicon carbide epitaxial layer, a first P-type silicon carbide buried layer, a second P-type silicon carbide buried layer, a first gate oxide layer, a second gate oxide layer, first polysilicon, second polysilicon, a P-type silicon carbide base region, a source region layer, a medium and a metal layer; the first gate oxide layer and the second gate oxide layer are both L-shaped; the N-type silicon carbide epitaxial layer is of a boss structure; the mixed substrate layer is arranged on the back metal; the N-type silicon carbide epitaxial layer is arranged on the mixed substrate layer;
The first P-type silicon carbide buried layer is positioned in the left shoulder groove of the N-type silicon carbide epitaxial layer; the first side of the first gate oxide layer is connected with the upper part of the first P-type silicon carbide buried layer, and the second side of the first gate oxide layer is connected with the left side of the N-type silicon carbide epitaxial layer boss; the first polysilicon is positioned in the L-shaped groove of the first gate oxide layer; the second P-type silicon carbide buried layer is positioned in the right shoulder groove of the N-type silicon carbide epitaxial layer; the first side of the second gate oxide layer is connected with the upper part of the second P-type silicon carbide buried layer, and the second side of the second gate oxide layer is connected with the right side of the N-type silicon carbide epitaxial layer boss; the second polysilicon is positioned in the L-shaped groove of the second gate oxide layer; the P-type silicon carbide base region is arranged on a boss of the N-type silicon carbide epitaxial layer, and the left side and the right side of the P-type silicon carbide base region are respectively connected with the second side of the first gate oxide layer and the second side of the second gate oxide layer; a source region layer is arranged above the P-type silicon carbide base region; and a dielectric layer and a metal layer are arranged above the source region layer.
Preferably, the mixed substrate layer comprises a first N-type silicon carbide substrate, a second N-type silicon carbide substrate and a P-type silicon carbide substrate;
the first N-type silicon carbide substrate is arranged at the left upper part of the back metal; the second N-type silicon carbide substrate is arranged on the right upper side of the back metal; the P-type silicon carbide substrate is disposed between the first N-type silicon carbide substrate and the second N-type silicon carbide substrate.
Preferably, the doping concentration range of the P-type silicon carbide substrate is 1.0E18To 1.0E22/>And its doping concentration should be at least an order of magnitude higher than the N-type silicon carbide epitaxial layer.
Preferably, the P-type silicon carbide substrate is formed by high-energy ion implantation, and the pretreatment before the ion implantation comprises substrate thinning, drilling and physical/chemical vapor deposition.
Preferably, the doping concentration ranges of the first and second P-type silicon carbide buried layers are 1.0E18To 1.0E22/>And its potential floats.
Preferably, the doping concentration range of the P-type silicon carbide base region is 1.0E16To 1.0E19/>。
Preferably, the source region layer comprises a first N-type silicon carbide source region, a second N-type silicon carbide source region and a P-type silicon carbide source region;
The first N-type silicon carbide source region, the second N-type silicon carbide source region and the P-type silicon carbide source region are sequentially connected and arranged from left to right; the left side of the first N-type silicon carbide source region is contacted with the second side of the first gate oxide layer; the second N-type silicon carbide source region is in contact with a second side of the second gate oxide layer.
Preferably, the dielectric and metal layer comprises an interlayer dielectric and a surface metal;
the bottom of the interlayer medium is connected with the upper part of the first polysilicon, the upper part of the second side of the first gate oxide layer and the upper left part of the first N-type silicon carbide source region;
The surface metal is of an L-shaped structure, an L-shaped opening of the surface metal faces downwards, the bottom of a first side of the surface metal is connected with the top of the interlayer medium, the left side of a second side of the surface metal is connected with the right side of the top of the interlayer medium, and the bottom of the second side of the surface metal is connected with the right upper part of the first N-type silicon carbide source region, the P-type silicon carbide source region and the second N-type silicon carbide source region.
Preferably, metal silicide is formed between the surface metal and three regions of the first N-type silicon carbide source region, the P-type silicon carbide source region and the second N-type silicon carbide source region by using metal Ni or metal Ti.
Preferably, metal silicide is formed between the second polysilicon and the surface metal by using metal Ti.
The technical scheme of the embodiment of the invention has at least the following advantages and beneficial effects:
the bipolar conducting mode is replaced by the unipolar conducting mode in a channel freewheeling mode by integrating the grid-controlled diode, so that reverse recovery current of the body diode is completely eliminated, and switching loss of the device is reduced. In addition, the channel barrier of the integrated gate control diode is adjustable relative to the junction barrier, so that the conduction loss of the body diode can be reduced;
The PNP BJT is integrated, and the base region composite current is reduced by the body diode in a mode of reversely extracting minority carriers by the emitter junction, so that the base region composite current is reduced while the current capacity of the body diode is improved, and the base region composite current is reduced, thereby reducing the channel current density of the integrated gate control diode and improving the robustness of the device under the condition that the body diode is conducted under the heavy current;
And under the rated working condition, the emitter junction of the PNP BJT cannot be conducted, the device is equivalent to a common SiC MOSFET, and the PNP BJT works in a unipolar conduction mode and has extremely high switching speed. When the device is in a high-temperature high-current working condition, the emitter junction of the PNP BJT is conducted, the device enters a bipolar conducting state, and the conducting resistance of the device is greatly reduced by the double effects of conducting modulation and parasitic PNP BJT conduction, so that the device can bear larger current under the same power limit (transient thermal resistance determination).
Drawings
FIG. 1 is a schematic diagram of a trench silicon carbide MOSFET with optimized current capability according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an equivalent circuit of a trench silicon carbide MOSFET with optimized current capability according to an embodiment of the present invention;
FIG. 3 is a first quadrant conduction I-V curve of a trench silicon carbide MOSFET with optimized current capability in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram of current distribution when the third quadrant rated current of a trench silicon carbide MOSFET with optimized current capability is turned on according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating the current distribution of a trench silicon carbide MOSFET with optimized current capability in the third quadrant during high current conduction according to an embodiment of the present invention;
Reference numerals: 01-back metal, 021-first N-type silicon carbide substrate, 022-second N-type silicon carbide substrate, 03-P-type silicon carbide substrate, 04-N-type silicon carbide epitaxial layer, 051-first P-type silicon carbide buried layer, 052-second P-type silicon carbide buried layer, 061-first gate oxide layer, 062-second gate oxide layer, 071-first polysilicon, 072-second polysilicon, 08-P-type silicon carbide base region, 091-first N-type silicon carbide source region, 092-second N-type silicon carbide source region, 010-P-type silicon carbide source region, 011-interlayer dielectric, 012-surface metal.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Example 1
The embodiment provides a trench silicon carbide MOSFET with optimized current capability, referring specifically to fig. 1, which includes a back metal 01, a mixed substrate layer, an N-type silicon carbide epitaxial layer 04, a first P-type silicon carbide buried layer 051, a second P-type silicon carbide buried layer 052, a first gate oxide layer 061, a second gate oxide layer 062, a first polysilicon 071, a second polysilicon 072, a P-type silicon carbide base 08, a source region layer, a medium and a metal layer; the first gate oxide layer 061 and the second gate oxide layer 062 are both L-shaped; the N-type silicon carbide epitaxial layer 04 is of a boss structure; the mixed substrate layer is arranged on the back metal 01; the N-type silicon carbide epitaxial layer 04 is arranged on the mixed substrate layer;
The first P-type silicon carbide buried layer 051 is positioned in a left shoulder groove of the N-type silicon carbide epitaxial layer 04; a first side of the first gate oxide layer 061 is connected with the upper part of the first P-type silicon carbide buried layer 051, and a second side of the first gate oxide layer 061 is connected with the left side of the boss of the N-type silicon carbide epitaxial layer 04; the first polysilicon 071 is located in the L-shaped groove of the first gate oxide layer 061; the second P-type silicon carbide buried layer 052 is positioned in the right shoulder groove of the N-type silicon carbide epitaxial layer 04; the first edge of the second gate oxide layer 062 is connected with the upper part of the second P-type silicon carbide buried layer 052, and the second edge is connected with the right side of the boss of the N-type silicon carbide epitaxial layer 04; the second polysilicon 072 is located in the L-shaped groove of the second gate oxide 062; the P-type silicon carbide base region 08 is arranged on a boss of the N-type silicon carbide epitaxial layer 04, and the left side and the right side of the P-type silicon carbide base region 08 are respectively connected with the second side of the first gate oxide layer 061 and the second side of the second gate oxide layer 062; a source region layer is arranged above the P-type silicon carbide base region 08; and a dielectric layer and a metal layer are arranged above the source region layer.
When the device is in a rated working state, the drain-source voltage drop is only 1-3 VSiC PN junction with an opening voltage higher than 3V, and the emitter junction of the PNP BJT cannot be conducted, so that the device is in a unipolar conduction mode and has the same switching speed as a common SiC MOSFET. However, when the device is in a high-temperature high-current working state, the emitter junction of the PNP BJT is conducted, the device enters a bipolar conduction mode, and the resistance of the device is reduced, so that higher current can be achieved under the same power limit.
Example 2
The present embodiment is based on the technical solution of embodiment 1, and further refines the structure of the trench silicon carbide MOSFET with optimized current capability.
Referring specifically to fig. 1, the hybrid substrate layer includes a first N-type silicon carbide substrate 021, a second N-type silicon carbide substrate 022, and a p-type silicon carbide substrate 03;
The first N-type silicon carbide substrate 021 is arranged at the upper left part of the back metal 01; the second N-type silicon carbide substrate 022 is arranged on the upper right side of the back metal 01; the P-type silicon carbide substrate 03 is disposed between the first N-type silicon carbide substrate 021 and the second N-type silicon carbide substrate 022.
Further, the doping concentration range of the P-type silicon carbide substrate 03 is 1.0E18To 1.0E22/>And its doping concentration should be at least an order of magnitude higher than that of the N-type silicon carbide epitaxial layer 04.
In this embodiment, the P-type silicon carbide substrate 03 may be formed by high-energy ion implantation, and the pretreatment before the ion implantation includes substrate thinning, drilling, and physical/chemical vapor deposition.
Specifically, the doping concentration ranges of the first P-type silicon carbide buried layer 051 and the second P-type silicon carbide buried layer 052 are 1.0E18To 1.0E22/>And its potential floats.
Meanwhile, the doping concentration range of the P-type silicon carbide base region 08 is 1.0E16To 1.0E19/>。
In another aspect, the source region layer includes a first N-type silicon carbide source region 091, a second N-type silicon carbide source region 092, and a P-type silicon carbide source region 010;
the first N-type silicon carbide source region 091, the second N-type silicon carbide source region 092 and the P-type silicon carbide source region 010 are sequentially connected and arranged from left to right; the left side of the first N-type silicon carbide source region 091 is in contact with the second side of the first gate oxide 061; the second N-type silicon carbide source region 092 is in contact with a second side of the second gate oxide layer 062.
In this embodiment, the dielectric and metal layer includes an interlayer dielectric 011 and a surface metal 012;
The bottom of the interlayer dielectric 011 is connected with the upper part of the first polysilicon 071, the upper part of the second side of the first gate oxide 061 and the upper left part of the first N-type silicon carbide source area 091;
The surface metal 012 has an L-shaped structure with an opening facing downwards, the bottom of the first side of the surface metal 012 is connected with the top of the interlayer dielectric 011, the left side of the second side of the surface metal 012 is connected with the right side of the top of the interlayer dielectric 011, and the bottom of the second side of the surface metal 012 is connected with the upper right side of the first N-type silicon carbide source region 091, the P-type silicon carbide source region 010 and the second N-type silicon carbide source region 092.
As a further optimization scheme, metal silicide is formed between the three regions of the first N-type silicon carbide source region 091, the P-type silicon carbide source region 010 and the second N-type silicon carbide source region 092 and the surface metal 012 by using metal Ni or metal Ti.
In particular, a metal silicide is formed between the second polysilicon 072 and the surface metal 012 using metal Ti.
The specific working principle of this embodiment is as follows:
An equivalent circuit diagram of a trench silicon carbide MOSFET with optimized current capability of this embodiment is shown in fig. 2. As can be seen from the equivalent circuit diagram, the device is mainly composed of 4 parts, namely a MOSFET, a gated diode, a PNP BJT and a resistor R1, wherein the resistor R1 can be adjusted by changing the ratio of the P-type silicon carbide substrate 03 and the first N-type silicon carbide substrate 021 and the second N-type silicon carbide substrate 022 as in fig. 1.
When the device is in the first quadrant conduction state, currentWill flow through the resistor R1 and MOSFET portion, in this on state, since the emitter junction of the PNP BJT is not on, the device will operate in unipolar conduction mode, with a switching speed equivalent to that of a normal MOSFET. With the increase of the on-current of the device, the potential difference at the two ends of the resistor R1 is increased, when the potential difference between the node 1 and the node 2 exceeds 3V, the emitter junction of the PNP BJT is conducted, the collector is reversely biased, the PNP BJT is conducted, at the moment, the original current IDS1 is enhanced under the effect of the conductivity modulation effect, and simultaneously, bipolar current/>At this point the total current of the device will be equal to/>Sum/>As shown in fig. 3, the maximum sustainable current simulation comparison result of the device of the present embodiment and the common SiC MOSFET at 175 ℃, due to the conductance modulation effect and the addition of the PNP BJT current, a larger current can be achieved in the device structure setting of the present embodiment compared to the common SiC MOSFET.
When the device is in the third quadrant working state, the current flows from the source electrode to the drain electrode through the grid-controlled diode to form electron current，/>Flow is divided into two branches/>，/>The current distribution is shown in fig. 4, and since the current distribution is in the unipolar conduction mode, the minority carrier storage effect is not existed, and the channel barrier of the gated diode is adjustable, the current distribution is due to the conventional PN junction body diode in both static characteristic and dynamic characteristic. With the continuous increase of current, the voltage drop on the grid-controlled diode is higher than 3V, and the collector junction of the PNP BJT is conducted in the forward direction to form current/>，/>Is bipolar current, which is divided into hole diffusion current formed by large injection of PN junction and electron current formed by recombination of holes in the process of base region transportation and flowing through a channel of a grid-controlled diode, so that the actual current is/>, under the large currentAnd/>The current distribution of which is shown in FIG. 5, the particular branch comprises two/>Two/>/>. When the device enters a high-current conduction state, the part of the composite current is increased/>The power consumption of the channel of the gate control diode is increased, the heat is generated, and the reliability of the gate oxide layer is reduced, which is particularly obvious when the epitaxial layer is thicker. To reduce the complex current/>The embodiment adopts an integrated PNP BJT mode to extract minority carriers of a base region by utilizing a space charge region electric field of a PNP BJT emitter junction, and by the method, the effective base width is reduced from the original Wb to Wb', the minority carrier recombination rate is reduced, the recombination current density is reduced, and the reliability of the grid-controlled diode under high current is improved.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. The trench silicon carbide MOSFET with optimized current capability is characterized by comprising a back metal (01), a mixed substrate layer, an N-type silicon carbide epitaxial layer (04), a first P-type silicon carbide buried layer (051), a second P-type silicon carbide buried layer (052), a first gate oxide layer (061), a second gate oxide layer (062), first polysilicon (071), second polysilicon (072), a P-type silicon carbide base region (08), a source region layer, a medium and a metal layer; the first gate oxide layer (061) and the second gate oxide layer (062) are both L-shaped; the N-type silicon carbide epitaxial layer (04) is of a boss structure; the mixed substrate layer is arranged on the back metal (01); the N-type silicon carbide epitaxial layer (04) is arranged on the mixed substrate layer;
The first P-type silicon carbide buried layer (051) is positioned in a left shoulder groove of the N-type silicon carbide epitaxial layer (04); a first side of the first gate oxide layer (061) is connected with the upper part of the first P-type silicon carbide buried layer (051), and a second side of the first gate oxide layer is connected with the left side of the boss of the N-type silicon carbide epitaxial layer (04); the first polysilicon (071) is located in the L-shaped groove of the first gate oxide layer (061); the second P-type silicon carbide buried layer (052) is positioned in the right shoulder groove of the N-type silicon carbide epitaxial layer (04); the first side of the second gate oxide layer (062) is connected with the upper part of the second P-type silicon carbide buried layer (052), and the second side of the second gate oxide layer is connected with the right side of the boss of the N-type silicon carbide epitaxial layer (04); the second polysilicon (072) is positioned in the L-shaped groove of the second gate oxide layer (062); the P-type silicon carbide base region (08) is arranged on a boss of the N-type silicon carbide epitaxial layer (04), and the left side and the right side of the P-type silicon carbide base region (08) are respectively connected with the second side of the first gate oxide layer (061) and the second side of the second gate oxide layer (062); a source region layer is arranged above the P-type silicon carbide base region (08); a medium and a metal layer are arranged above the source region layer;
the source region layer comprises a first N-type silicon carbide source region (091), a second N-type silicon carbide source region (092) and a P-type silicon carbide source region (010);
The first N-type silicon carbide source region (091), the second N-type silicon carbide source region (092) and the P-type silicon carbide source region (010) are sequentially connected and arranged from left to right; the left side of the first N-type silicon carbide source region (091) is in contact with the second side of the first gate oxide layer (061); the second N-type silicon carbide source region (092) is in contact with a second side of the second gate oxide layer (062);
the medium and metal layer comprises an interlayer medium (011) and surface metal (012);
the bottom of the interlayer medium (011) is connected with the upper part of the first polysilicon (071), the upper part of the second side of the first gate oxide layer (061) and the upper left part of the first N-type silicon carbide source region (091);
the surface metal (012) is in an L-shaped structure, an L-shaped opening of the surface metal (012) is downward, the bottom of a first side of the surface metal (012) is connected with the top of the interlayer medium (011), the left side of a second side of the surface metal (012) is connected with the right side of the top of the interlayer medium (011), and the bottom of the second side of the surface metal (012) is connected with the right upper part of the first N-type silicon carbide source region (091), the P-type silicon carbide source region (010) and the second N-type silicon carbide source region (092);
forming metal silicide between the three regions of the first N-type silicon carbide source region (091), the P-type silicon carbide source region (010) and the second N-type silicon carbide source region (092) and the surface metal (012) by using metal Ni or metal Ti;
the mixed substrate layer comprises a first N-type silicon carbide substrate (021), a second N-type silicon carbide substrate (022) and a P-type silicon carbide substrate (03);
The first N-type silicon carbide substrate (021) is arranged at the upper left part of the back metal (01); the second N-type silicon carbide substrate (022) is arranged on the upper right side of the back metal (01); the P-type silicon carbide substrate (03) is disposed between the first N-type silicon carbide substrate (021) and the second N-type silicon carbide substrate (022).
2. A current capability optimized trench silicon carbide MOSFET as claimed in claim 1, wherein the P-type silicon carbide substrate (03) has a doping concentration in the range 1.0E18 to 1.0E22And its doping concentration should be at least an order of magnitude higher than the N-type silicon carbide epitaxial layer (04).
3. A trench silicon carbide MOSFET with optimized current capability according to claim 2, characterized in that the P-type silicon carbide substrate (03) is formed by high energy ion implantation, the pre-treatment before ion implantation comprising substrate thinning, drilling, physical/chemical vapor deposition.
4. The current-capability-optimized trench silicon carbide MOSFET of claim 1 wherein said first and second buried P-type silicon carbide layers (051, 052) each have a doping concentration in the range 1.0E18To 1.0E22/>And its potential floats.
5. A current capability optimized trench silicon carbide MOSFET as claimed in claim 4, wherein said P-type silicon carbide base region (08) has a doping concentration in the range 1.0E16To 1.0E19/>。
6. A current capability optimized trench silicon carbide MOSFET as claimed in claim 1, wherein a metal silicide is formed between said second polysilicon (072) and said surface metal (012) using metal Ti.
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| CN114551601A (en) * | 2022-04-26 | 2022-05-27 | 成都蓉矽半导体有限公司 | Silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) of integrated grid-controlled diode with high surge current resistance |
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