CN108550630B - Diode and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 255
- 229910052751 metal Inorganic materials 0.000 claims abstract description 62
- 239000002184 metal Substances 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 38
- 230000008569 process Effects 0.000 claims description 36
- 238000005530 etching Methods 0.000 claims description 30
- 238000000151 deposition Methods 0.000 claims description 22
- 230000004888 barrier function Effects 0.000 claims description 21
- 238000005468 ion implantation Methods 0.000 claims description 16
- 230000008021 deposition Effects 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 9
- 210000003850 cellular structure Anatomy 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000007667 floating Methods 0.000 claims description 2
- 238000011084 recovery Methods 0.000 abstract description 22
- 229910010271 silicon carbide Inorganic materials 0.000 description 242
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 196
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 38
- 229920005591 polysilicon Polymers 0.000 description 34
- 238000010586 diagram Methods 0.000 description 16
- 230000000903 blocking effect Effects 0.000 description 13
- 210000004027 cell Anatomy 0.000 description 12
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 12
- 230000000694 effects Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 241000282414 Homo sapiens Species 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
- 239000000969 carrier Substances 0.000 description 5
- 230000006872 improvement Effects 0.000 description 5
- 239000002210 silicon-based material Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 210000003127 knee Anatomy 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 241000282412 Homo Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000003034 coal gas Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000003345 natural gas Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004083 survival effect Effects 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
Abstract
A diode device and a manufacturing method thereof belong to the technical field of power semiconductor devices. The cell structure of the device comprises a metal cathode, an N + substrate, an N-epitaxial layer and a metal anode, wherein two sides of the top layer of the N-epitaxial layer are provided with groove structures, each groove structure comprises a P + semiconductor area and a P-type semiconductor Well area from bottom to top, the P-type semiconductor Well areas are in contact with the metal anode above the P-type semiconductor Well areas, and the upper surfaces of part of the P-type semiconductor Well areas and the N-semiconductor epitaxial layer are provided with dielectric layers; the upper surfaces of the dielectric layer and the N-semiconductor epitaxial layer are provided with heterogeneous semiconductors; the hetero-semiconductor, the dielectric layer, the P-type semiconductor Well region and the N-semiconductor epitaxial layer form a super-barrier structure. On the premise of not influencing the performance of the device, the forward starting voltage of the traditional PIN device is obviously reduced, the reverse recovery characteristic of the device is optimized, and the good compromise characteristic between the forward conduction voltage drop and the turn-off loss is obtained. In addition, the device also provides multiple working mode selections, thereby greatly facilitating the practical application occasions.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a diode and a manufacturing method thereof.
Background
The energy resource is an important material basis for human survival and realization and development and is a power source for human production and life. Many energy resources are inexhaustible, such as wind energy, solar energy, tidal energy and the like. However, the main energy sources used in production and life are non-renewable energy sources, including fossil energy, coal, and natural gas, etc., thereby causing global energy crisis. Since the 21 st century, this problem has been increasingly emphasized. How to reduce unnecessary energy loss in production and life, that is, how to improve the utilization rate of energy resources, is an important means for relieving the global energy crisis. Electric energy has long been indispensable in life as one of energy sources that can be directly used by humans. The electric power system is a necessary way for human beings to utilize electric energy and improve the use efficiency of the electric energy, and the electric power system reflects the modernization degree of the electric power system on the aspects of electric energy transportation, management and use efficiency and further reflects the utilization efficiency of energy resources by human beings. According to statistics, more than 90% of the world electric energy is controlled by a power device through an electric power system. From a certain point of view, the control electric energy efficiency of the power device is high and low, and the sustainable development of human beings is concerned.
Power diodes are the simplest electronic components among many power semiconductor devices, but are also one of the most widely used devices, and play a very critical role in the circuit. Therefore, the performance of the power diode is often one of the key factors for the success of the circuit design. The power diode typically employs a P + N-N + structure as shown in fig. 1, with the low doped region of the diode typically being driven to a large implant state when the device is in a forward biased state. The middle region in this state is the same as without doping (intrinsic) and therefore the P + N-N + diode PIN is commonly referred to as a PIN diode. The PIN diode is used as a bipolar device, the forward voltage drop of the PIN diode can be obviously reduced by a conductance modulation effect generated in the forward conduction process of the PIN diode, however, a large number of excess carriers exist in a drift region during turn-off, which causes unavoidable turn-off loss during turn-off, prolongs turn-off time, further influences the reverse recovery characteristic of the PIN diode, and is not beneficial to the application of the PIN diode in occasions such as high-speed rectification, fast recovery and the like. While the reverse recovery characteristics of PIN diodes are critical to power electronics systems.
Meanwhile, with the gradual maturity of power semiconductor technology, the characteristics of silicon-based power devices gradually approach the theoretical limit. Researchers strive to find better parameters in a narrow optimization space of a silicon-based power device and pay attention to excellent material characteristics of third-generation wide-bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN) and the like in the fields of high power, high frequency, high temperature resistance, radiation resistance and the like. Among them, the silicon carbide power diode device is called a "green energy" device of "new energy revolution" by those in the industry because the silicon carbide, which is a wide bandgap semiconductor material, has a significant effect of reducing power loss. Besides, the silicon carbide material has many attractive properties, such as 10 times of the critical breakdown electric field strength of the silicon material, high thermal conductivity, large forbidden band width, high electron saturation drift velocity, etc., and these performance advantages make the silicon carbide material a hot research point for power semiconductor devices internationally. However, while the development of silicon carbide power diode devices is becoming mature, the disadvantages of wide bandgap semiconductor materials are also shown: the wide bandgap of the semiconductor material can cause a larger knee point voltage, taking silicon carbide as an example, the forward conduction voltage drop of the silicon carbide PIN diode device is about 3.1V, and the forward conduction voltage drop of the silicon PIN diode is only about 0.7V, so that compared with the silicon carbide PIN diode device, the conduction loss is obviously increased, the rectification efficiency is reduced, and the serious waste of energy resources is caused. This is contrary to the "green industry" concept that is highly emphasized by today's society.
Disclosure of Invention
In view of the above, the present invention aims to: aiming at the problems of larger conduction loss, poor reverse recovery characteristic and the like of a PIN diode in the prior art, the diode device structure capable of reducing forward conduction voltage, optimizing reverse recovery characteristic and maintaining high-voltage blocking capability is provided, and the diode device structure is suitable for various semiconductor materials; meanwhile, the invention also provides a preparation method of the diode device.
On one hand, the invention provides a diode device, the cellular structure of which comprises a metal cathode 5, an N + wide bandgap semiconductor substrate 4, an N-wide bandgap semiconductor epitaxial layer 3 and a metal anode 1 which are sequentially stacked from bottom to top; two sides of the top layer of the N-wide forbidden band semiconductor epitaxial layer 3 are provided with groove structures, each groove structure comprises a P + wide forbidden band semiconductor region 2 and a P type wide forbidden band semiconductor Well region 10, the P + wide forbidden band semiconductor region 2 is positioned at the bottom of each groove, and the P type wide forbidden band semiconductor Well region 10 is positioned on the upper surface of the P + wide forbidden band semiconductor region 2; the upper surface of a part of the P-type wide bandgap semiconductor Well area 10 is contacted with the metal anode 1, and the upper surfaces of the part of the P-type wide bandgap semiconductor Well area 10 and the part of the N-type wide bandgap semiconductor epitaxial layer 3 are provided with a dielectric layer 8 contacted with the upper surface; the dielectric layer 8 and the upper surface of part of the N-wide bandgap semiconductor epitaxial layer 3 are provided with a narrow bandgap semiconductor region 7 contacted with the dielectric layer; the narrow forbidden band semiconductor region 7, the dielectric layer 8, the P type wide forbidden band semiconductor Well region 10 and the N-wide forbidden band semiconductor epitaxial layer 3 form a super barrier structure, the narrow forbidden band semiconductor region 7 and the N-wide forbidden band semiconductor epitaxial layer 3 form a heterojunction, and the P + wide forbidden band semiconductor region 2 and the N-wide forbidden band semiconductor epitaxial layer 3 form a PN junction.
Furthermore, the invention also comprises an N + wide bandgap semiconductor source region 9 directly contacted with the metal anode 1, wherein the N + wide bandgap semiconductor source region 9 is positioned at the top layer of a P-type wide bandgap semiconductor Well region 10, the P-type wide bandgap semiconductor Well region 10 is separated from the metal anode 1 through the N + wide bandgap semiconductor source region 9, and the upper surface of part of the N + wide bandgap semiconductor source region 9 is contacted with the dielectric layer 8.
Furthermore, the invention also comprises a P + wide forbidden band semiconductor contact region 6, wherein the P + wide forbidden band semiconductor contact region 6 and the P type wide forbidden band semiconductor Well region 10 are arranged on the upper surface of the P + wide forbidden band semiconductor region 2 in parallel, and the P + wide forbidden band semiconductor contact region 6 is contacted with the N + wide forbidden band semiconductor source region 9; the upper surfaces of the P + wide bandgap semiconductor contact region 6 and the partial N + wide bandgap semiconductor source region 9 are contacted with the metal anode 1, and the upper surface of the partial N + wide bandgap semiconductor source region 9 is contacted with the dielectric layer 8.
Further, the width of the P + wide bandgap semiconductor region 2 is larger than the width of the trench in the present invention.
Furthermore, the P + wide bandgap semiconductor region 2 and the N-wide bandgap semiconductor epitaxial layer 3 form a super junction structure; according to the common knowledge of those skilled in the art, the P + wide bandgap semiconductor region 2 and the N-wide bandgap semiconductor epitaxial layer 3 satisfy the requirement of Qp ═ Qn.
Preferably, when the P + wide bandgap semiconductor region 2 and the N-wide bandgap semiconductor epitaxial layer 3 form a super junction structure, the doping concentration of the top layer of the N-wide bandgap semiconductor epitaxial layer 3 is higher than the doping concentration below the top layer.
Preferably, when the P + wide bandgap semiconductor region 2 and the N-wide bandgap semiconductor epitaxial layer 3 form a super junction structure, the doping concentration of the top layer of the P + wide bandgap semiconductor region 2 is higher than the doping concentration below the top layer.
According to the embodiment of the present invention, the material of the wide bandgap semiconductor is silicon carbide, and the material of the narrow bandgap semiconductor is silicon material, and according to the common general knowledge in the art, other combinations composed of the wide bandgap semiconductor material and the narrow bandgap semiconductor material are also suitable for the device structure provided by the present invention, and the present invention is not limited thereto.
Further, when the narrow bandgap semiconductor is made of a silicon material, the narrow bandgap semiconductor may be polysilicon or monocrystalline silicon, the polycrystalline silicon may be P-type polysilicon or N-type polysilicon, and the monocrystalline silicon may be P-type monocrystalline silicon or N-type monocrystalline silicon.
Further, the P + wide bandgap semiconductor region 2 may be shorted to the ground or may be arranged in a floating manner.
On the other hand, the invention provides a manufacturing method of a diode device, which is characterized by comprising the following steps:
step 1: selecting a wide bandgap semiconductor material as an N + wide bandgap semiconductor substrate 4 and an N-wide bandgap semiconductor epitaxial layer 3;
step 2: forming grooves on two sides of the N-wide bandgap semiconductor epitaxial layer 3 through a groove etching process;
and step 3: depositing a P-type wide bandgap semiconductor material at the bottom of the groove or injecting a P-type wide bandgap semiconductor material below the groove by a deposition and etching process or an ion injection process to form a P + wide bandgap semiconductor region 2;
and 4, step 4: forming a P-type wide bandgap semiconductor Well region 10 on the upper surface of the P + wide bandgap semiconductor region 2 through a deposition and etching process or an epitaxial process;
and 5: depositing a dielectric layer material on the upper surfaces of the P-type wide bandgap semiconductor Well region 10 and the N-wide bandgap semiconductor epitaxial layer 3 through a dry oxygen oxidation or deposition process, and removing the redundant dielectric layer material through etching to form a dielectric layer 8 covering a part of the P-type wide bandgap semiconductor Well region 10 and a part of the N-wide bandgap semiconductor epitaxial layer 3;
step 6: depositing a narrow bandgap semiconductor material on the dielectric layer 8 and the upper surface of the N-wide bandgap semiconductor epitaxial layer 3 through a deposition and etching process, and removing the redundant narrow bandgap semiconductor material through etching to form a narrow bandgap semiconductor region 7 positioned above the dielectric layer 8 and the N-wide bandgap semiconductor epitaxial layer 3;
and 7: through deposition, photoetching and etching processes, a metal anode 1 is formed on the upper surfaces of the narrow bandgap semiconductor 7, the dielectric layer 8 and the P-type wide bandgap semiconductor Well region 10, and a metal cathode 5 is formed on the back surface of the turnover device, so that the manufacture of the device is completed.
Further, the step 5 is preceded by the steps of: through photoetching and ion implantation processes, an N + wide bandgap semiconductor source region 9 is formed on the top layer of a P type wide bandgap semiconductor Well region 10, and a metal anode 1 and a dielectric layer 8 are respectively manufactured on the upper surface of the N + wide bandgap semiconductor source region 9.
Furthermore, when the N + wide bandgap semiconductor source region 9 is formed between the P-type wide bandgap semiconductor Well region 10 and the metal anode 1, the P + wide bandgap semiconductor region 2 in step 7 of the present invention can be either grounded or float.
Further, the step 5 is preceded by the steps of: through photoetching and ion implantation processes, a P + silicon carbide contact region 6 which is parallel to a P type wide forbidden band semiconductor Well region 10 is formed on the upper surface of the P + wide forbidden band semiconductor region 2, an N + wide forbidden band semiconductor source region 9 which is in contact with the P + silicon carbide contact region 6 is formed on the P type wide forbidden band semiconductor Well region 10, a metal anode 1 is manufactured on the upper surface of the P + wide forbidden band semiconductor contact region 6 and part of the N + wide forbidden band semiconductor source region 9, and a dielectric layer 8 is manufactured on the upper surface of part of the N + wide forbidden band semiconductor source region 9.
Furthermore, the P + wide bandgap semiconductor region 2, the P + silicon carbide contact region 6, the N + wide bandgap semiconductor source region 9 and the P-type wide bandgap semiconductor Well region 10 formed in the present invention can also be formed by directly adopting a multi-time high-energy ion implantation manner without trench etching.
Further, the present invention may form the P + wide bandgap semiconductor region 2 having a lateral width greater than that of the trench by a thermal diffusion process in step 3.
Further, the operations of forming the trench and the P + wide bandgap semiconductor region 2 in the steps 2 and 3 may be replaced by the following operations: the depth of the groove etching is deepened through multiple times of epitaxy, thermal diffusion and etching, so that the P + wide bandgap semiconductor region 2 and the N-wide bandgap semiconductor epitaxial layer 3 are distributed at intervals, and a super junction structure is formed by controlling the width and the doping concentration of the P + wide bandgap semiconductor region 2 and the N-wide bandgap semiconductor epitaxial layer 3.
Further, in the forming of the super junction structure, the step 2 further includes forming a heavily doped N-wide bandgap semiconductor epitaxial layer 3b on top of the N-wide bandgap semiconductor epitaxial layer 3 by an ion implantation process after forming the trench.
Further, in forming the above super junction structure, after forming the P + wide bandgap semiconductor region 2 in step 3, forming a P + + wide bandgap semiconductor region 2b on top of the P + wide bandgap semiconductor region 2 by an ion implantation process is further included.
According to the embodiment of the present invention, the material of the wide bandgap semiconductor is silicon carbide, and the material of the narrow bandgap semiconductor is silicon material, and according to the common general knowledge in the art, other combinations composed of the wide bandgap semiconductor material and the narrow bandgap semiconductor material are also suitable for the device structure provided by the present invention, and the present invention is not limited thereto.
Further, when the narrow bandgap semiconductor deposited in step 6 is silicon, the narrow bandgap semiconductor may be polysilicon or monocrystalline silicon, the polycrystalline silicon may be P-type polysilicon or N-type polysilicon, and the monocrystalline silicon may be P-type monocrystalline silicon or N-type monocrystalline silicon.
According to the invention, by reasonably improving the structure of the device, the narrow-bandgap semiconductor, the dielectric layer, the Well region and the epitaxial layer form a super-barrier structure, and the narrow-bandgap semiconductor in the super-barrier structure and the epitaxial layer form a heterojunction at a contact interface. Through the integration of the functional regions, the problems of large conduction loss, poor reverse recovery characteristic and the like of the conventional PIN diode device are solved. It should be noted that the device structure proposed by the present invention is applicable not only to N-channel devices, but also to P-channel devices.
The principles of the present invention will be explained in detail below by selecting a diode device formed by using silicon carbide as a wide bandgap semiconductor and polysilicon as a narrow bandgap semiconductor, and those skilled in the art can easily obtain the principles of the device by combining other wide and narrow bandgap semiconductor materials according to the following disclosure.
The polysilicon region, the dielectric layer and the Well region in the diode device form a metal (M) -insulator (I) -semiconductor (S) structure (hereinafter referred to as MIS structure), and parameters such as the doping concentration of polysilicon, the thickness and the charge number of the dielectric layer, the doping concentration of the P-type silicon carbide Well region and the like are adjusted through process control, so that the threshold voltage of the MIS structure is smaller than 0.1V. When the voltage applied by the metal anode is close to 0.1V, a small part of electron current flows through the N-wide band gap semiconductor epitaxial layer, the P-type wide band gap semiconductor Well region and the N + wide band gap semiconductor source region due to the existence of the current of the sub-threshold region of the MIS structure. This electron current causes a voltage drop across the Well region of the P-type wide bandgap semiconductor. At the other end of the dielectric layer, since the Si/SiC heterojunction is greater than the forward-direction turn-on voltage of 0.1V, the polysilicon region can be considered to have no current flowing, i.e., the potential of the polysilicon region is the same everywhere. The potential on the two sides of the dielectric layer is gradually increased from top to bottom along the vertical direction of the device, and the difference enables the voltage on the metal anode not to be added to 0.1V (namely the gate voltage of the super barrier structure), so that the device can have obvious current passing, namely the device is conducted. For a conventional power device, the normal operation of the conventional power device needs to be above a higher voltage, and the device structure provided by the invention has a turn-on voltage lower than 0.1V, which can be considered as close to 0V, so that the device structure provided by the invention has an absolute advantage in low-voltage application. Meanwhile, the device has the characteristic of high current density under normal working bias through structural improvement.
The P + wide bandgap semiconductor region and the N-wide bandgap semiconductor epitaxial layer form a bipolar path. The bipolar path exhibits a conductance modulation effect at a large bias voltage. For silicon carbide PIN diodes, a sufficiently high level of conductivity modulation is required to reduce the large resistance of the epitaxial layers. Due to the super barrier diode structure and the existence of Si/SiC heterojunction multi-electron current, the structure of the invention can obtain the same on-state voltage drop as the traditional silicon carbide PIN diode without excessively high conductance modulation level. In other words, in the forward conduction mode, the stored charge of the silicon carbide PIN diode structure provided by the invention is far lower than that of the traditional silicon carbide PIN diode, namely the device structure provided by the invention optimizes the reverse recovery characteristic of the device and reduces the turn-off loss of the device, so that a good compromise characteristic is obtained between the forward conduction voltage drop VF and the turn-off loss Eoff.
The PN junction formed by the P + wide bandgap semiconductor region and the N-wide bandgap semiconductor epitaxial layer can resist voltage in a blocking state, and the voltage blocking capability of the PN junction is basically the same as that of a traditional silicon carbide PIN diode. The proposed structure has lower reverse leakage than conventional silicon carbide PIN diodes due to the very low leakage of the super barrier structure.
Furthermore, the P + wide bandgap semiconductor region and the N-wide bandgap semiconductor epitaxial layer form a super junction structure, so that the voltage blocking capability of the device can be obviously improved, and the better compromise characteristic of forward voltage drop and breakdown voltage is obtained; and because the diode under the super junction structure does not have a low-doped i area, the diode has stronger surge current resistance and can process larger di/dt working conditions.
In order to achieve better reverse recovery characteristics, the present invention also provides two types of multi-sub-devices as shown in fig. 3 and 4. Fig. 3 shows a first multi-sub-device cell structure, in which an N + wide bandgap semiconductor source region is formed on a P-type wide bandgap semiconductor Well region, so that the N + wide bandgap semiconductor source region covers the P-type wide bandgap semiconductor Well region and the originally contacted portion of a metal anode, and the P + wide bandgap semiconductor region is grounded or floated, thereby cutting off a hole current path. In a forward mode of operation, the multi-sub device has a knee voltage close to 0V while having a high minority current density level; in the turn-off process, as no charge storage exists, the reverse recovery characteristic is very good; in the blocking state, the device also has voltage blocking capability similar to that of a traditional silicon carbide PIN device due to the effect of the P + wide bandgap semiconductor region. Fig. 4 shows a cell structure of a second multi-sub device, in which a P-type wide bandgap semiconductor Well region forms a schottky contact with a metal anode, there is no P + silicon carbide contact region and no N + wide bandgap semiconductor source region, the schottky contact is in a reverse bias state when a diode metal anode applies a forward bias voltage, when a voltage of the metal anode is higher than 0.1V, the surface of the P-type wide bandgap semiconductor Well region is inverted to form an electron path, and electrons reaching a schottky reverse bias junction interface from an N + wide bandgap semiconductor substrate through an N-wide bandgap semiconductor epitaxial layer and a surface inversion channel are rapidly pumped away by the anode to form a current, which is a forward conduction current for the diode device. The second multi-sub-device also has good reverse recovery characteristics, as does the first multi-sub-device.
The invention has the beneficial effects that:
the diode device provided by the invention has a forward starting voltage close to 0V, so that the rectification efficiency of the diode is obviously improved, the on-state loss of the device is reduced, and the energy resource is saved.
Secondly, the diode device provided by the invention has the same forward conduction voltage drop VFAnd the conductivity modulation level is lower, so that the number of stored charges is reduced, the reverse recovery time is shortened, the reverse recovery time is reduced, and the reverse recovery characteristic of the device is optimized. Namely, the diode device provided by the invention has a forward conduction voltage drop VFA good compromise is obtained with the reverse recovery charge Qrr.
And thirdly, the diode device provided by the invention has lower electric leakage on the premise of not influencing withstand voltage, thereby having higher reliability and larger safe working area.
The diode device provided by the invention adopts a super junction structure, the voltage blocking capability of the device is obviously improved, and meanwhile, as the low-doped i region does not exist, the diode device can process larger di/dt working conditions and has stronger surge current resistance.
The diode device is convenient and quick in practical application and flexible in application, and the applied functional module can be selected according to specific application conditions, namely a unipolar working mode or a bipolar working mode can be selected to adapt to different application occasions.
Sixth, the diode device provided by the invention can completely work in a multi-sub-device mode through structural improvement, so that the reverse recovery characteristic of the device is further improved, and the diode device has great advantages in application occasions such as high-speed rectification, fast recovery and the like.
Drawings
FIG. 1 is a schematic diagram of a cell structure of a conventional silicon carbide PIN diode device;
fig. 2 is a schematic diagram of a cell structure of a diode device provided in embodiment 1 of the present invention;
fig. 3 is a schematic diagram of a cell structure of a diode device provided in embodiment 2 of the present invention;
fig. 4 is a schematic diagram of a cell structure of a diode device provided in embodiment 3 of the present invention;
fig. 5 is a schematic diagram of a cell structure of a diode device provided in embodiment 4 of the present invention;
FIG. 6 is a schematic diagram showing the arrangement of the metal anode region in three-dimensional space in example 5 of the present invention;
fig. 7 is a schematic diagram of a cell structure of a diode device provided in embodiment 6 of the present invention;
fig. 8 is a functional region division schematic diagram of a diode device provided in embodiment 1 of the present invention;
fig. 9 is a schematic view of a diode device provided in embodiment 1 of the present invention, which is labeled with a1, a2, b1, and b 2;
fig. 10 is a schematic diagram of the potential distribution on both sides of the dielectric layer in the diode device provided in embodiment 1 of the present invention;
fig. 11 is an I-V characteristic curve of each functional region in the diode device provided in embodiment 1 of the present invention;
fig. 12 is an I-V characteristic curve of a diode device provided in embodiment 1 of the present invention;
fig. 13 is a schematic view of a substrate and an epitaxial layer of a diode device provided in embodiment 1 of the present invention;
fig. 14 is a schematic view of a trench formed in the diode device provided in embodiment 1 of the present invention;
fig. 15 is a schematic diagram of a diode device according to embodiment 1 of the present invention, in which a P + wide bandgap semiconductor region is formed;
fig. 16 is a schematic view of a P-type wide bandgap semiconductor Well region formed in the diode device provided in embodiment 1 of the present invention;
fig. 17 is a schematic view of a P + wide bandgap semiconductor contact region formed in the diode device according to embodiment 1 of the present invention;
fig. 18 is a schematic view of a diode device provided in embodiment 1 of the present invention for forming a P + wide bandgap semiconductor source region;
fig. 19 is a schematic view of a diode device formation dielectric layer provided in embodiment 1 of the present invention;
fig. 20 is a schematic diagram of a diode device according to embodiment 1 of the present invention, in which a narrow bandgap semiconductor region is formed;
fig. 21 is a schematic diagram of forming a metal anode and a metal cathode of the diode device provided in embodiment 1 of the present invention.
The numbering in the figures means the following:
1 is a metal anode, 2 is a P + silicon carbide region, 2a is a lightly doped P + silicon carbide region, 2b is a P + + silicon carbide region, 3 is an N-silicon carbide epitaxial layer, 3a is a lightly doped N-silicon carbide epitaxial layer, 3b is a heavily doped N-silicon carbide epitaxial layer, 4 is an N + silicon carbide substrate, 5 is a metal cathode, 6 is a P + silicon carbide contact region, 7 is a polysilicon region, 8 is a dielectric layer, 9 is an N + silicon carbide source region, and 10 is a P-type silicon carbide Well region.
Detailed Description
The structure and fabrication method of the device are described in detail below with reference to the drawings, so that those skilled in the art can clearly understand the technical scheme and principle of the present invention. The specific examples are provided for illustration only and are not intended to limit the scope of the invention.
Although the traditional silicon carbide PIN diode has the advantages of simple process, strong voltage blocking capability, good surge current resistance and the like, the application and popularization of the traditional silicon carbide PIN diode in the market are greatly limited due to the problems of large forward starting voltage (about 3.1V), poor reverse recovery capability and the like. The present invention proposes a structure that can optimize the above-mentioned deficiencies of the silicon carbide PIN diode by structural improvement, as shown in fig. 2 to 6.
Example 1:
a diode device has a cellular structure as shown in figure 2, and comprises a metal cathode 5, an N + silicon carbide substrate 4, an N-silicon carbide epitaxial layer 3 and a metal anode 1 which are sequentially stacked from bottom to top; the two sides of the top layer of the N-silicon carbide epitaxial layer 3 are provided with a trench structure, the trench structure comprises a P + silicon carbide region 2, a P + silicon carbide contact region 6, an N + silicon carbide source region 9 and a P-type silicon carbide Well region 10, the P + silicon carbide region 2 is positioned at the bottom of the trench, the P + silicon carbide contact region 6 and the P-type silicon carbide Well region 10 are positioned on the upper surface of the P + silicon carbide region 2 in parallel, and the N + silicon carbide source region 9 is positioned on the top layer of the P-type silicon carbide Well region 10 and is in contact with the P + silicon carbide contact region 6; the upper surfaces of the P + silicon carbide contact region 6 and part of the N + silicon carbide source region 9 are in contact with the metal anode 1, the upper surfaces of part of the N + silicon carbide source region 9, the P-type silicon carbide Well region 10 and part of the N-silicon carbide epitaxial layer 3 are in contact with the dielectric layer 8, the upper surfaces of the dielectric layer 8 and the N-silicon carbide epitaxial layer 3 are in contact with the polysilicon region 7, the dielectric layer 8, the N + silicon carbide source region 9, the P-type silicon carbide Well region 10 and the N-silicon carbide epitaxial layer 3 form a super barrier structure, the polysilicon region 7 and the N-silicon carbide epitaxial layer 3 form a heterojunction, and the P + silicon carbide region 2 and the N-silicon carbide epitaxial layer 3 form a PN junction.
In this embodiment, the wide bandgap semiconductor is silicon carbide, the narrow bandgap semiconductor is polysilicon, and the parameters of each structure are given below by taking a 1200VN channel diode device as an example: the thickness of the metal anode 1 and the metal cathode 5 is 0.4-2 μm, and the width is 2-5 μm; the doping concentration of the N + silicon carbide substrate 4 is 3e 18-8 e18/cm3The thickness is 0.5 to 2.5 μm, and the width is 2.0 to 5.0 μm; the doping concentration of the N-silicon carbide epitaxial layer 3 is 1e 14-8 e15/cm3The thickness is 5-8 μm, and the width is 2.0-5.0 μm; the P + SiC region 2 has a thickness of about 0.5 to 1.6 μm and a doping concentration of about 5e18 to 6e19/cm3The width is about 0.5-0.7 μm; the width of the polysilicon region 7 is about 2.0 μm to 4.0 μm, and the thickness is about 0.8 μm to 1.6 μm; the thickness of the dielectric layer 8 is about 10 nm-60 nm, and the width is about 0.4 μm-0.6 μm; the P-type silicon carbide Well region 10 has a thickness of about 0.3 μm to about 0.5 μm, a width of about 0.2 μm to about 0.4 μm, and a doping concentration of about 1e15 to about 1e17/cm3(ii) a The N + silicon carbide source region 9 has a thickness of about 0.1 μm to about 0.3 μm, a width of about 0.2 μm to about 0.3 μm, and a doping concentration of about 1e18 to about 7e18/cm3(ii) a The P + SiC contact area 6 has a thickness of about 0.3 μm to about 0.5 μm and a width of about 0.2 μm to about E0.3 μm and a doping concentration of about 1e 18-8 e18/cm3。
According to the invention, by reasonably improving the device structure and forming three functional regions of a super barrier structure (A functional region), a heterojunction (B functional region) and a PN junction (C functional region) as shown in FIG. 8, the comprehensive performance of the device is obviously superior to that of the traditional PIN diode.
The principles and features of the present invention will be described in detail below with reference to specific embodiments:
in this embodiment, an N-channel diode device formed by using silicon carbide as a wide bandgap semiconductor material and polysilicon as a narrow bandgap semiconductor material is taken as an example to explain the principle and characteristics of the present invention in detail, and a person skilled in the art can derive the principle of a P-channel diode device and the principle of a diode device formed by combining the remaining wide and narrow bandgap semiconductor materials according to the following disclosure:
aiming at the problems of large forward starting voltage (about 3.1V of a silicon carbide PIN diode), poor reverse recovery capability and the like of the traditional PIN diode, the invention reasonably improves the structure of the device to optimize the performance.
In the diode device provided by the invention, the polysilicon region 7, the dielectric layer 8 and the P-type silicon carbide Well region 10 form a metal (M) -insulator (I) -semiconductor (S) structure (hereinafter referred to as MIS structure), and parameters such as the doping concentration of the polysilicon region 7, the thickness and the charge number of the dielectric layer 8, the doping concentration of the P-type silicon carbide Well region 10 and the like are adjusted through process control, so that the threshold voltage of the MIS structure is smaller than 0.1V. When the voltage applied by the metal anode 1 is close to 0.1V, a small part of electron current flows through the N-silicon carbide epitaxial layer 3, the P-type silicon carbide Well region 10 and the N + silicon carbide source region 9 due to the existence of the current of the sub-threshold region of the MIS structure. This electron current causes a voltage drop across the P-type silicon carbide Well region 10. At the other end of the dielectric layer 8, since the Si/SiC heterojunction is greater than the forward-direction turn-on voltage of 0.1V, it can be considered that no current flows through the polysilicon region, i.e., the potential of the polysilicon region 7 is the same everywhere. Referring to fig. 10, which is a potential distribution diagram of both sides of the dielectric layer 8, a1, a2, b1 and b2 are labeled in fig. 9, and it can be seen that the potential difference between points a1 and a2 is almost zero, and the potential difference increases from top to bottom in the vertical direction from point a to point b. This difference makes it unnecessary to apply a voltage to the metal anode of 0.1V (i.e., the gate voltage of the super barrier structure), and the device will have a significant current flow, i.e., the device is already on. For a conventional power device, the normal operation of the conventional power device needs to be above a higher voltage, and the device structure provided by the invention has a turn-on voltage lower than 0.1V, which can be considered as close to 0V, so that the device structure provided by the invention has an absolute advantage in low-voltage application. Meanwhile, the device has the characteristic of high current density under normal working bias through structural improvement.
In the case of neglecting the resistance, the I-V characteristic curve of a single functional region is shown in FIG. 11, wherein A, B, C three functional regions are shown in FIG. 8, wherein A is a super barrier structure, B is a Si/SiC heterojunction, and C is a SiC PN junction. In the present embodiment, the P-type polysilicon is taken as an example for detailed description, and those skilled in the art can derive the principle of N-type polysilicon based on the above. A. B, C the forward opening voltage drops of three functional regions, i.e. super barrier structure, Si/SiC heterojunction and silicon carbide PN junction are about 0V, 1.1V and 3.1V respectively. Along with the increase of the voltage applied to the metal anode 1, the voltage drop at the two ends of the Si/SiC heterojunction and the silicon carbide PIN diode is increased, and when the voltages at the two ends of the Si/SiC heterojunction and the silicon carbide PIN diode reach 1.1V and 3.1V respectively, the Si/SiC heterojunction and the silicon carbide PIN diode are respectively conducted. For the sake of explanation in principle, assuming that the Si/SiC heterojunction conducts before the silicon carbide PIN diode, the I-V characteristic curve of the diode device is shown in fig. 12. Curve a in fig. 12 represents the case where only the super barrier structure is on; the curve A + B represents the conduction condition of the super barrier structure and the Si/SiC heterojunction; and the curve A + B + C represents the condition that the super barrier structure, the Si/SiC heterojunction and the silicon carbide PN junction are both conducted. Although the diode device provided by the invention still belongs to a bipolar device under the condition that the super barrier structure, the heterojunction and the PN junction are conducted, namely the conductance modulation effect can occur under the condition of large injection, the diode device provided by the invention has a lower conductance modulation level under the same voltage drop. As described above, the P + silicon carbide region 2 forms a bipolar path with the N-silicon carbide epitaxial layer 3. The bipolar path exhibits a conductance modulation effect at a large bias voltage. For silicon carbide PIN diodes, a sufficiently high level of conductivity modulation is required to reduce the large resistance of the epitaxial layers. Due to the super barrier diode structure and the existence of Si/SiC heterojunction multi-electron current, the structure of the invention can obtain the same on-state voltage drop as the traditional silicon carbide PIN diode without excessively high conductance modulation level. In other words, in the forward conduction mode, the storage charge of the silicon carbide PIN diode structure provided by the invention is far lower than that of the traditional silicon carbide PIN diode, namely the device structure provided by the invention optimizes the reverse recovery characteristic of the device and reduces the turn-off loss of the device, so that a good compromise characteristic is obtained between the forward conduction voltage drop VF and the reverse recovery charge Qrr.
The PN junction formed by the P + silicon carbide region and the N-silicon carbide epitaxial layer can resist voltage in a blocking state, and the voltage blocking capability of the PN junction is basically the same as that of a traditional silicon carbide PIN diode. The proposed structure has lower reverse leakage than conventional silicon carbide PIN diodes due to the very low leakage of the super barrier structure.
Example 2:
a diode device has a cellular structure as shown in FIG. 3, and comprises a metal cathode 5, an N + silicon carbide substrate 4, an N-silicon carbide epitaxial layer 3 and a metal anode 1 which are sequentially stacked from bottom to top; two sides of the top layer of the N-silicon carbide epitaxial layer 3 are provided with a trench structure, the trench structure comprises a P + silicon carbide region 2, an N + silicon carbide source region 9 and a P-type silicon carbide Well region 10, the P + silicon carbide region 2 is positioned at the bottom of the trench, the P-type silicon carbide Well region 10 is positioned on the upper surface of the P + silicon carbide region 2, and the N + silicon carbide source region 9 is positioned on the top layer of the P-type silicon carbide Well region 10; the upper surface of part of the N + silicon carbide source region 9 is in contact with the metal anode 1, the upper surfaces of part of the N + silicon carbide source region 9, the P-type silicon carbide Well region 10 and part of the N-silicon carbide epitaxial layer 3 are in contact with the dielectric layer 8, the dielectric layer 8 is in contact with the upper surface of the N-silicon carbide epitaxial layer 3 and the polysilicon region 7, the dielectric layer 8, the N + silicon carbide source region 9, the P-type silicon carbide Well region 10 and the N-silicon carbide epitaxial layer 3 form a super barrier structure, the polysilicon region 7 and the N-silicon carbide epitaxial layer 3 form a heterojunction, and the P + silicon carbide region 2 and the N-silicon carbide epitaxial layer 3 form a PN junction.
Compared with the embodiment 1, the embodiment does not provide the P + silicon carbide contact region 6, and the N + silicon carbide source region 9 covers the contact part of the metal anode 1 and the P-type silicon carbide Well region 10, so as to form the N + silicon carbide source region 9 with the width of 0.4-0.6 μm, the doping of 1e 17-1 e18/cm3 and the thickness of 0.1-0.3 μm. Meanwhile, the P + silicon carbide region 2 is floated or grounded. The arrangement can block the hole current path, so that the invented device can work in a unipolar mode. The improvements of this embodiment have a positive impact on the wide application of the device in high speed, fast recovery applications.
Example 3:
a diode device, the cellular structure of which is shown in figure 4, comprises a metal cathode 5, an N + silicon carbide substrate 4, an N-silicon carbide epitaxial layer 3 and a metal anode 1 which are sequentially stacked from bottom to top; the two sides of the top layer of the N-silicon carbide epitaxial layer 3 are provided with a trench structure, the trench structure comprises a P + silicon carbide region 2 and a P-type silicon carbide Well region 10, the P + silicon carbide region 2 is positioned at the bottom of the trench, and the P-type silicon carbide Well region 10 is positioned on the upper surface of the P + silicon carbide region 2; the upper surface of part of the P-type silicon carbide Well region 10 is contacted with the metal anode 1, and the upper surfaces of part of the P-type silicon carbide Well region 10 and part of the N-silicon carbide epitaxial layer 3 are provided with a dielectric layer 8 contacted with the upper surfaces; the dielectric layer 8 and the upper surface of part of the N-silicon carbide epitaxial layer 3 are provided with a polysilicon region 7 in contact with the upper surface; the polycrystalline silicon region 7, the dielectric layer 8, the P-type silicon carbide Well region 10 and the N-silicon carbide epitaxial layer 3 form a super barrier structure, the polycrystalline silicon region 7 and the N-silicon carbide epitaxial layer 3 form a heterojunction, and the P + silicon carbide region 2 and the N-silicon carbide epitaxial layer 3 form a PN junction.
In this embodiment, the P-type silicon carbide Well region 10 is in direct contact with the metal anode 1 to form a schottky contact. When the anode of the diode is forward biased, the Schottky contact is in a reverse biased state. Once there is excess minority carriers in the P-type silicon carbide Well region 10, the minority carriers will be swept towards the metal anode 1. When the voltage applied to the metal anode 1 is higher than 0.1V, excess minority carriers will appear in the P-type silicon carbide Well region 10, and the excess minority carriers are rapidly pumped away by the metal anode 1 to form a current. This current is a forward conducting current for the diode device. The current in this mode of operation is unipolar, so that the inventive device operates in unipolar mode. Like embodiment 2, this embodiment also facilitates the popularization of the device in high-speed applications.
Example 4:
the schematic diagram of the cell structure of the diode device provided in this embodiment is shown in fig. 5, and the difference compared with embodiment 1 is that: the lateral width of the P + silicon carbide region 2 is made larger. Compared with embodiment 2, the larger the lateral width of the P + silicon carbide region 2 is, the stronger the electric field shielding effect on the region above the P + silicon carbide region 2 is when the device is in the blocking state, which not only protects the structures such as the heterojunction and the super barrier structure, but also improves the voltage withstanding performance of the device. It is to be noted that the wider the width of the P + silicon carbide region 2, the greater the on-resistance when the device is operating in the forward direction. The width of the P + silicon carbide region 2 needs to be balanced between forward and reverse operation.
Example 5:
the difference between the cell structure of the diode device provided by this embodiment and that of embodiment 1 is: the P + silicon carbide region 2 forms a super junction structure with the N-silicon carbide epitaxial layer 3. By controlling and adjusting the process parameters, the N columns, i.e., the N-silicon carbide epitaxial layer 3, and the P columns, i.e., the P + silicon carbide regions 2 satisfy Qn — Qp.
The super junction structure introduced in the embodiment can improve the voltage blocking capability of the device by optimizing the electric field distribution in the blocking mode, so that better compromise characteristics of forward voltage drop and breakdown voltage are obtained; meanwhile, the super junction structure can improve the epitaxial concentration, so that the device can bear larger di/dt impact, and the device has higher surge current resistance.
Example 6:
the schematic diagram of the cell structure of the diode device provided by this embodiment is shown in fig. 6, and the difference compared with embodiment 5 is that: a heavily doped N-silicon carbide epitaxial layer 3b is formed on the top of the N-silicon carbide epitaxial layer 3, and a lightly doped N-silicon carbide epitaxial layer 3a is formed below the top.
Example 7:
the schematic diagram of the cell structure of the diode device provided in this embodiment is shown in fig. 7, and the difference compared with embodiment 6 is that: a P + + silicon carbide region 2b is formed on the top of the P + silicon carbide region 2, and a lightly doped P + silicon carbide region 2a is formed below the top.
Compared with embodiment 6, in the case that the N column (i.e., N-silicon carbide epitaxial layer 3) and the P column (i.e., P + silicon carbide region 2) are fully depleted, the present embodiment can better protect the super barrier structure, the Si/SiC heterojunction structure, etc. above the N column, thereby improving the reliability of the device and expanding the safe operating region.
Example 8:
a manufacturing method of a diode device is characterized by comprising the following steps:
step 1: as shown in fig. 13, a silicon carbide wafer with appropriate resistivity and thickness is selected as the N + silicon carbide substrate 4 and the N-silicon carbide epitaxial layer 3, wherein the doping concentration of the N + silicon carbide substrate 4 is 3e 18-8 e18/cm3The thickness is 0.5-2.5 μm, and the width is 2.0-5.0 μm; the doping concentration of the N-silicon carbide epitaxial layer 3 is 1e 14-8 e15/cm3The thickness is 5-8 μm;
step 2: through a groove etching process, grooves with the width of about 0.3-0.5 μm, the depth of about 1.1-1.8 μm and the width of about 0.5-0.7 are etched on two sides of the N-silicon carbide epitaxial layer 3 by utilizing a Trench mask, as shown in FIG. 14;
and step 3: depositing a P-type silicon carbide material at the bottom of the trench by deposition and etching processes, and removing the unnecessary P-type silicon carbide material by etching to form a P + silicon carbide region 2 with a thickness of about 0.5-1.6 μm and a doping concentration of about 5e 18-6 e19/cm3, as shown in FIG. 15;
and 4, step 4: depositing a P-type silicon carbide material on the P + silicon carbide region 2 by deposition and etching processes, and removing the unnecessary P-type silicon carbide material by etching to form a P-type silicon carbide Well region 10 with the thickness of about 0.3-0.5 μm, the width of 0.2-0.4 μm and the doping concentration of about 1e 15-1 e17/cm3, as shown in FIG. 16;
and 5: performing aluminum ion implantation at 450-550 ℃ by using a PSD mask through the processes of photoetching, ion implantation and the like, wherein the implantation energy is about 1400-1700 keV, and a P + silicon carbide contact region 6 with the thickness of about 0.3-0.5 mu m, the width of about 0.2-0.3 mu m and the doping of about 1e 18-8 e18/cm3 is formed, as shown in FIG. 17;
step 6: through the processes of photoetching, ion implantation and the like, phosphorus ion implantation is carried out at the temperature of 450-550 ℃ by utilizing a PSD mask, the implantation energy is about 1300-1700 keV, and an N + silicon carbide source region 9 with the thickness of about 0.1-0.3 mu m, the width of about 0.2-0.3 mu m and the doping of about 1e 18-7 e18/cm3 is formed, as shown in figure 18;
and 7: depositing a dielectric layer material on the upper surfaces of the P-type silicon carbide Well region 10 and the N-silicon carbide epitaxial layer 3 through a dry oxygen oxidation or deposition process, and removing the redundant dielectric layer material through etching to form a dielectric layer 8 covering a part of the P-type silicon carbide Well region 10 and a part of the N-silicon carbide epitaxial layer 3, as shown in FIG. 19;
and 8: depositing polysilicon on the dielectric layer 8 and the upper surface of the N-silicon carbide epitaxial layer 3 by deposition and etching processes, and removing excessive polysilicon material by etching to form a polysilicon region 7 with a width of about 2.0 to 4.0 μm and a thickness of about 0.8 to 1.6 μm on the dielectric layer 8 and the N-silicon carbide epitaxial layer 3, as shown in FIG. 20;
and step 9: through deposition, photoetching and etching processes, a metal anode 1 is formed on the upper surfaces of the polysilicon region 7, the dielectric layer 8 and the P-type silicon carbide Well region 10, and a metal cathode 5 is formed on the back surface of the device by turning over the device, as shown in fig. 21, so that the device is manufactured.
Further, in steps 2 to 6 of this embodiment, the P + silicon carbide region 2, the P + silicon carbide contact region 6, the N + silicon carbide source region 9, and the P-type silicon carbide Well region 10 are formed through trench etching, deposition, photolithography, and other processes, and may also be formed by multiple times of high-energy ion implantation without trench etching.
Further, when trenches are formed by etching using the Trench mask in step 2 of this embodiment, a depth of 5.0 μm to 8.0 μm may also be etched, P + silicon carbide regions 2P columns and N-silicon carbide epitaxial layers 3N columns formed by multiple times of epitaxy, thermal diffusion and etching are alternately distributed, and a super junction structure is formed by controlling widths and doping concentrations of the P + silicon carbide regions 2 and the N-silicon carbide epitaxial layers 3.
Furthermore, when the super junction structure is formed, a heavily doped N-silicon carbide epitaxial layer 3a is formed on the top of the N-silicon carbide epitaxial layer 3 through an ion implantation process, so that the device structure shown in fig. 6 can be obtained.
Furthermore, on the basis of forming the heavily doped N-silicon carbide epitaxial layer 3a on the top of the N-silicon carbide epitaxial layer 3 by an ion implantation process during the formation of the super junction structure, ion implantation is performed again in the top end region of the P + silicon carbide region 2 to form a P + + silicon carbide region 2b with a doping concentration of 8e 18-7 e19/cm3, so as to obtain the device structure shown in fig. 7.
Further, in this embodiment, after the P + silicon carbide is epitaxially grown or deposited in step 3, a thermal diffusion may be performed to form a P + silicon carbide region 2 with a lateral width of 0.5 μm to 0.9 μm.
Further, the step 5 is preceded by the steps of: an N + silicon carbide source region 9 is formed on the top layer of the P-type silicon carbide Well region 10 through photoetching and ion implantation processes.
Further, step 5 of this embodiment may be omitted, that is, the operation of forming the P + silicon carbide contact region 6 is omitted, and the step 6 is directly proceeded to, and in step 6, the size of the NSD mask is adjusted, so that the N + silicon carbide source region 9 covers the contact portion between the metal anode 1 and the P-type silicon carbide Well region 10, and the N + silicon carbide source region 9 with the width of 0.4 μm to 0.6 μm and the doping thickness of 1e17 to 1e18/cm3 of 0.1 μm to 0.3 μm is formed, so as to obtain the device structure shown in fig. 3.
Furthermore, when the N + silicon carbide source region 9 covers the contact portion of the metal anode 1 and the P-type silicon carbide Well region 10 to form the N + silicon carbide source region 9 located between the P-type silicon carbide Well region 10 and the metal anode 1, the P + silicon carbide region 2 in step 7 of the present invention can be either grounded or float.
Further, in this embodiment, steps 5 and 6 can be omitted, and the P-type silicon carbide Well region 10 is in direct contact with the metal anode 1 to form a schottky contact, so as to obtain the device structure shown in fig. 4.
Further, the step 5 is preceded by the steps of: through photoetching and ion implantation processes, a P + silicon carbide contact region 6 which is parallel to the P type silicon carbide Well region 10 is formed on the upper surface of the P + silicon carbide region 2, and an N + silicon carbide source region 9 which is in contact with the P + silicon carbide contact region 6 is formed in the P type silicon carbide Well region 10.
Further, the narrow bandgap semiconductor deposited in step 6 is not limited to polysilicon, and may also be monocrystalline silicon, where the polysilicon may be P-type polysilicon or N-type polysilicon, and the monocrystalline silicon may be P-type monocrystalline silicon or N-type monocrystalline silicon.
It should also be claimed that: as can be seen from the basic knowledge in the art, the wide bandgap semiconductor and the narrow bandgap semiconductor materials used in the diode device structure and the fabrication method of the diode device structure disclosed in the present invention are not limited to the silicon carbide and the silicon material disclosed in the present embodiment, and other combinations composed of the wide bandgap semiconductor material and the narrow bandgap semiconductor material are also suitable for the device structure provided in the present invention, and the present invention is not limited thereto; the material for forming the dielectric layer can be implemented by any suitable high-K dielectric material such as silicon dioxide (SiO2), silicon nitride (Si3N4), hafnium dioxide (HfO2), aluminum oxide (Al2O3) and the like, besides silicon dioxide (SiO 2); meanwhile, the specific implementation mode of the manufacturing process can be adjusted according to actual needs.
Claims (6)
1. A diode device comprises a cellular structure, a metal cathode (5), an N + wide bandgap semiconductor substrate (4), an N-wide bandgap semiconductor epitaxial layer (3) and a metal anode (1) which are sequentially stacked from bottom to top; two sides of the top layer of the N-wide forbidden band semiconductor epitaxial layer (3) are provided with groove structures, each groove structure comprises a P + wide forbidden band semiconductor region (2) and a P type wide forbidden band semiconductor Well region (10), the P + wide forbidden band semiconductor region (2) is positioned at the bottom of each groove, and the P type wide forbidden band semiconductor Well region (10) is positioned on the upper surface of the P + wide forbidden band semiconductor region (2); the upper surface of part of the P-type wide bandgap semiconductor Well area (10) is contacted with the metal anode (1), and the upper surfaces of the part of the P-type wide bandgap semiconductor Well area (10) and the part of the N-wide bandgap semiconductor epitaxial layer (3) are provided with a dielectric layer (8) contacted with the upper surface; the dielectric layer (8) and the upper surface of part of the N-wide bandgap semiconductor epitaxial layer (3) are provided with a narrow bandgap semiconductor region (7) which is in contact with the dielectric layer and the upper surface of the part of the N-wide bandgap semiconductor epitaxial layer; the narrow forbidden band semiconductor region (7), the dielectric layer (8), the P-type wide forbidden band semiconductor Well region (10) and the N-wide forbidden band semiconductor epitaxial layer (3) form a super barrier structure, the narrow forbidden band semiconductor region (7) and the N-wide forbidden band semiconductor epitaxial layer (3) form a heterojunction, and the P + wide forbidden band semiconductor region (2) and the N-wide forbidden band semiconductor epitaxial layer (3) form a PN junction;
the P-type wide bandgap semiconductor Well region (10) and the metal anode (1) form Schottky contact;
the threshold voltage of an MIS structure formed by the narrow band gap semiconductor region (7), the dielectric layer (8) and the P type wide band gap semiconductor Well region (10) is less than 0.1V.
2. A diode device according to claim 1, wherein: the P + wide bandgap semiconductor region (2) and the N-wide bandgap semiconductor epitaxial layer (3) form a super junction structure; the doping concentration of the top layer of the N-wide bandgap semiconductor epitaxial layer (3) is higher than that of the lower part of the top layer; the doping concentration of the top layer of the P + wide bandgap semiconductor region (2) is higher than the doping concentration below the top layer.
3. A diode device comprises a cellular structure, a metal cathode (5), an N + wide bandgap semiconductor substrate (4), an N-wide bandgap semiconductor epitaxial layer (3) and a metal anode (1) which are sequentially stacked from bottom to top; two sides of the top layer of the N-wide forbidden band semiconductor epitaxial layer (3) are provided with groove structures, each groove structure comprises a P + wide forbidden band semiconductor region (2) and a P type wide forbidden band semiconductor Well region (10), the P + wide forbidden band semiconductor region (2) is positioned at the bottom of each groove, and the P type wide forbidden band semiconductor Well region (10) is positioned on the upper surface of the P + wide forbidden band semiconductor region (2); the upper surfaces of a part of P-type wide bandgap semiconductor Well area (10) and a part of N-type wide bandgap semiconductor epitaxial layer (3) are provided with dielectric layers (8) contacted with the upper surfaces; the dielectric layer (8) and the upper surface of part of the N-wide bandgap semiconductor epitaxial layer (3) are provided with a narrow bandgap semiconductor region (7) which is in contact with the dielectric layer and the upper surface of the part of the N-wide bandgap semiconductor epitaxial layer; the narrow forbidden band semiconductor region (7), the dielectric layer (8), the P-type wide forbidden band semiconductor Well region (10) and the N-wide forbidden band semiconductor epitaxial layer (3) form a super barrier structure, the narrow forbidden band semiconductor region (7) and the N-wide forbidden band semiconductor epitaxial layer (3) form a heterojunction, and the P + wide forbidden band semiconductor region (2) and the N-wide forbidden band semiconductor epitaxial layer (3) form a PN junction;
the semiconductor device further comprises a P + wide forbidden band semiconductor contact region (6) and an N + wide forbidden band semiconductor source region (9), wherein the P + wide forbidden band semiconductor contact region (6) and the P type wide forbidden band semiconductor Well region (10) are arranged on the upper surface of the P + wide forbidden band semiconductor region (2) in parallel, the N + wide forbidden band semiconductor source region (9) is arranged on the top layer of the P type wide forbidden band semiconductor Well region (10), and the P + wide forbidden band semiconductor contact region (6) is in contact with the N + wide forbidden band semiconductor source region (9); the upper surfaces of the P + wide bandgap semiconductor contact region (6) and the partial N + wide bandgap semiconductor source region (9) are contacted with the metal anode (1), and the upper surface of the partial N + wide bandgap semiconductor source region (9) is contacted with the dielectric layer (8);
the threshold voltage of an MIS structure formed by the narrow band gap semiconductor region (7), the dielectric layer (8) and the P type wide band gap semiconductor Well region (10) is less than 0.1V.
4. A diode device as claimed in claim 1 or 3, wherein: the P + wide bandgap semiconductor region (2) is short-circuited to ground or is arranged in a floating manner.
5. A diode device as claimed in claim 1 or 3, wherein: the width of the P + wide bandgap semiconductor region (2) is larger than the width of the trench.
6. A manufacturing method of a diode device is characterized by comprising the following steps:
step 1: selecting a wide bandgap semiconductor material as an N + wide bandgap semiconductor substrate (4) and an N-wide bandgap semiconductor epitaxial layer (3);
step 2: forming grooves on two sides of the N-wide bandgap semiconductor epitaxial layer (3) through a groove etching process;
and step 3: depositing and etching process or ion implantation process on the bottom of the groove or implanting P-type wide bandgap semiconductor material below the groove to form a P + wide bandgap semiconductor region (2);
and 4, step 4: forming a P-type wide bandgap semiconductor Well region (10) on the upper surface of the P + wide bandgap semiconductor region (2) through a deposition and etching process or an epitaxial process;
and 5: depositing a dielectric layer material on the upper surfaces of the P-type wide bandgap semiconductor Well region (10) and the N-wide bandgap semiconductor epitaxial layer (3) through a dry oxygen oxidation or deposition process, and removing the redundant dielectric layer material through etching to form a dielectric layer (8) covering a part of the P-type wide bandgap semiconductor Well region (10) and a part of the N-wide bandgap semiconductor epitaxial layer (3);
step 6: depositing a narrow bandgap semiconductor material on the dielectric layer (8) and the upper surface of the N-wide bandgap semiconductor epitaxial layer (3) through deposition and etching processes, and removing the redundant narrow bandgap semiconductor material through etching to form a narrow bandgap semiconductor region (7) positioned above the dielectric layer (8) and the N-wide bandgap semiconductor epitaxial layer (3);
and 7: forming a metal anode (1) on the upper surfaces of a narrow forbidden band semiconductor region (7), a dielectric layer (8) and a P-type wide forbidden band semiconductor Well region (10) through deposition, photoetching and etching processes, wherein the P-type wide forbidden band semiconductor Well region (10) and the metal anode (1) form Schottky contact; and turning the device to form a metal cathode (5) on the back surface, thus finishing the manufacture of the device.
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