CN108550630A - A kind of diode and preparation method thereof - Google Patents
A kind of diode and preparation method thereof Download PDFInfo
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- CN108550630A CN108550630A CN201810553843.2A CN201810553843A CN108550630A CN 108550630 A CN108550630 A CN 108550630A CN 201810553843 A CN201810553843 A CN 201810553843A CN 108550630 A CN108550630 A CN 108550630A
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- 230000004888 barrier function Effects 0.000 claims abstract description 22
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- 238000005530 etching Methods 0.000 claims description 20
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 37
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- 239000010703 silicon Substances 0.000 description 37
- 239000013078 crystal Substances 0.000 description 22
- 238000010586 diagram Methods 0.000 description 22
- 229910003978 SiClx Inorganic materials 0.000 description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 19
- 229920005591 polysilicon Polymers 0.000 description 15
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
Abstract
A kind of diode component and preparation method thereof, belongs to power semiconductor device technology field.The structure cell of device includes metallic cathode, N+ substrates and N epitaxial layers and metal anode, the top layer both sides of N epitaxial layers have groove structure, groove structure includes P+ semiconductor regions and the areas P-type semiconductor Well from bottom to top, the areas P-type semiconductor Well are in contact with the metal anode above it, and there are dielectric layer in the part areas P-type semiconductor Well and N semiconductor epitaxial layers upper surface；Dielectric layer has heterogeneous semiconductor with N semiconductor epitaxial layers upper surface；Heterogeneous semiconductor, dielectric layer, the areas P-type semiconductor Well and N semiconductor epitaxial layers form super barrier structure.The present invention significantly reduces traditional PI N device forward direction cut-in voltage, optimizes device reverse recovery characteristic under the premise of not influencing device performance, obtains good compromise characteristic between forward conduction voltage drop and turn-off power loss.In addition, device of the present invention additionally provides multiple-working mode selection, practical application is greatly facilitated.
Description
Technical field
The invention belongs to power semiconductor device technology field, more particularly to a kind of diode and preparation method thereof.
Background technology
Energy resources are the important substance bases that the mankind depended on and realized development for existence, are that the mankind carry out the dynamic of production and living
Power source.Many energy resources are inexhaustible, nexhaustible, such as wind energy, solar energy and tide energy.However in production and living
Used main energy sources are non-renewable energy resources, including fossil energy, coal and natural gas etc., have thus caused the whole world
Energy crisis.Since the 21th century from the mankind, which more attracts people's attention.How to reduce need not in production and living
How the energy loss wanted improves the utilization rate of energy resources, be the important means for alleviating global energy crisis.Electric energy conduct
One of the energy that the mankind can directly use is indispensable already in life.Electric system is human use's electric energy and carries
The necessary ways of high electric energy service efficiency, electric system transports electric energy, manages and the height of service efficiency, embodies electric power
The up-to-dateness of system, and then embody height of the mankind for energy resources utilization ratio.And according to statistics, in the world 90%
Above electric energy by power device by electric power system control.For certain angle, the control electric energy efficiency of power device
Height, concerning human kind sustainable development.
Power diode is electronic component the simplest in many power semiconductor devices, but is also that application is the widest
One of general device plays very crucial effect in circuit.Therefore, the performance of power diode often sets as circuit
Count one of the key factor of success.Power diode generally uses P+N-N+ structures as shown in Figure 1, when device is in just
When to bias state, the low doped region of P+N-N+ structure diodes will usually be driven to big injection state.In this state
Under intermediate region be with no doping (intrinsic), therefore P+N-N+ diodes PIN is commonly referred to as bis- poles PIN
Pipe.For PIN diode as a kind of bipolar device, the conductivity modulation effect that forward conduction generates in the process can significantly reduce it
Forward voltage drop, however, since there are excessive carriers in drift region when shutdown, this also causes it to exist when off can not
The turn-off power loss avoided extends the turn-off time, and then affects PIN diode reverse recovery characteristic, is unfavorable for it in high speed
The application of the occasions such as rectification, fast recovery.And the reverse recovery characteristic of PIN diode is most important for power electronic system.
Meanwhile with the increasingly maturation of power semiconductor technologies, the characteristic of silicon-based power devices has gradually approached its theory
The limit.It is also noted that carbon while researcher makes every effort to find more preferably parameter in the narrow optimization space of silicon-based power devices
The third generations wide bandgap semiconductor materials such as SiClx (SiC), gallium nitride (GaN) are in high-power, high-frequency, high temperature resistant, radioresistance etc.
Excellent material property in field.Wherein, the semiconductor material with wide forbidden band that silicon carbide power diode component is used by it ---
Silicon carbide is notable to the reducing effect of power attenuation, so insider's silicon carbide power semiconductor devices are referred to as that " new energy is removed from office
" green energy resource " device of life ".In addition to this carbofrax material also has many attracting characteristics, such as 10 times of silicon materials
Critical breakdown electric field intensity, high thermal conductivity, big energy gap and high electronics saturation drift velocity etc., these performances are excellent
Gesture makes carbofrax material become the research hotspot of power semiconductor in the world.But in silicon carbide power diode component
The drawbacks of development also shows semiconductor material with wide forbidden band while reaching its maturity：The broad stopband of semi-conducting material can cause larger
Knee-point voltage, by taking silicon carbide as an example, silicon carbide PIN diode device forward conduction voltage drop is 3.1V or so, and bis- poles silicon PIN
The forward conduction voltage drop of pipe is only 0.7V or so, and in contrast silicon carbide PIN diode device significantly increases conduction loss, drop
Low rectification efficiency, results in the serious waste of energy resources.And " green industry " theory that this is emphasized with today's society height
It disagrees.
Invention content
In view of described above, it is an object of the invention to：For PIN diode in the prior art there are conduction loss compared with
Greatly, the problems such as reverse recovery characteristic is poor, it is proposed that low forward conduction voltage, optimization reverse recovery characteristic can drop in one kind, simultaneously
The diode device structure of high voltage blocking ability can also be kept, which is suitable for various semi-conducting materials；Simultaneously originally
Invention additionally provides the preparation method of this kind of diode component.
On the one hand the present invention provides a kind of diode component, and structure cell includes the gold being cascading from bottom to top
Belong to cathode 5, N+ wide bandgap semiconductors substrate 4, N- wide bandgap semiconductors epitaxial layer 3 and metal anode 1；Outside N- wide bandgap semiconductors
The top layer both sides for prolonging layer 3 have groove structure, and the groove structure includes that P+ wide bandgap semiconductors area 2 and p-type broad stopband are partly led
The areas body Well 10, P+ wide bandgap semiconductors area 2 are located at channel bottom, and the areas p-type wide bandgap semiconductor Well 10 are located at the broad stopbands P+
2 upper surface of semiconductor region；The upper surface in the part areas p-type wide bandgap semiconductor Well 10 is in contact with metal anode 1, part p-type
The areas wide bandgap semiconductor Well 10 and the upper surface of part N- wide bandgap semiconductors epitaxial layer 3 have the dielectric layer 8 contacted；
Dielectric layer 8 has the low-gap semiconductor area 7 contacted with 3 upper surface of part N- wide bandgap semiconductors epitaxial layer；It is described narrow
Bandgap semiconductor area 7, dielectric layer 8, the areas p-type wide bandgap semiconductor Well 10 and N- wide bandgap semiconductors epitaxial layer 3 form super
Barrier structure, the low-gap semiconductor area 7 form hetero-junctions, P+ wide bandgap semiconductors with N- wide bandgap semiconductors epitaxial layer 3
Area 2 forms PN junction with N- wide bandgap semiconductors epitaxial layer 3.
Further, the invention also includes the N+ wide bandgap semiconductors source region 9 being in direct contact with metal anode 1, N+ wide taboos
It is located at the top layer in the areas p-type wide bandgap semiconductor Well 10 with semiconductor source region 9, the areas p-type wide bandgap semiconductor Well 10 pass through N+
Wide bandgap semiconductor source region 9 is isolated with metal anode 1, upper surface and 8 phase of dielectric layer of part N+ wide bandgap semiconductors source region 9
Contact.
Further, the invention also includes P+ wide bandgap semiconductors contact zone 6, P+ wide bandgap semiconductors contact zones 6
It is located at 2 upper surface of P+ wide bandgap semiconductors area side by side with the areas p-type wide bandgap semiconductor Well 10, and P+ wide bandgap semiconductors contact
Area 6 is in contact with N+ wide bandgap semiconductors source region 9；P+ wide bandgap semiconductors contact zone 6 and part N+ wide bandgap semiconductors source region 9
Upper surface is in contact with metal anode 1, and the upper surface of part N+ wide bandgap semiconductors source region 9 is in contact with dielectric layer 8.
Further, the present invention in P+ wide bandgap semiconductors area 2 width be more than groove width.
Further, P+ wide bandgap semiconductors area 2 forms superjunction knot with N- wide bandgap semiconductors epitaxial layer 3 in the present invention
Structure；According to common sense well known to those skilled in the art, P+ wide bandgap semiconductors area 2 and N- wide bandgap semiconductors epitaxial layer 3 meet Qp
The demand of=Qn.
It is preferred that when P+ wide bandgap semiconductors area 2 and N- wide bandgap semiconductors epitaxial layer 3 form super-junction structure
When, the doping concentration of 3 top layer of N- wide bandgap semiconductors epitaxial layer compares the doping concentration higher under its top layer.
It is preferred that when P+ wide bandgap semiconductors area 2 and N- wide bandgap semiconductors epitaxial layer 3 form super-junction structure
When, the doping concentration of 2 top layer of P+ wide bandgap semiconductors area compares the doping concentration higher under its top layer.
According to embodiments of the present invention, the material of the wide bandgap semiconductor is silicon carbide, the material of the low-gap semiconductor
Material is silicon materials, other to be made of semiconductor material with wide forbidden band and low-gap semiconductor material according to general knowledge known in this field
Combination is equally applicable for device architecture provided by the invention, and the present invention is without limitation.
Further, when the material of low-gap semiconductor is silicon materials, low-gap semiconductor can be that polysilicon also may be used
Think that monocrystalline silicon, polysilicon can be that p-type polysilicon may be N-type polycrystalline silicon, monocrystalline silicon can be that p type single crystal silicon can also
For n type single crystal silicon.
Further, P+ wide bandgap semiconductors area 2 can be with ground short circuit, can also floating setting.
On the other hand the present invention provides a kind of production method of diode component, which is characterized in that includes the following steps：
Step 1：Select semiconductor material with wide forbidden band as N+ wide bandgap semiconductors substrate 4 and N- wide bandgap semiconductor extensions
Layer 3；
Step 2：By trench etch process, the groove positioned at 3 both sides of N- wide bandgap semiconductors epitaxial layer is formed；
Step 3：By deposit and etching technics, either ion implantation technology deposits in channel bottom or in beneath trenches
Implanting p-type semiconductor material with wide forbidden band forms P+ wide bandgap semiconductors area 2；
Step 4：By deposit and etching technics or epitaxy technique, p-type is formed in 2 upper surface of P+ wide bandgap semiconductors area
The areas wide bandgap semiconductor Well 10；
Step 5：By dry-oxygen oxidation or depositing technics, in the areas p-type wide bandgap semiconductor Well 10 and the broad stopbands N- half
3 upper surface dielectric layer deposited material of conductor epitaxial layer, and the etched extra dielectric layer material of removal, it is wide to form covering part p-type
The dielectric layer 8 of the areas bandgap semiconductor Well 10 and part N- wide bandgap semiconductors epitaxial layer 3；
Step 6：It is narrow in dielectric layer 8 and the deposit of 3 upper surface of N- wide bandgap semiconductors epitaxial layer by deposit and etching technics
Bandgap semiconductor material, and the etched extra low-gap semiconductor material of removal, form and are partly led positioned at dielectric layer 8 and the broad stopbands N-
Low-gap semiconductor area 7 on body epitaxial layer 3；
Step 7：By deposit, photoetching and etching technics, partly led in low-gap semiconductor 7, dielectric layer 8 and p-type broad stopband
The upper surface in the areas body Well 10 forms metal anode 1, and overturning device overleaf forms metallic cathode 5, so far completes the system of device
Make.
Further, further include following steps before the step 5：By photoetching, ion implantation technology, in the wide taboo of p-type
10 top layer of the areas band semiconductor Well forms N+ wide bandgap semiconductors source region 9, is made respectively in 9 upper surface of N+ wide bandgap semiconductors source region
Make metal anode 1 and dielectric layer 8.
Further, when formation N+ wide bandgap semiconductors between the areas p-type wide bandgap semiconductor Well 10 and metal anode 1
Source region 9, P+ wide bandgap semiconductors area 2 can be both grounded the present invention in step 7, can also floating setting.
Further, further include following steps before the step 5：By photoetching, ion implantation technology, in the broad stopbands P+
2 upper surface of semiconductor region is formed and P+ silicon carbide contacts area 6 arranged side by side of the areas 10 p-type wide bandgap semiconductor Well, in p-type broad stopband
The areas semiconductor Well 10 form the N+ wide bandgap semiconductors source region 9 being in contact with P+ silicon carbide contacts area 6, are partly led in the broad stopbands P+
Body contact zone 6 and 9 upper surface of part N+ wide bandgap semiconductors source region make metal anode 1, part N+ wide bandgap semiconductors source region 9
Upper surface makes dielectric layer 8.
Further, formation P+ wide bandgap semiconductors area 2, P+ silicon carbide contacts area 6, the broad stopbands N+ are partly led in the present invention
Body source region 9 and the areas p-type wide bandgap semiconductor Well 10 can not also pass through etching groove, directly be injected using multiple energetic ion
Mode formed.
Further, the present invention can form the P+ that transverse width is more than groove width by thermal diffusion process in step 3
Wide bandgap semiconductor area 2.
Further, formed in the step 2 and 3 groove and P+ wide bandgap semiconductors area 2 operation can be replaced it is as follows
Operation：Deepen the depth of etching groove by multiple extension, thermal diffusion and etching so that P+ wide bandgap semiconductors area 2 and N-
Wide bandgap semiconductor epitaxial layer 3 distributes alternately, and by controlling P+ wide bandgap semiconductors area 2 and N- wide bandgap semiconductor epitaxial layers
3 width and doping concentration forms super-junction structure.
Further, when forming above-mentioned super-junction structure, the step 2 further includes passing through ion after trench formation
Injection technology forms heavy doping N- wide bandgap semiconductor epitaxial layers 3b at the top of N- wide bandgap semiconductors epitaxial layer 3.
Further, it when forming above-mentioned super-junction structure, is formed after P+ wide bandgap semiconductors area 2 in the step 3
Further include that P++ wide bandgap semiconductors area 2b is formed at the top in P+ wide bandgap semiconductors area 2 by ion implantation technology.
According to embodiments of the present invention, the material of the wide bandgap semiconductor is silicon carbide, the material of the low-gap semiconductor
Material is silicon materials, other to be made of semiconductor material with wide forbidden band and low-gap semiconductor material according to general knowledge known in this field
Combination is equally applicable for device architecture provided by the invention, and the present invention is without limitation.
Further, can may be list for polysilicon when the low-gap semiconductor that the step 6 is deposited is silicon
Crystal silicon, the polysilicon can be that p-type polysilicon may be N-type polycrystalline silicon, and the monocrystalline silicon can be that p type single crystal silicon also may be used
Think n type single crystal silicon.
The present invention makes low-gap semiconductor, dielectric layer, the areas Well and epitaxial layer be formed super by rational modification device architecture
Barrier structure, and low-gap semiconductor forms hetero-junctions with epitaxial layer in contact interface in super barrier structure.Pass through above-mentioned work(
Can area it is integrated, the present invention is addressed that the conduction loss present in now current PIN diode device is larger, reverse recovery characteristic
The problems such as poor.It should be strongly noted that device architecture proposed by the present invention is applicable not only to N-channel device, it is equally applicable to P
Channel device.
Silicon carbide, low-gap semiconductor is used to be formed by diode using polysilicon selection wide bandgap semiconductor below
As an example to elaborate the principle of the invention, those skilled in the art can be readily available device according to following disclosure
Remaining wide, low-gap semiconductor combination of materials forms the principle of device.
Multi-crystal silicon area, dielectric layer and the areas Well constitute metal (M)-insulator in diode component provided by the invention
(I)-semiconductor (S) structure (hereinafter referred to as MIS structure), doping concentration, the medium of polysilicon are adjusted by technology controlling and process
The parameters such as the thickness and charge number of floor and the doping concentration in the areas p-type silicon carbide Well so that the threshold voltage of MIS structure is less than
0.1V.When the voltage that metal anode applies is close to 0.1V, due to the presence of MIS structure subthreshold region electric current so that have one small
Part electronic current flows through N- wide bandgap semiconductors epitaxial layer, the p-type areas wide bandgap semiconductor Well and N+ wide bandgap semiconductors
Source region.The electronic current causes the pressure drop in the areas p-type wide bandgap semiconductor Well.And in the other end of dielectric layer, due to Si/
SiC hetero-junctions is more than the positive cut-in voltage of 0.1V, therefore is believed that multi-crystal silicon area no current flows through, i.e., multi-crystal silicon area potential is everywhere
It is identical.And the potential of dielectric layer both sides gradually increases from top to bottom along device vertical direction, this difference makes on metal anode
Voltage without adding to 0.1V (i.e. the grid voltage of super barrier structure), which just has apparent electric current and passes through, i.e., device has been
Conducting.For conventional power devices, normal work usually requires on high voltage, and device proposed by the present invention
Structure has the cut-in voltage less than 0.1V, may be considered that the cut-in voltage close to 0V, therefore device proposed by the present invention
Structure has absolute predominance in low pressure applications.Meanwhile device of the present invention is by the improvement in structure, in the case where working normally bias,
Have the characteristics that current density is big.
P+ wide bandgap semiconductors area forms bipolar access with N- wide bandgap semiconductor epitaxial layers.The bipolar access is larger
Conductivity modulation effect occurs under bias.For silicon carbide PIN diode, need sufficiently high conductance modulation horizontal, with drop
The larger resistance of low epitaxial layer.Due to the presence of super barrier diode structure and the more electron currents of Si/SiC hetero-junctions, the present invention
Structure is horizontal without excessively high conductance modulation, you can to obtain on-state voltage drop identical with Conventional silicon carbide PIN diode.Change and
Yan Zhi, under forward conduction mode, the storage charge of silicon carbide PIN diode structure proposed by the invention is carbonized far below tradition
Storage charge in silicon PIN diode, i.e., device architecture of the present invention optimize device reverse recovery characteristic, reduce device shutdown
Loss, to obtain a good compromise characteristic between forward conduction voltage drop VF and turn-off power loss Eoff.
The PN junction that P+ wide bandgap semiconductors area is constituted with N- wide bandgap semiconductor epitaxial layers in the bar state can be pressure-resistant,
Its voltage blocking capability and Conventional silicon carbide PIN diode are essentially identical.And due to the extremely low electric leakage of super barrier structure, it is proposed
Structure have reverse leakage more lower than Conventional silicon carbide PIN diode.
Further, P+ wide bandgap semiconductors area forms super-junction structure with N- wide bandgap semiconductor epitaxial layers, can show in this way
The voltage blocking capability for promoting device is write, to obtain the compromise characteristic of better forward voltage drop and breakdown voltage；And surpass
Diode under junction structure, since the low-doped areas i are not present in it, therefore it can be handled with stronger Antisurge current ability
The di/dt operating modes of bigger.
In order to reach better reverse recovery characteristic, the present invention also provides devices more than two kinds as shown in Figure 3 and Figure 4.
Fig. 3 show the structure cell of the first how sub- device, and the structure in the areas p-type wide bandgap semiconductor Well by forming N+ wide
Bandgap semiconductor source region so that N+ wide bandgap semiconductor source regions cover the original in the p-type areas wide bandgap semiconductor Well and metal anode
The part of this contact, with season P+ wide bandgap semiconductors area ground connection or floating, to cut off hole current access.Forward direction work
Under pattern, which has the knee voltage close to 0V, while having high few electron current level of density；In turn off process,
Since there is no charge storage, therefore it is with extraordinary reverse recovery characteristic；Under blocking state, due to P+ wide bandgap semiconductors
The effect in area, the device also have and voltage blocking capability similar in Conventional silicon carbide PIN devices.Fig. 4 is shown more than second
The structure cell of sub- device, the structure p-type areas wide bandgap semiconductor Well form Schottky contacts with metal anode, do not have P+ carbon
SiClx contact zone and N+ wide bandgap semiconductor source regions, when diode metal anode applies positive bias, the Schottky contacts
In reverse-biased, when the voltage of metal anode is higher than 0.1V, the p-type areas wide bandgap semiconductor Well surface transoid forms electricity
Sub-channel, it is reverse-biased through N- wide bandgap semiconductors epitaxial layer and surface inversion channel arrival Schottky from N+ wide bandgap semiconductors substrate
The electronics of junction interface is taken away rapidly by anode and forms electric current, and the electric current is for diode component, and as forward conduction is electric
Stream.The same with the first how sub- device, sub- device more than second also has good reverse recovery characteristic.
The beneficial effects of the invention are as follows：
One, diode component proposed by the present invention has the positive cut-in voltage close to 0V, to be obviously improved two
The rectification efficiency of pole pipe reduces device on-state loss, has saved energy resources.
Two, diode component proposed by the present invention is in identical forward conduction voltage drop VFUnder, there is lower conductance modulation
Level reduces reverse recovery time, optimizes device to reduce storage electric charge number, shorten reverse recovery time
Reverse recovery characteristic.Diode component i.e. proposed by the present invention is in forward conduction voltage drop VFIt is obtained between reverse recovery charge Qrr
Obtained a good compromise characteristic.
Three, diode component proposed by the present invention has lower electric leakage under the premise of not influencing pressure resistance, to have
Higher reliability, the safety operation area of bigger.
Four, diode component proposed by the present invention uses super-junction structure, considerably enhances device voltage blocking ability, together
When, since the low-doped areas i are not present in it, therefore it can handle the di/dt operating modes of bigger, have stronger Antisurge current energy
Power.
Five, diode component proposed by the present invention it is convenient, fast in practical applications, using flexible, can be according to specifically answering
With the function module of situation selection application, you can selection monopolar operation pattern or bipolar operation pattern, to adapt to different answer
Use occasion.
Six, diode component proposed by the present invention can be fully operational in how sub- device model by structure improvement, to
Device reverse recovery characteristic is further increased, makes it that there is larger advantage in application scenarios such as high-speed rectifier, fast recoveries.
Description of the drawings
Fig. 1 is the structure cell schematic diagram of Conventional silicon carbide PIN diode device；
Fig. 2 is the structure cell schematic diagram for the diode component that the embodiment of the present invention 1 provides；
Fig. 3 is the structure cell schematic diagram for the diode component that the embodiment of the present invention 2 provides；
Fig. 4 is the structure cell schematic diagram for the diode component that the embodiment of the present invention 3 provides；
Fig. 5 is the structure cell schematic diagram for the diode component that the embodiment of the present invention 4 provides；
Fig. 6 be in the embodiment of the present invention 5 metal anode area in the setting schematic diagram of three dimensions；
Fig. 7 is the diode component structure cell schematic diagram that the embodiment of the present invention 6 provides；
Fig. 8 is the function zoning schematic diagram for the diode component that the embodiment of the present invention 1 provides；
Fig. 9 is the schematic diagram that the diode component that the embodiment of the present invention 1 provides is labeled with a1, a2, b1 and b2；
Figure 10 is the Potential Distributing schematic diagram for the diode component dielectric layer both sides that the embodiment of the present invention 1 provides；
Figure 11 is each functional areas I-V characteristic curve in the diode component that the embodiment of the present invention 1 provides；
Figure 12 is the I-V characteristic curve for the diode component that the embodiment of the present invention 1 provides；
Figure 13 is the substrate and epitaxial layer schematic diagram for the diode component that the embodiment of the present invention 1 provides；
Figure 14 is the schematic diagram that the diode component that the embodiment of the present invention 1 provides forms groove；
Figure 15 is the schematic diagram that the diode component that the embodiment of the present invention 1 provides forms P+ wide bandgap semiconductors area；
Figure 16 is the schematic diagram that the diode component that the embodiment of the present invention 1 provides forms the areas p-type wide bandgap semiconductor Well；
Figure 17 is the schematic diagram that the diode component that the embodiment of the present invention 1 provides forms P+ wide bandgap semiconductors contact zone；
Figure 18 is the schematic diagram that the diode component that the embodiment of the present invention 1 provides forms P+ wide bandgap semiconductor source regions；
Figure 19 is the schematic diagram that the diode component that the embodiment of the present invention 1 provides forms dielectric layer；
Figure 20 is the schematic diagram that the diode component that the embodiment of the present invention 1 provides forms low-gap semiconductor area；
Figure 21 is the schematic diagram that the diode component that the embodiment of the present invention 1 provides forms metal anode and metallic cathode.
Serial number meaning is described as follows in figure：
1 is metal anode, and 2 be the silicon carbide regions P+, and 2a is that the silicon carbide regions P+ are lightly doped, and 2b is the silicon carbide regions P++, and 3 be N-
Silicon carbide epitaxial layers, 3a are that N- silicon carbide epitaxial layers are lightly doped, and 3b is heavy doping N- silicon carbide epitaxial layers, and 4 serve as a contrast for N+ silicon carbide
Bottom, 5 be metallic cathode, and 6 be P+ silicon carbide contacts area, and 7 be multi-crystal silicon area, and 8 be dielectric layer, and 9 be N+ silicon carbide source regions, and 10 be P
The areas type silicon carbide Well.
Specific implementation mode
With reference to the accompanying drawings of the specification, the structure of device and production method are described in detail so that art technology
Personnel understand technical scheme of the present invention and principle.Specific embodiment is only used for explaining the present invention, is not intended to limit the present invention
Range.
Although there are simple for process, blocking voltage ability be strong and good antisurge electricity for Conventional silicon carbide PIN diode
The advantages such as stream ability, but because there is positive cut-in voltage big (about 3.1V), Reverse recovery ability in Conventional silicon carbide PIN diode
The problems such as poor so that its application in the market is limited by very large.The present invention is carried by the improvement in structure
Gone out it is a kind of can optimize the above-mentioned insufficient structure of silicon carbide PIN diode, as shown in figures 2-6.
Embodiment 1：
A kind of diode component, structure cell is as shown in Fig. 2, include the metallic cathode being cascading from bottom to top
5, N+ silicon carbide substrates 4, N- silicon carbide epitaxial layers 3 and metal anode 1；The top layer both sides of N- silicon carbide epitaxial layers 3 have groove
Structure, the groove structure include the silicon carbide regions P+ 2, P+ silicon carbide contacts area 6, N+ silicon carbide source region 9 and p-type silicon carbide Well
Area 10, the silicon carbide regions P+ 2 are located at channel bottom, and P+ silicon carbide contacts area 6 and the areas p-type silicon carbide Well 10 are located at P+ and are carbonized side by side
2 upper surface of silicon area, N+ silicon carbide source region 9 are located at 10 top layer of the areas p-type silicon carbide Well and are in contact with P+ silicon carbide contacts area 6；P
+ silicon carbide contact area 6 and 9 upper surface of part N+ silicon carbide source region are in contact with metal anode 1, part N+ silicon carbide source region 9, P
The areas type silicon carbide Well 10 and the upper surface of part N- silicon carbide epitaxial layers 3 are in contact with dielectric layer 8, and dielectric layer 8 and N- is carbonized
3 upper surface of silicon epitaxy layer is in contact with multi-crystal silicon area 7, the multi-crystal silicon area 7, dielectric layer 8, N+ silicon carbide source region 9, p-type carbonization
The areas silicon Well 10 and N- silicon carbide epitaxial layers 3 form super barrier structure, the multi-crystal silicon area 7 and 3 shape of N- silicon carbide epitaxial layers
At hetero-junctions, the silicon carbide regions P+ 2 form PN junction with N- silicon carbide epitaxial layers 3.
Wide bandgap semiconductor selects silicon carbide in the present embodiment, and low-gap semiconductor selects polysilicon, below with 1200VN
The parameter of each structure is provided for channeling diode device：Metal anode 1, metallic cathode 5 thickness be 0.4 μm~2 μm, width
It is 2~5 μm；The doping concentration of N+ silicon carbide substrates 4 is 3e18~8e18/cm3, thickness is 0.5 μm to 2.5 μm, width 2.0
μm~5.0 μm；The doping concentration of N- silicon carbide epitaxial layers 3 is 1e14~8e15/cm3, thickness is 5 μm~8 μm, and width is 2.0 μ
M~5.0 μm；The thickness of the silicon carbide regions P+ 2 is about 0.5~1.6 μm, and doping concentration is about 5e18~6e19/cm3, width is about
0.5 μm~0.7 μm；The width of multi-crystal silicon area 7 is about 2.0 μm~4.0 μm, and thickness is about 0.8 μm~1.6 μm；The thickness of dielectric layer 8
Degree is about 10nm~60nm, and width is about 0.4 μm~0.6 μm；The thickness in the areas p-type silicon carbide Well 10 is about 0.3 μm~0.5 μ
M, width are about 0.2 μm~0.4 μm, and doping concentration is about 1e15~1e17/cm3；The thickness of N+ silicon carbide source region 9 is about 0.1 μ
M~0.3 μm, width are about 0.2 μm~0.3 μm, and doping concentration is about 1e18~7e18/cm3；The thickness in P+ silicon carbide contacts area 6
About 0.3 μm~0.5 μm of degree, width is about 0.2 μm~0.3 μm, and doping concentration is about 1e18~8e18/cm3。
The present invention forms super barrier structure (functional areas A), hetero-junctions (B as shown in Figure 8 by rational modification device architecture
Functional areas) and PN junction (functional areas C) these three functional areas, so that the comprehensive performance of device is significantly better than traditional PIN diode
Performance.
The inventive principle and characteristic of the present invention are described in detail with reference to specific embodiment：
Using silicon carbide as semiconductor material with wide forbidden band, polysilicon is formed the present embodiment as low-gap semiconductor material
N-channel diode component for, the principle of the invention and characteristic are described in detail, those skilled in the art are according to following public affairs
Open that content can release the principle of P-channel diode component and remaining wide, low-gap semiconductor combination of materials forms diode device
The principle of part：
The present invention be directed to positive cut-in voltage big (silicon carbide PIN diode about 3.1V) present in traditional PIN diode,
The problems such as Reverse recovery energy force difference, rational modification device architecture is to optimize above-mentioned performance.
Multi-crystal silicon area 7, dielectric layer 8 and the areas p-type silicon carbide Well 10 constitute in diode component provided by the invention
Metal (M)-insulator (I)-semiconductor (S) structure (hereinafter referred to as MIS structure), multi-crystal silicon area is adjusted by technology controlling and process
The parameters such as 7 doping concentration, the thickness of dielectric layer 8 and charge number and the doping concentration in the areas p-type silicon carbide Well 10 so that
The threshold voltage of MIS structure is less than 0.1V.When the voltage that metal anode 1 applies is close to 0.1V, due to MIS structure subthreshold region
The presence of electric current so that there is sub-fraction electronic current to flow through N- silicon carbide epitaxial layers 3, the areas p-type silicon carbide Well 10 and N+
Silicon carbide source region 9.The electronic current causes the pressure drop in the areas p-type silicon carbide Well 10.And in the other end of dielectric layer 8, by
It is more than the positive cut-in voltage of 0.1V in Si/SiC hetero-junctions, therefore is believed that multi-crystal silicon area no current flows through, is i.e. multi-crystal silicon area 7
Potential is identical everywhere.To the potential profile that Figure 10 is 8 both sides of dielectric layer, a1, a2, b1 and b2 are marked in fig.9, from
A1 and 2 points of a2 be can be seen that in figure almost without potential difference, and from point a to point b, potential difference gradually increases from top to bottom in vertical direction
Greatly.This difference makes the voltage on metal anode without adding to 0.1V (i.e. the grid voltage of super barrier structure), which just has
Apparent electric current passes through, i.e., device has been turned on.For conventional power devices, normal work is usually required in higher electricity
On pressure, and device architecture proposed by the present invention has the cut-in voltage less than 0.1V, may be considered that the unlatching close to 0V
Voltage, therefore device architecture proposed by the present invention has absolute predominance in low pressure applications.Meanwhile device of the present invention passes through in structure
Improvement have the characteristics that current density is big in the case where working normally bias.
In the case of negligible resistance, the I-V characteristic curve in individual feature area is as shown in figure 11, wherein tri- work(of A, B, C
As shown in figure 8, wherein A is super barrier structure, B is Si/SiC hetero-junctions in energy area, and C is SiC PN junctions.It is more with p-type in the present embodiment
It is described in detail for crystal silicon, those skilled in the art can obtain the principle of N-type polycrystalline silicon on this basis.A, B, C tri-
Functional areas, i.e. super barrier structure, Si/SiC hetero-junctions and silicon carbide PN junction it is positive open pressure drop respectively about 0V, 1.1V and
3.1V.With applying alive increase, the pressure drop at Si/SiC hetero-junctions and silicon carbide PIN diode both ends on metal anode 1
Increase therewith, when the voltage of Si/SiC hetero-junctions and silicon carbide PIN diode both ends respectively reaches 1.1V and 3.1V, Si/SiC
Hetero-junctions and silicon carbide PIN diode are respectively turned on.For the ease of being explained from principle, it is assumed that Si/SiC hetero-junctions is prior to carbonization
Silicon PIN diode is connected, then the I-V characteristic curve of diode component is as shown in figure 12.Curve A indicates only have superpotential in Figure 12
The case where building structure conducting；Curve A+B indicates the case where super barrier structure and Si/SiC hetero-junctions are connected；And curve A+B+C tables
Show super barrier structure, the case where Si/SiC hetero-junctions and silicon carbide PN junction are both turned on.Although diode component proposed by the present invention
Bipolar device is still fallen in the case where super barrier structure hetero-junctions and PN junction are both turned on, that is to say, that in injection situation greatly
Under conductivity modulation effect can occur, but under identical pressure drop, diode component proposed by the invention has lower electricity
Lead modulation level.According to preceding described, the silicon carbide regions P+ 2 form bipolar access with N- silicon carbide epitaxial layers 3.The bipolar access compared with
Conductivity modulation effect occurs under big bias.For silicon carbide PIN diode, need sufficiently high conductance modulation horizontal, with
Reduce the larger resistance of epitaxial layer.Due to the presence of super barrier diode structure and the more electron currents of Si/SiC hetero-junctions, this hair
Bright structure is horizontal without excessively high conductance modulation, you can to obtain on-state voltage drop identical with Conventional silicon carbide PIN diode.It changes
For it, under forward conduction mode, the storage charge of silicon carbide PIN diode structure proposed by the invention is far below conventional carbon
Storage charge in SiClx PIN diode, i.e., device architecture of the present invention optimize device reverse recovery characteristic, reduce device pass
Breakdown consumes, to obtain a good compromise characteristic between forward conduction voltage drop VF and reverse recovery charge Qrr.
The PN junction that the silicon carbide regions P+ are constituted with N- silicon carbide epitaxial layers in the bar state can be pressure-resistant, voltage block energy
Power and Conventional silicon carbide PIN diode are essentially identical.And due to the extremely low electric leakage of super barrier structure, the structure that is proposed have than
The lower reverse leakage of Conventional silicon carbide PIN diode.
Embodiment 2：
A kind of diode component, structure cell as shown in figure 3, include that the metal that is cascading is cloudy from bottom to top
Pole 5, N+ silicon carbide substrates 4, N- silicon carbide epitaxial layers 3 and metal anode 1；The top layer both sides of N- silicon carbide epitaxial layers 3 have ditch
Slot structure, the groove structure include the silicon carbide regions P+ 2, N+ silicon carbide source region 9 and the areas p-type silicon carbide Well 10, P+ silicon carbide
Area 2 is located at channel bottom, and the areas p-type silicon carbide Well 10 are located at 2 upper surface of the silicon carbide regions P+, and N+ silicon carbide source region 9 is located at p-type carbon
10 top layer of the areas SiClx Well；N+ silicon carbide source region 9 upper surface in part is in contact with metal anode 1, part N+ silicon carbide source region 9, P
The areas type silicon carbide Well 10 and the upper surface of part N- silicon carbide epitaxial layers 3 are in contact with dielectric layer 8, and dielectric layer 8 and N- is carbonized
3 upper surface of silicon epitaxy layer is in contact with multi-crystal silicon area 7, the multi-crystal silicon area 7, dielectric layer 8, N+ silicon carbide source region 9, p-type carbonization
The areas silicon Well 10 and N- silicon carbide epitaxial layers 3 form super barrier structure, the multi-crystal silicon area 7 and 3 shape of N- silicon carbide epitaxial layers
At hetero-junctions, the silicon carbide regions P+ 2 form PN junction with N- silicon carbide epitaxial layers 3.
Compared to embodiment 1, P+ silicon carbide contacts area 6 is not arranged for the present embodiment, and N+ silicon carbide source region 9 is made to cover gold
Belong to anode 1 and 10 contact portion of the areas p-type silicon carbide Well, formation width is 0.4 μm~0.6 μm, is doped to 1e17~1e18/
The N+ silicon carbide source region 9 that cm3 thickness is 0.1 μm~0.3 μm.Meanwhile the silicon carbide regions P+ 2 are by the way of floating or ground connection.
Such setting can block hole current access, make invention device be operated in monopolar mode.The improvement of the present embodiment is for device
Part has actively impact in high speed, the fast extensive use for restoring occasion.
Embodiment 3：
A kind of diode component, structure cell is as shown in figure 4, include the metallic cathode being cascading from bottom to top
5, N+ silicon carbide substrates 4, N- silicon carbide epitaxial layers 3 and metal anode 1；The top layer both sides of N- silicon carbide epitaxial layers 3 have groove
Structure, the groove structure include the silicon carbide regions P+ 2 and the areas p-type silicon carbide Well 10, and the silicon carbide regions P+ 2 are located at channel bottom, P
The areas type silicon carbide Well 10 are located at 2 upper surface of the silicon carbide regions P+；The upper surface in the part areas p-type silicon carbide Well 10 and metal anode
1 is in contact, and the upper surface of the part areas p-type silicon carbide Well 10 and part N- silicon carbide epitaxial layers 3 has the medium contacted
Layer 8；Dielectric layer 8 has the multi-crystal silicon area 7 contacted with 3 upper surface of part N- silicon carbide epitaxial layers；The multi-crystal silicon area 7,
Dielectric layer 8, the areas p-type silicon carbide Well 10 and N- silicon carbide epitaxial layers 3 form super barrier structure, the multi-crystal silicon area 7 and N-
Silicon carbide epitaxial layers 3 form hetero-junctions, and the silicon carbide regions P+ 2 form PN junction with N- silicon carbide epitaxial layers 3.
The areas p-type silicon carbide Well 10 are in direct contact to form Schottky contacts with metal anode 1 in the present embodiment.Work as diode
When anode adds positive bias, Schottky contacts are in reverse-biased.Once there is superfluous few son in the areas p-type silicon carbide Well 10, it should
Few son will be swept to metal anode 1.It, will in the areas p-type silicon carbide Well 10 when the voltage for being applied to metal anode 1 is higher than 0.1V
There is superfluous few son, the few son of the surplus is taken away rapidly by metal anode 1 and forms electric current.The electric current for diode component and
Speech, as forward conduction electric current.Electric current under this operating mode is monopolar current so that institute's invention device works in monopole mould
Formula.With embodiment 2, the present embodiment improvement is also conducive to popularization of the device in high-speed applications.
Embodiment 4：
Diode component structure cell schematic diagram provided in this embodiment is as shown in figure 5, compare the difference of embodiment 1
It is：The bigger that the transverse width of the silicon carbide regions P+ 2 is done.For comparing embodiment 2, the transverse width of the silicon carbide regions P+ 2 is made
It is bigger, it is also stronger to the electric field shielding effect of 2 area above of the silicon carbide regions P+ when device is in blocking state, both protected
The structures such as hetero-junctions, super barrier structure have been protected, while also having improved the pressure-resistant performance of device.It should be noted that P+ silicon carbide
The width in area 2 is wider, and conducting resistance when device forward direction works is bigger.Therefore the width of the silicon carbide regions P+ 2 need it is positive with
Weighed between reverse operation.
Embodiment 5：
Diode component structure cell provided in this embodiment compare embodiment 1 the difference is that：The silicon carbide regions P+ 2
Super-junction structure is formed with N- silicon carbide epitaxial layers 3.Pass through control and adjusting process parameter so that N columns, that is, N- silicon carbide epitaxial layers 3
Meet Qn=Qp with P columns, that is, silicon carbide regions P+ 2.
The super-junction structure introduced in the present embodiment can promote the electricity of device by optimizing the field distribution under blocking mode
Pressure drag cutting capacity, to obtain the compromise characteristic of better forward voltage drop and breakdown voltage；Simultaneously as super-junction structure can
Promote extension concentration so that device can be subjected to the di/dt impacts of bigger, therefore device is enable to have higher Antisurge current
Power.
Embodiment 6：
Diode component structure cell schematic diagram provided in this embodiment is as shown in fig. 6, compare the difference of embodiment 5
It is：Heavy doping N- silicon carbide epitaxial layers 3b are formed on the top of N- silicon carbide epitaxial layers 3, is formed under top and N- carbon is lightly doped
SiClx epitaxial layer 3a.
Embodiment 7：
Diode component structure cell schematic diagram provided in this embodiment is as shown in fig. 7, compare the difference of embodiment 6
It is：P++ silicon carbide region 2b are formed on the top of the silicon carbide regions P+ 2, is formed under top and the silicon carbide regions P+ 2a is lightly doped.
The present embodiment compares embodiment 6, N columns (i.e. N- silicon carbide epitaxial layers 3) and P columns (i.e. the silicon carbide regions P+ 2) fully- depleted
In the case of, better protective effect can be played to its top super barrier structure, Si/SiC heterojunction structures etc., to improve
Device reliability extends safety operation area.
Embodiment 8：
A kind of production method of diode component, which is characterized in that include the following steps：
Step 1：As shown in figure 13, the silicon carbide plate of suitable resistivity and thickness is chosen as N+ silicon carbide substrates 4 and N-
Silicon carbide epitaxial layers 3, wherein the doping concentration of N+ silicon carbide substrates 4 is 3e18~8e18/cm3, thickness is 0.5 μm~2.5 μ
M, width are 2.0 μm~5.0 μm；The doping concentration of N- silicon carbide epitaxial layers 3 is 1e14~8e15/cm3, thickness is 5 μm~8 μ
m；
Step 2：By trench etch process, width is etched in 3 both sides of N- silicon carbide epitaxial layers using Trench mask plates
About 0.3 μm~0.5 μm of degree, the groove that depth is about 1.1 μm~1.8 μm, width is about 0.5 μm~0.7, as shown in figure 14；
Step 3：By deposit and etching technics, p-type carbofrax material is deposited in channel bottom, is not required to by etching removal
The p-type carbofrax material wanted, it is about 0.5 μm~1.6 μm to form thickness, the P+ carbonizations that doping concentration is about 5e18~6e19/cm3
Silicon area 2, as shown in figure 15；
Step 4：By deposit and etching technics, p-type carbofrax material is deposited on the silicon carbide regions P+ 2, is gone by etching
Except unwanted p-type carbofrax material, it is about 0.3 μm~0.5 μm to form thickness, and width is 0.2 μm~0.4 μm, doping concentration
The areas p-type silicon carbide Well 10 of about 1e15~1e17/cm3, as shown in figure 16；
Step 5：By processes such as photoetching, ion implantings, using PSD mask plates, at a temperature of 450 DEG C~550 DEG C into
Row Al ion implantation, Implantation Energy are about 1400~1700keV, and it is about 0.3 μm~0.5 μm to form thickness, and width is about 0.2 μm
~0.3 μm, doping is about the P+ silicon carbide contacts area 6 of 1e18~8e18/cm3, as shown in figure 17；
Step 6：By processes such as photoetching, ion implantings, using PSD mask plates, at a temperature of 450 DEG C~550 DEG C into
Row phosphonium ion injects, and Implantation Energy is about 1300~1700keV, and it is about 0.1 μm~0.3 μm to form thickness, and width is about 0.2 μm
~0.3 μm, doping is about the N+ silicon carbide source region 9 of 1e18~7e18/cm3, as shown in figure 18；
Step 7：By dry-oxygen oxidation or depositing technics, in the areas p-type silicon carbide Well 10 and N- silicon carbide epitaxial layers 3
Surface deposition dielectric layer material, and the extra dielectric layer material of etched removal, formed the areas covering part p-type silicon carbide Well 10 and
The dielectric layer 8 of part N- silicon carbide epitaxial layers 3, as shown in figure 19；
Step 8：By deposit and etching technics, in 3 upper surface depositing polysilicon of dielectric layer 8 and N- silicon carbide epitaxial layers,
And etched removal excess polysilicon material, it is about 2.0 μm to form the width on dielectric layer 8 and N- silicon carbide epitaxial layers 3
~4.0 μm, thickness is about 0.8 μm~1.6 μm of multi-crystal silicon area 7, as shown in figure 20；
Step 9：By deposit, photoetching and etching technics, in multi-crystal silicon area 7, dielectric layer 8 and the areas p-type silicon carbide Well 10
Upper surface formed metal anode 1, overturning device overleaf form metallic cathode 5, as shown in figure 21, so far complete device system
Make.
Further, the present embodiment step 2~6 form the silicon carbide regions P+ by techniques such as etching groove, deposit, photoetching
2, the process in P+ silicon carbide contacts area 6, N+ silicon carbide source region 9 and the areas p-type silicon carbide Well 10 can not also pass through groove and carve
Erosion, and formed by the way of the injection of multiple energetic ion.
Further, when etching to form groove using Trench mask plates in the present embodiment step 2,5.0 μ can also be etched
The depth of m~8.0 μm, the silicon carbide regions the P+ 2P columns and N- silicon carbide epitaxies formed by multiple extension, thermal diffusion and etching
Layer 3N columns formation distributes alternately, and width and doping concentration by controlling the silicon carbide regions P+ 2 and N- silicon carbide epitaxial layers 3 are formed
Super-junction structure.
Further, further include by ion implantation technology in N- silicon carbide epitaxies when forming above-mentioned super-junction structure
Heavy doping N- silicon carbide epitaxial layers 3a is formed on the top of layer 3, you can obtains device architecture as shown in Figure 6.
Further, when forming above-mentioned super-junction structure by ion implantation technology on the top of N- silicon carbide epitaxial layers 3
Portion is formed on the basis of heavy doping N- silicon carbide epitaxial layers 3a, and in the silicon carbide regions P+, 2 apex zone tries again ion implanting, shape
At the silicon carbide regions the P++ 2b that doping concentration is 8e18~7e19/cm3, you can obtain device architecture as shown in Figure 7.
Further, it can do a thermal diffusion after extension or deposit P+ silicon carbide in the present embodiment step 3, be formed laterally
The silicon carbide regions P+ 2 that width is 0.5 μm~0.9 μm.
Further, further include following steps before the step 5：By photoetching, ion implantation technology, it is carbonized in p-type
10 top layer of the areas silicon Well forms N+ silicon carbide source region 9.
Further, the present embodiment step 5 can be omitted, that is, formed P+ silicon carbide contacts area 6 operation omit, and directly into
Enter step 6, and so that the N+ silicon carbide source region 9 is covered metal anode 1 by adjusting the size of NSD mask plates in step 6
With 10 contact portion of the areas p-type silicon carbide Well, formation width, which is 0.4 μm~0.6 μm, is doped to 1e17~1e18/cm3 thickness is
0.1 μm~0.3 μm of N+ silicon carbide source region 9, you can obtain device architecture as shown in Figure 3.
Further, when N+ silicon carbide source region 9 covers metal anode 1 and 10 contact portion shape of the areas p-type silicon carbide Well
At the N+ silicon carbide source region 9 between the areas p-type silicon carbide Well 10 and metal anode 1, present invention P+ silicon carbide in step 7
Area 2 can be both grounded, can also floating setting.
Further, the present embodiment step 5 and 6 can be omitted, and the areas p-type silicon carbide Well 10 directly connect with metal anode 1
It touches and forms Schottky contacts, you can obtain device architecture as shown in Figure 4.
Further, further include following steps before the step 5：By photoetching, ion implantation technology, in P+ silicon carbide
2 upper surface of area is formed and P+ silicon carbide contacts area 6 arranged side by side of the areas 10 p-type silicon carbide Well, is formed in the areas p-type silicon carbide Well 10
The N+ silicon carbide source region 9 being in contact with P+ silicon carbide contacts area 6.
Further, the low-gap semiconductor that the step 6 is deposited is not limited to polysilicon, or monocrystalline silicon,
The polysilicon can be that p-type polysilicon may be N-type polycrystalline silicon, and the monocrystalline silicon can be that p type single crystal silicon may be N
Type monocrystalline silicon.
While need to declare is：Those skilled in the art are according to this field basic knowledge it is found that disclosed by the invention one
Kind diode device structure and production method, wide bandgap semiconductor and low-gap semiconductor material used are not limited to the present embodiment
Disclosed silicon carbide and silicon materials, other combinations being made of semiconductor material with wide forbidden band and low-gap semiconductor material are equally suitable
In device architecture provided by the invention, the present invention is without limitation；The material of dielectric layer is formed in addition to titanium dioxide may be used
Silicon (SiO2) can also use silicon nitride (Si3N4), hafnium oxide (HfO2), alundum (Al2O3) (Al2O3) etc. any suitable
High K dielectric material is realized；Meanwhile the specific implementation mode of manufacturing process can also be adjusted according to actual needs.
Claims (10)
1. a kind of diode component, structure cell includes the metallic cathode (5) being cascading, the broad stopbands N+ from bottom to top
Semiconductor substrate (4), N- wide bandgap semiconductors epitaxial layer (3) and metal anode (1)；N- wide bandgap semiconductors epitaxial layer (3)
Top layer both sides have groove structure, and the groove structure includes P+ wide bandgap semiconductors area (2) and p-type wide bandgap semiconductor Well
Area (10), P+ wide bandgap semiconductors area (2) are located at channel bottom, and the areas p-type wide bandgap semiconductor Well (10) are located at the broad stopbands P+
Semiconductor region (2) upper surface；The upper surface in the part areas p-type wide bandgap semiconductor Well (10) is in contact with metal anode (1), portion
Point areas p-type wide bandgap semiconductor Well (10) and the upper surface of part N- wide bandgap semiconductors epitaxial layer (3), which have, to be contacted
Dielectric layer (8)；Dielectric layer (8) has the low energy gap contacted with part N- wide bandgap semiconductors epitaxial layer (3) upper surface
Semiconductor region (7)；The low-gap semiconductor area (7), dielectric layer (8), the areas p-type wide bandgap semiconductor Well (10) and N- wide
Bandgap semiconductor epitaxial layer (3) forms super barrier structure, the low-gap semiconductor area (7) and N- wide bandgap semiconductor epitaxial layers
(3) hetero-junctions is formed, P+ wide bandgap semiconductors area (2) forms PN junction with N- wide bandgap semiconductors epitaxial layer (3).
2. a kind of diode component according to claim 1, it is characterised in that：Further include directly being connect with metal anode (1)
Tactile N+ wide bandgap semiconductors source region (9), N+ wide bandgap semiconductors source region (9) are located at the areas p-type wide bandgap semiconductor Well (10)
Top layer, the areas p-type wide bandgap semiconductor Well (10) are isolated by N+ wide bandgap semiconductors source region (9) and metal anode (1),
The upper surface of part N+ wide bandgap semiconductors source region (9) is in contact with dielectric layer (8).
3. a kind of diode component according to claim 2, it is characterised in that：P+ wide bandgap semiconductors area (2) and ground are short
It connects or floating is arranged.
4. a kind of diode component according to claim 1, it is characterised in that：It further include P+ wide bandgap semiconductors contact zone
(6) and N+ wide bandgap semiconductors source region (9), P+ wide bandgap semiconductors contact zone (6) and the areas p-type wide bandgap semiconductor Well
(10) it is located at P+ wide bandgap semiconductors area (2) upper surface side by side, N+ wide bandgap semiconductors source region (9) is located at p-type broad stopband and partly leads
The top layer in the areas body Well (10), and P+ wide bandgap semiconductors contact zone (6) is in contact with N+ wide bandgap semiconductors source region (9)；P+
Wide bandgap semiconductor contact zone (6) and part N+ wide bandgap semiconductors source region (9) upper surface are in contact with metal anode 1, part N
The upper surface of+wide bandgap semiconductor source region (9) is in contact with dielectric layer (8).
5. a kind of diode component according to claim 1, it is characterised in that：The width in P+ wide bandgap semiconductors area (2)
More than the width of groove.
6. a kind of diode component according to claim 1, it is characterised in that：P+ wide bandgap semiconductors area (2) and N- wide
Bandgap semiconductor epitaxial layer (3) forms superjunction knot.
7. a kind of diode component according to claim 1, it is characterised in that：N- wide bandgap semiconductors epitaxial layer (3) pushes up
The doping concentration of layer compares the doping concentration higher under its top layer.
8. a kind of diode component according to claim 1, it is characterised in that：P+ wide bandgap semiconductors area (2) top layer
Doping concentration compares the doping concentration higher under its top layer.
9. a kind of production method of diode component, which is characterized in that include the following steps：
Step 1：Select semiconductor material with wide forbidden band as N+ wide bandgap semiconductors substrate (4) and N- wide bandgap semiconductor epitaxial layers
(3)；
Step 2：By trench etch process, the groove positioned at N- wide bandgap semiconductors epitaxial layer (3) both sides is formed；
Step 3：By deposit and etching technics, either ion implantation technology is deposited in channel bottom or is injected in beneath trenches
P-type semiconductor material with wide forbidden band is formed P+ wide bandgap semiconductors area (2)；
Step 4：By deposit and etching technics or epitaxy technique, it is wide to form p-type in P+ wide bandgap semiconductors area (2) upper surface
The areas bandgap semiconductor Well (10)；
Step 5：By dry-oxygen oxidation or depositing technics, partly led in the areas p-type wide bandgap semiconductor Well (10) and the broad stopbands N-
Body epitaxial layer (3) upper surface dielectric layer deposited material, and the etched extra dielectric layer material of removal, it is wide to form covering part p-type
The dielectric layer (8) of the areas bandgap semiconductor Well (10) and part N- wide bandgap semiconductors epitaxial layer (3)；
Step 6：It is narrow in dielectric layer (8) and the deposit of N- wide bandgap semiconductors epitaxial layer (3) upper surface by deposit and etching technics
Bandgap semiconductor material, and the etched extra low-gap semiconductor material of removal, form positioned at dielectric layer (8) and the broad stopbands N- half
Low-gap semiconductor area (7) on conductor epitaxial layer (3)；
Step 7：By deposit, photoetching and etching technics, partly led in low-gap semiconductor (7), dielectric layer (8) and p-type broad stopband
The upper surface in the areas body Well (10) forms metal anode (1), and overturning device overleaf forms metallic cathode (5), so far completes device
The making of part.
10. a kind of production method of diode component according to claim 1, it is characterised in that：Before the step 5 also
Include the following steps：By photoetching, ion implantation technology, N+ wide taboos are formed in p-type wide bandgap semiconductor Well area (10) top layer
Band semiconductor source region (9), metal anode 1 and dielectric layer (8) are made in N+ wide bandgap semiconductors source region (9) upper surface respectively, or
Person is formed and p-type wide bandgap semiconductor Well by photoetching, ion implantation technology in P+ wide bandgap semiconductors area (2) upper surface
Area (10) P+ wide bandgap semiconductors contact zone (6) arranged side by side is formed and P+ wide in p-type wide bandgap semiconductor Well area (10) top layer
The N+ wide bandgap semiconductors source region (9) that bandgap semiconductor contact zone (6) is in contact, in P+ wide bandgap semiconductors contact zone (6) and
Part N+ wide bandgap semiconductors source region (9) upper surface makes metal anode 1, part N+ wide bandgap semiconductors source region (9) upper surface
Make dielectric layer (8).
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080023707A1 (en) * | 2006-07-27 | 2008-01-31 | Nissan Motor Co., Ltd. | Semiconductor device and method of producing the semiconductor device |
| JP2017216297A (en) * | 2016-05-30 | 2017-12-07 | 株式会社東芝 | Semiconductor device |
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2018
- 2018-06-01 CN CN201810553843.2A patent/CN108550630B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080023707A1 (en) * | 2006-07-27 | 2008-01-31 | Nissan Motor Co., Ltd. | Semiconductor device and method of producing the semiconductor device |
| JP2017216297A (en) * | 2016-05-30 | 2017-12-07 | 株式会社東芝 | Semiconductor device |
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| CN116072708A (en) * | 2023-03-07 | 2023-05-05 | 青岛嘉展力芯半导体有限责任公司 | Diode, preparation method thereof and electronic device |
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