CN116344587A - Groove type silicon carbide MOSFET device and preparation process thereof - Google Patents
Groove type silicon carbide MOSFET device and preparation process thereof Download PDFInfo
- Publication number
- CN116344587A CN116344587A CN202310461968.3A CN202310461968A CN116344587A CN 116344587 A CN116344587 A CN 116344587A CN 202310461968 A CN202310461968 A CN 202310461968A CN 116344587 A CN116344587 A CN 116344587A
- Authority
- CN
- China
- Prior art keywords
- type
- concentration
- region
- silicon carbide
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 92
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 85
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 230000004888 barrier function Effects 0.000 claims description 53
- 210000000746 body region Anatomy 0.000 claims description 47
- 150000002500 ions Chemical class 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 17
- 238000000137 annealing Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000008569 process Effects 0.000 description 14
- 230000005684 electric field Effects 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- -1 aluminum ions Chemical class 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention provides a groove type silicon carbide MOSFET device and a preparation process thereof, wherein the MOSFET device comprises a high-concentration N-type drain electrode and drain electrode metal, a low-concentration N-type epitaxial layer is arranged on the high-concentration N-type drain electrode, a P-type well region is arranged above the N-type epitaxial layer, a high-concentration N-type source electrode and a high-concentration P-type source electrode are arranged on the surface of the P-type well region, a longitudinal groove is arranged on one end surface of the N-type epitaxial layer far away from the high-concentration N-type drain electrode, polysilicon is arranged in the longitudinal groove, the periphery of the polysilicon is wrapped by a gate oxide layer, a P-type doped region is further arranged in the N-type epitaxial layer in a region right below the bottom of the longitudinal groove, the P-type doped region extends towards a direction close to the high-concentration N-type drain electrode, and contact holes and a dielectric layer are further arranged on the surfaces of the high-concentration N-type source electrode and the high-concentration P-type source electrode. The invention can provide comprehensive protection for the gate oxide layer of the device, meanwhile, the formation of the P-type doped region does not need to use a mask plate, thereby improving the precision and reducing the cost.
Description
Technical Field
The invention relates to a semiconductor device, in particular to a groove type silicon carbide MOSFET device and a preparation process thereof.
Background
Compared with the traditional silicon-based power device, the silicon carbide (SiC) MOSFET device is characterized by high breakdown voltage, low on-resistance, small switching loss and the like, is generally used in the high-voltage field of 650V and above due to the advantages, and can replace the silicon-based superjunction MOSFET device and the high-voltage IGBT device to be applied to the fields of new energy automobiles, photovoltaic power generation, high-voltage inverters and the like.
The most used 4H-SiC material in the power device has a forbidden band width three times that of the silicon material, and the critical breakdown field strength is generally proportional to the square of the forbidden band width, so that the critical breakdown field strength of the 4H-SiC material is 9-10 times that of the silicon material, specifically, the critical breakdown field strength of the silicon material is 300kV/cm, and the critical breakdown field strength of the 4H-SiC material is 3000kV/cm. For a SiC MOSFET device, a thin gate oxide layer is generally disposed on the surface of SiC, and the thickness of the gate oxide layer is generally about tens of nanometers, polysilicon is disposed above the oxide layer to serve as a gate of the device, and when the surface of the SiC MOSFET device bears a relatively high electric field, the electric field in the gate oxide layer is generally about 3 times higher than that in SiC, so that the gate oxide layer of the SiC MOSFET device is particularly fragile, and the electric field in the gate oxide layer needs to be reduced as much as possible during device design, so that breakdown of the gate oxide layer is avoided, and failure of the SiC MOSFET device is caused.
Disclosure of Invention
The invention aims to provide a groove type silicon carbide MOSFET device and a preparation process thereof, which can provide comprehensive protection for a gate oxide layer of the device, and meanwhile, a mask plate is not required to be used for forming a P type doped region, so that the precision of a production process is improved, and the process production cost is reduced.
In order to achieve the technical purpose, the technical scheme adopted by the embodiment of the invention is as follows:
in a first aspect, an embodiment of the present invention provides a trench silicon carbide MOSFET device, including a high-concentration N-type drain and a drain metal, where a low-concentration N-type epitaxial layer is disposed on the high-concentration N-type drain as a drift region of the MOSFET device, a P-type well region is disposed above the N-type epitaxial layer, a high-concentration N-type source and a high-concentration P-type source are further disposed on a surface of the P-type well region, a longitudinal trench is disposed on a surface of one end of the N-type epitaxial layer far from the high-concentration N-type drain, polysilicon is disposed inside the longitudinal trench, a periphery of the polysilicon is wrapped by a gate oxide layer, an implantation depth of the P-type well region in the N-type epitaxial layer is smaller than a depth of the longitudinal trench, a P-type doped region is further disposed in the N-type epitaxial layer in a region directly below a bottom of the longitudinal trench, a width of the P-type doped region is smaller than or equal to a width of the longitudinal trench, the P-type doped region extends in a direction close to the high-concentration N-type drain, contact holes are further disposed on a surface of the high-concentration N-type source and a contact hole is further disposed on a surface of the N-type source, the high-concentration N-type epitaxial layer is further, the contact hole is further disposed on the surface of the N-type epitaxial layer, and the contact hole is used to connect to a signal layer to a contact hole to a surface other dielectric layer;
at least one P-type body region is arranged in the direction perpendicular to the transverse extending direction of the longitudinal groove, when the number of the P-type body regions is greater than one, the P-type body regions are distributed at intervals and in parallel, the upper surface of the P-type body region overlaps the P-type well region, and the lower surface of the P-type body region is positioned above the lower surface of the P-type doped region;
or a P-type body region is arranged on one side of the longitudinal groove, the upper surface of the P-type body region is overlapped with the P-type well region, and the lower surface of the P-type body region is positioned above the lower surface of the P-type doped region.
Preferably, the thickness of the gate oxide layer at the bottom of the longitudinal groove is larger than that of the gate oxide layers at two sides.
Further, the N-type epitaxial layer comprises a plurality of epitaxial layers, and the doping concentrations of different epitaxial layers are different.
Preferably, the N-type epitaxial layer comprises two layers of epitaxial layers, a first epitaxial layer is arranged on the high-concentration N-type drain electrode, a second epitaxial layer is arranged above the first epitaxial layer, the thickness of the first epitaxial layer is 1-20 μm, and the thickness of the second epitaxial layer is 3-20 μm.
Further, the high-concentration N-type source electrodes are positioned on two sides of the longitudinal groove, and the high-concentration P-type source electrodes are alternately arranged between two adjacent high-concentration N-type source electrodes.
Further, the high-concentration N-type source electrode and the high-concentration P-type source electrode are distributed at intervals in a direction perpendicular to the transverse extending direction of the longitudinal groove.
Further, an N-type doped region is further arranged in the N-type epitaxial layer between the adjacent P-type doped regions or the adjacent longitudinal grooves, and the concentration of the N-type doped region is higher than that of the N-type epitaxial layer.
Preferably, the doping concentration of the P-type doped region is 1E13cm -3 ~1E21cm -3 The doping concentration of the P-type well region is 1E13cm -3 ~1E17cm -3 。
In a second aspect, an embodiment of the present invention provides a process for preparing a trench silicon carbide MOSFET device, applied to a first portion of the trench silicon carbide MOSFET device, including the steps of:
s1, selecting an N-type substrate material as a high-concentration N-type drain electrode of a device, and epitaxially growing an N-type epitaxial layer for one time or multiple times to obtain a silicon carbide epitaxial wafer;
s2, injecting acceptor ions into the surface of the N-type epitaxial layer by using a mask plate of the P-type well region to form a P-type well region, injecting acceptor ions into the surface of the N-type epitaxial layer by using a mask plate of the P-type body region to form a P-type body region, and injecting donor ions into the P-type body region to form a high-concentration N-type source electrode by using the mask plate respectively;
s3, depositing a first barrier layer on the surface of the N-type epitaxial layer, removing the first barrier layer in the longitudinal groove area by using a mask, and further etching silicon carbide to form a longitudinal groove;
s4, depositing a second barrier layer on the surface of the silicon carbide epitaxial wafer, etching the second barrier layer at the bottom of the longitudinal groove, and reserving the second barrier layer on the side wall of the longitudinal groove;
s5, implanting acceptor ions on the surface of the silicon carbide epitaxial wafer by using an ion implantation method to form a P-type doped region with the width smaller than or equal to the width of the longitudinal groove;
step S6, etching the second barrier layer and the first barrier layer remained on the surface of the silicon carbide epitaxial wafer, and then performing high-temperature annealing to activate impurity ions implanted into the silicon carbide;
step S7, growing a gate oxide layer in the longitudinal groove, and then depositing polysilicon in the groove;
s8, depositing a dielectric layer on the surface of the silicon carbide epitaxial wafer, selectively etching a contact hole on the dielectric layer, depositing metal in the contact hole, forming ohmic contact between the metal and the high-concentration N-type source electrode and between the metal and the high-concentration P-type source electrode after high-temperature annealing, and selectively etching the metal to form source electrode metal;
and S9, thinning the N-type substrate, depositing drain metal at the bottom of the high-concentration N-type drain electrode, and forming ohmic contact between the drain metal and the N-type substrate after high-temperature annealing.
In a third aspect, an embodiment of the present invention provides a process for manufacturing a trench silicon carbide MOSFET device, applied to a first portion of the trench silicon carbide MOSFET device, where a P-type well region and a P-type doped region are formed simultaneously, including the steps of:
firstly, selecting an N-type substrate material as a high-concentration N-type drain electrode of a device, and epitaxially growing an N-type epitaxial layer for one time or multiple times to obtain a silicon carbide epitaxial wafer;
injecting acceptor ions into the surface of the N-type epitaxial layer by using a mask plate of the P-type body region to form a P-type body region, injecting donor ions into the surface of the N-type epitaxial layer by using the mask plate, and injecting acceptor ions to form a high-concentration N-type source;
step three, etching the surface of the N-type epitaxial layer by using a mask plate to form a longitudinal groove;
depositing a second barrier layer on the surface of the silicon carbide epitaxial wafer, etching the second barrier layer at the bottom of the longitudinal groove, and reserving the second barrier layer on the side wall of the longitudinal groove;
injecting acceptor ions on the surface of the silicon carbide epitaxial wafer by using an ion injection method to form a P-type well region and a P-type doped region at the same time;
step six, etching the remaining second barrier layer on the surface of the silicon carbide epitaxial wafer, and then carrying out high-temperature annealing to activate impurity ions implanted into the silicon carbide;
and step seven to step nine are consistent with step S7 to step S9 in the second part.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
(1) The trench type silicon carbide MOSFET device provided by the invention is provided with the deeper P-type doped region at the bottom of the trench gate, and the P-type doped region is 0.1-5 mu m deeper than the longitudinal trench, so that the electric field intensity at the gate-oxide interface can be effectively reduced, and the reliability of the device is improved.
(2) In the preparation of the P-type doping region of the groove type silicon carbide MOSFET device, a second barrier layer is deposited on the surface of a silicon carbide epitaxial wafer, then the second barrier layer is etched, the second barrier layer at the bottom of a longitudinal groove is etched, and the second barrier layer on the side wall of the longitudinal groove is reserved; implanting acceptor ions on the surface of the silicon carbide epitaxial wafer by using an ion implantation method to form a P-type doped region with the width smaller than or equal to that of the longitudinal groove; the self-alignment process method can accurately form the P-type doped region at the bottom of the longitudinal groove without using a mask plate, and reduces the preparation difficulty and the production cost of the device. The conventional use of the mask plate to form the P-type doped region has an alignment error between the mask plate and the longitudinal groove, so that it is difficult to precisely form the P-type doped region at the bottom of the longitudinal groove, and the yield of devices is reduced once the P-type doped region deviates from the bottom of the longitudinal groove, thereby increasing the production cost.
Drawings
Fig. 1 is a schematic cross-sectional view of a trench silicon carbide MOSFET device according to embodiment 1 of the present invention.
Fig. 2 is a top view of a trench silicon carbide MOSFET device according to embodiment 2 of the present invention.
Fig. 3 is a schematic diagram showing a cross-sectional structure of a trench silicon carbide MOSFET device along the BB' direction in embodiment 2 of the present invention.
Fig. 4 is a schematic diagram showing a cross-sectional structure of a trench silicon carbide MOSFET device along the AA' direction in embodiment 2 of the present invention.
Fig. 5 is a top view of a trench silicon carbide MOSFET device in accordance with example 3 of the present invention.
Fig. 6 is a schematic diagram showing a cross-sectional structure of a trench silicon carbide MOSFET device along the AA' direction in embodiment 3 of the present invention.
Fig. 7 is a schematic cross-sectional structure of the N-type epitaxial layer in example 4.
Fig. 8 is a schematic cross-sectional view of the P-type body region, the P-type well region, the high-concentration N-type source and the high-concentration P-type source in embodiment 4.
Fig. 9 is a schematic cross-sectional structure of embodiment 4 after the etching of the longitudinal grooves is completed.
FIG. 10 is a schematic cross-sectional view of the second barrier layer deposition of example 4.
Fig. 11 is a schematic cross-sectional view of the second barrier layer after etching in embodiment 4.
Fig. 12 is a schematic cross-sectional view of the P-type doped region of embodiment 4 after implantation.
Fig. 13 is a schematic cross-sectional structure of example 4 after etching the first barrier layer and the second barrier layer.
Fig. 14 is a schematic cross-sectional structure after the gate oxide growth and polysilicon filling are completed in example 4.
Fig. 15 is a schematic cross-sectional structure after the source metal deposition is completed in example 4.
Fig. 16 is a schematic cross-sectional structure after the drain metal deposition is completed in example 4.
Fig. 17 is a schematic cross-sectional structure of the high-concentration N-type source electrode and the high-concentration P-type source electrode of embodiment 5.
Fig. 18 is a schematic sectional view of the structure of embodiment 5 after the etching of the longitudinal grooves is completed.
FIG. 19 is a schematic cross-sectional view showing the structure after the second barrier layer deposition in example 5.
Fig. 20 is a schematic cross-sectional view of the second barrier layer after etching in embodiment 5.
Fig. 21 is a schematic cross-sectional structure of the P-type well region and the P-type doped region in embodiment 5.
Fig. 22 is a schematic cross-sectional structure of embodiment 5 after etching away the second barrier layer.
Reference numerals illustrate: 01-drain metal; 02-high concentration N-type drain; 03-N type epitaxial layer; 04-P type doped region; 05-longitudinal grooves; 06-polysilicon: 07-gate oxide; 08-P type well region; 09—high concentration N-type source; 10-high concentration P-type source; 11-contact holes; 12-a dielectric layer; 13-source metal; 14—a first barrier layer; 15-a second barrier layer; a 16-P type body region; 101-silicon carbide epitaxial wafer.
Detailed Description
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
As shown in fig. 1, a trench silicon carbide MOSFET device includes a drain metal 01 and a high concentration N-type drain 02 above the drain metal, a low concentration N-type epitaxial layer 03 is disposed on the high concentration N-type drain 02 as a drift region of the MOSFET device, a P-type well region 08 is disposed above the N-type epitaxial layer 03, a high concentration N-type source 09 and a high concentration P-type source 10 are further disposed on a surface of the P-type well region 08, a longitudinal trench 05 is disposed on a surface of one end of the N-type epitaxial layer 03 far from the high concentration N-type drain 02, polysilicon 06 is disposed inside the longitudinal trench 05, an outer periphery of the polysilicon 06 is surrounded by a gate oxide layer 07, an implantation depth of the P-type well region 08 in the N-type epitaxial layer 03 is smaller than a depth of the longitudinal trench 05, a P-type doped region 04 is further disposed in the N-type epitaxial layer 03 in a region directly below a bottom of the longitudinal trench 05, a width of the P-type doped region 04 is smaller than or equal to a width of the longitudinal trench 05, the P-type doped region 04 extends in a direction close to the high concentration N-type drain 02, a contact hole 11 is further disposed on a surface of the high concentration N-type source 09 and the high concentration P-type source 10, a contact hole 11 is further disposed on a surface of the high concentration N-type source 09 is further disposed on the P-type source 11, and a contact hole 11 is further disposed on a contact hole 11 is further for connecting the N-type source electrode 11 to a surface to a contact hole 12, and a contact hole 12 is further disposed on a surface of the metal layer.
As an embodiment, the thickness of the gate oxide layer 07 at the bottom of the vertical trench 05 is greater than that of the gate oxide layers 07 at the two sides, and the thicker bottom oxide layer can improve the gate oxide reliability of the device.
As an embodiment, the N-type epitaxial layer 03 includes multiple epitaxial layers, and the doping concentrations of the different epitaxial layers are different, so that the on-resistance of the device can be further reduced by using the multiple epitaxial layers.
Specifically, the N-type epitaxial layer 03 in this embodiment includes two epitaxial layers, a first epitaxial layer is disposed on the high-concentration N-type drain electrode 02, a second epitaxial layer is disposed above the first epitaxial layer, the thickness of the first epitaxial layer ranges from 1 μm to 20 μm, and the thickness of the second epitaxial layer ranges from 3 μm to 20 μm.
The more the number of epitaxial layers, the higher the cost of the device, and in order to achieve a better compromise between the cost of the device and the performance of the device, it is preferable to use a process of two epitaxy, i.e. the N-type epitaxial layer 03 is preferably a two-layer epitaxial layer.
The high-concentration N-type source electrode 09 is positioned at two sides of the longitudinal groove 05, and the high-concentration P-type source electrode 10 is alternately inserted between two adjacent high-concentration N-type source electrodes 09.
An N-type doped region is also arranged in the N-type epitaxial layer 03 between the adjacent longitudinal grooves 05, and the concentration of the N-type doped region is higher than that of the N-type epitaxial layer 03.
An N-type doped region is further arranged in the N-type epitaxial layer 03 between the adjacent P-type doped regions 04, and the concentration of the N-type doped region is higher than that of the N-type epitaxial layer 03.
The additional N-type doping is mainly aimed at increasing the doping concentration of the N-type epitaxial layer and reducing the on-resistance of the device, especially in the region adjacent to the longitudinal trenches 05 or between adjacent P-type doped regions 04, since this region is typically smaller in width, e.g. 0.1um. According to the resistance formula r=ρl/S, where L is the length, ρ is the resistivity and S is the cross-sectional area of the flow-through region. In this embodiment, the cross-sectional area of the current flowing through the region is smaller, i.e. S is smaller, so that the resistance R is larger, and by adding an additional N-type doped region, the resistivity ρ can be effectively reduced, and the on-resistance R of the region is reduced.
The doping concentration of the P-type doped region 04 is 1E17cm -3 ~1E21cm -3 The doping concentration range of the P-type well region 08 is 1E13cm -3 ~1E17cm -3 The higher concentration of the P-type doped region 04 can effectively reduce the electric field strength in the gate oxide layer.
The trench silicon carbide MOSFET device provided by the embodiment can provide better protection for the gate oxide layer, and reduce the electric field in the gate oxide layer, thereby improving the reliability of the device, and the principle is as follows: when the device is turned off, the source electrode and the gate electrode are grounded, the drain electrode is in charge of high voltage, the N-type epitaxial layer 03 is exhausted with the P-type doped region 04 and the P-type well region 08 to charge high voltage, in general, the electric field at the center of the exhausted region is strongest, if the P-type doped region 04 is not arranged, the strongest electric field is positioned at the corner position of the longitudinal groove 05, the electric field intensity in the gate oxide layer 07 can be sharply increased, the P-type doped region in the invention is deeply penetrated into the N-type epitaxial layer, so that the N-type epitaxial layer is exhausted preferentially, and the exhausted center is transferred to the corner position of the P-type doped region 04 from the corner position of the longitudinal groove 05, so that the electric field intensity is strongest, the gate oxide layer 07 is in principle, the electric field intensity in the oxide layer is reduced, and the reliability of the device is improved.
Example 2
The trench type silicon carbide MOSFET device comprises a drain metal 01 and a high-concentration N-type drain 02 above the drain metal, wherein a low-concentration N-type epitaxial layer 03 is arranged on the high-concentration N-type drain 02 as a drift region of the MOSFET device, a P-type well region 08 is arranged above the N-type epitaxial layer 03, a high-concentration N-type source 09 and a high-concentration P-type source 10 are also arranged on the surface of the P-type well region 08, and the high-concentration N-type source 09 and the high-concentration P-type source 10 are distributed at intervals and in parallel in a direction perpendicular to the transverse extending direction of a longitudinal trench 05; a longitudinal groove 05 is formed in the surface of one end, far away from the high-concentration N-type drain electrode 02, of the N-type epitaxial layer 03, polycrystalline silicon 06 is arranged in the longitudinal groove 05, the periphery of the polycrystalline silicon 06 is wrapped by a gate oxide layer 07, the injection depth of a P-type well region 08 in the N-type epitaxial layer 03 is smaller than the depth of the longitudinal groove 05, a P-type doped region 04 is further arranged in the N-type epitaxial layer 03 in the area right below the bottom of the longitudinal groove 05, the width of the P-type doped region 04 is smaller than or equal to the width of the longitudinal groove 05, the P-type doped region 04 extends towards the direction close to the high-concentration N-type drain electrode 02, contact holes 11 are further formed in the surfaces of the high-concentration N-type source electrode 09 and the high-concentration P-type source electrode 10, the contact holes 11 are used for connecting source signals to source electrodes 13, and dielectric layers 12 are further arranged in other areas, except the contact holes 11, on the surface of the N-type epitaxial layer 03.
In this embodiment, the high-concentration N-type source 09 and the high-concentration P-type source 10 are distributed at intervals in a direction perpendicular to the transverse extending direction of the longitudinal trench 05, so that the cell size Wcell of the device can be reduced, as shown in fig. 2, the cell refers to the smallest repeatable unit in the power device, the cell size refers to the size of the smallest repeatable unit, and the power device is a device structure formed by the same cell structures according to a certain arrangement method, so that the reduction of the cell size means the increase of the number of cells in the same area, thereby improving the current capability of the power device and reducing the on-resistance of the device.
Example 3
A groove type silicon carbide MOSFET device is shown in figures 1, 5 and 6, and comprises a drain metal 01 and a high-concentration N-type drain 02 above the drain metal, wherein a low-concentration N-type epitaxial layer 03 is arranged on the high-concentration N-type drain 02 and used as a drift region of the MOSFET device, a P-type well region 08 is arranged above the N-type epitaxial layer 03, a high-concentration N-type source 09 and a high-concentration P-type source 10 are further arranged on the surface of the P-type well region 08, a longitudinal groove 05 is arranged on one end surface of the N-type epitaxial layer 03 far from the high-concentration N-type drain 02, polysilicon 06 is arranged inside the longitudinal groove 05, the periphery of the polysilicon 06 is wrapped by a gate oxide layer 07, a P-type doped region 04 is further arranged in the N-type epitaxial layer 03, the P-type doped region 04 is arranged in the N-type epitaxial layer 03 in the region of the region right lower portion of the bottom of the longitudinal groove 05, the P-type doped region 04 is smaller than or equal to the width of the longitudinal groove 05, the P-type doped region 04 extends towards the direction close to the high-concentration N-type drain 02, a P-type channel region 16 is arranged in the direction perpendicular to the direction of the longitudinal groove 05, a P-type body region 16 is arranged on the surface of the N-type epitaxial layer 03, a contact region 16 is further arranged on the surface of the P-type well region 16 is further overlapped with the surface of the P-type source region 11, and the P-type epitaxial layer 11 is further arranged on the surface of the P-type epitaxial layer 11 is further, and the surface of the P-type epitaxial layer is in contact region 11 is in contact with the surface of the P-type source region 11, and the surface is further arranged on the surface of the P-type source region 11 is in contact region 11, and the surface of the surface was in contact region 11 is in contact region is in contact with the surface of the surface region 11, and is in the surface region is in the surface of the surface region was and is in the surface of the P-type region was and is.
As shown in fig. 5, the top view of the embodiment is that the high-concentration N-type source 09 and the high-concentration P-type source 10 are located above the P-type body region 16 in fig. 5, and the layers of the P-type body region 16 are shown for convenience in showing the positional relationship between the P-type body region 16 and the high-concentration N-type source 09 and the high-concentration P-type source 10.
The device structure shown in the BB 'section is identical to the device cross-sectional structure shown in embodiment 1, and the cross-sectional structure of the AA' section is shown in fig. 6, where P-type body region 16 connects P-type doped region 04 and P-type well region 08.
When the device is impacted by avalanche, holes in the drift region can be quickly absorbed by the P-type doped region 04 penetrating into the drift region, and then are extracted by the source metal 13 through the P-type body region 16, the P-type well region 08 and the high-concentration P-type source electrode 10, so that the groove-type silicon carbide MOSFET device provided by the embodiment can effectively improve the avalanche capacity of the device and enhance the reliability of the device.
At least one P-type body region 16 is provided in a direction perpendicular to the lateral extension direction of the longitudinal grooves 05. The P-type body regions 16 spaced in a direction perpendicular to the lateral extending direction of the longitudinal trenches 05 inevitably affect the on-resistance of the device, because the AA' cross section has no electron current in the on state, and the on-resistance and avalanche capability of the device can be simultaneously achieved by providing at least one P-type body region.
Specifically, a P-type body region 16 is disposed at one side of the longitudinal trench 05, an upper surface of the P-type body region 16 overlaps the P-type well region 08, and a lower surface of the P-type body region 16 is located above a lower surface of the P-type doped region 04. In this way, the P-type body region 16 connects the P-type doped region 04 and the P-type well region 08, and the source metal can directly draw out the hole current in the P-type doped region 04, so that the advantage of this arrangement is that the hole current can directly flow upwards to the source metal through the P-type body region 16, and is not conducted along the direction parallel to the longitudinal grooves, so that the conduction path of the hole current is reduced, that is, the EMI interference to the gate of the device is reduced, and the reliability of the device is improved.
Example 4
The preparation process of the trench silicon carbide MOSFET device in this embodiment selects the cross-sectional structure shown by the AA' section in embodiment 3 as an example, and shows the process method, and for other embodiments, the process method provided in this embodiment can also be realized by similar steps, and includes the following steps:
step S1: as shown in fig. 7, an N-type silicon carbide substrate is selected as a high-concentration N-type drain 02 of the device, wherein the silicon carbide substrate is made of 4H-SiC, 6H-SiC or 3C-SiC, and the like, and is generally made of 4H-SiC material at most, and a silicon carbide N-type epitaxial layer 03 is formed through single or multiple epitaxial growth to obtain a silicon carbide epitaxial wafer 101; the concentration of the silicon carbide N-type epitaxial layer 03 will generally be much lower than the substrate concentration, the thickness of which is related to the doping concentration and the breakdown voltage of the device;
step S2: as shown in fig. 8, a region where a P-type well region 08 needs to be formed on the surface of an N-type epitaxial layer 03 is exposed by photolithography using a mask, acceptor ions are implanted to form the P-type well region 08, acceptor ions are re-implanted on the surface of the N-type epitaxial layer 03 to form a P-type body region 16, donor ions are re-implanted on the surface of the N-type epitaxial layer 03 to form a high-concentration N-type source 09, and acceptor ions are re-implanted on the surface of the N-type epitaxial layer 03 to form a high-concentration P-type source 10 by the same technical means. If additional N-type doping is also arranged in the N-type epitaxial layer, the same technical means can be used for realizing the N-type epitaxial layer. Common acceptor ions include B, al, ga, in, etc., and common donor ions include P, N, as, sb, etc. In summary, this step requires multiple reticles to form different doped regions, and for embodiments 1 and 2 without P-type body region 16, reticles for P-type body region 16 may be omitted;
step S3: as shown in fig. 9, a first barrier layer 14 is deposited on the surface of the N-type epitaxial layer 03, then a mask is used to remove the first barrier layer 14 in the area of the longitudinal groove 05, and silicon carbide is further etched to form the longitudinal groove 05;
the first barrier layer 14 is formed using various dielectrics such as silicon nitride, silicon oxide, or polysilicon;
for example 3 with P-type body region 16, the depth of longitudinal trench 05 should not exceed the depth of P-type body region 16.
Step S4: as shown in fig. 10, a second barrier layer 15 is deposited on the surface of the silicon carbide epitaxial wafer 101 and in the longitudinal groove 05, the second barrier layer 15 may be made of silicon nitride, silicon oxide, polysilicon or other materials, then the second barrier layer 15 is etched, and the second barrier layer 15 with a thickness of several hundred angstroms may be left at the bottom of the groove as an ion implantation barrier layer, so that damage of the ion implantation to the silicon carbide wafer can be effectively reduced, or the N-type epitaxial layer is directly etched to the bottom of the longitudinal groove 05. The wafer surface is generally bombarded by using a dry etching technology, namely, plasma is used for removing the material with specified thickness on the surface, so that the oxide layer on the side wall part of the groove only etches away part of the outermost surface due to the thicker thickness of the oxide layer, and the oxide layer at the bottom is basically completely etched, as shown in fig. 11;
step S5: as shown in fig. 12, the P-type doped region 04 is formed by implanting aluminum ions into the wafer surface by ion implantation, and the P-type doped region 04 is formed only at the bottom of the trench because the wafer surface is covered by the first barrier layer 14 and the trench sidewall is protected by the second barrier layer 15;
step S6: as shown in fig. 13, the second barrier layer 15 remaining in the trench and the first barrier layer 14 on the wafer surface are etched, and a wet etching method is generally used, that is, different solvents are used for different media to remove the media, and then high-temperature annealing is performed to activate impurity ions implanted into silicon carbide, where a typical annealing temperature is above 1600 ℃, and different gases, such as hydrogen or argon, are added during the annealing according to different processes.
Step S7: as shown in fig. 14, a gate oxide layer 07 is grown in the longitudinal trenches 05, followed by the deposition of polysilicon 06 in the trenches, where a higher doping concentration of polysilicon is typically used, in order to facilitate lower gate resistance;
step S8: as shown in fig. 15, a dielectric layer 12, typically silicon oxide, oxynitride or polyimide, is deposited on the surface of a silicon carbide epitaxial wafer 101, then a contact hole 11 is selectively etched on the dielectric layer 12, then a metal is deposited in the contact hole 11, after high-temperature annealing, the metal forms ohmic contact with a high-concentration N-type source 09 and a high-concentration P-type source 10, and then the metal is selectively etched to form a source metal 13;
the metal may be Ni, ti, W, mo, cu, al or an alloy of various metal materials, and the high-temperature annealing may be Rapid Thermal Annealing (RTA), i.e. high-temperature treatment of the silicon carbide epitaxial wafer in a short time (several minutes).
Step S9: as shown in fig. 16, the N-type substrate is thinned, the thickness of the substrate is generally above 300 μm before thinning, the thickness of the substrate is below 200 μm after thinning, fig. 16 is only a schematic view, no change of the thickness of the substrate is shown, the purpose of substrate thinning is to further reduce the substrate resistance of the device, then the drain metal 01 is deposited at the bottom of the high-concentration N-type drain 02, and ohmic contact is formed between the drain metal 01 and the N-type substrate after high-temperature annealing.
The process method provided by the invention does not need to use a mask plate to define the pattern of the P-type doped region, and can realize self-aligned injection of the P-type doped region in the process, so that the exposure precision of the mask plate is not required to be considered in preparation, the number of the mask plate can be effectively saved, the production yield is improved, and the production cost of devices is reduced.
Example 5
The process of the present embodiment takes the trench type silicon carbide MOSFET device in embodiment 1 as an example, and the trench type silicon carbide MOSFET devices in embodiment 2 and embodiment 3 can be implemented by using the process of the present embodiment, and the process includes the following steps:
step one: as shown in fig. 7, an N-type silicon carbide substrate is selected as a high-concentration N-type drain 02 of the device, and a silicon carbide N-type epitaxial layer 03 is epitaxially grown to obtain a silicon carbide epitaxial wafer 101;
step two: as shown in fig. 17, the above method may be used to implant donor ions on the surface of the N-type epitaxial layer 03 to form a high-concentration N-type source 09 by using a mask, and implant acceptor ions to form a high-concentration P-type source 10, as in embodiment 3, when the P-type body region 16 is required to be provided;
step three: as shown in fig. 18, a mask is used to etch the surface of the N-type epitaxial layer 03 to form a longitudinal trench 05;
step four: as shown in fig. 19, a second barrier layer 15 is deposited on the surface of the silicon carbide epitaxial wafer 101, where the second barrier layer 15 may be a material such as silicon nitride, silicon oxide or polysilicon, and then the second barrier layer 15 is isotropically etched, and since the second barrier layer 15 is isotropically etched downward, a dry etching technique is generally used, i.e. the wafer surface is bombarded with plasma to remove the material with a specified thickness on the surface, so that the oxide layer on the sidewall portion of the trench is only etched to a part of its outermost surface due to its thicker thickness, and the oxide layer on the bottom is substantially entirely etched, as shown in fig. 20;
step five: as shown in fig. 21, acceptor ions are implanted on the surface of the silicon carbide epitaxial wafer 101 by an ion implantation method to form a P-type well region 08 and a P-type doped region 04;
step six: as shown in fig. 22, the remaining second barrier layer 15 on the surface of the silicon carbide epitaxial wafer 101 is etched away, followed by high-temperature annealing to activate impurity ions implanted into silicon carbide;
step seven to step nine are identical to step S7 to step S9 in example 4.
In this embodiment, the P-type well region 08 and the P-type doped region 04 are formed simultaneously, so that the process steps for preparing the device are further simplified, and the production cost of the device is reduced.
The invention and its embodiments have been described above without limitation, and only two embodiments of the invention are shown in the drawings, the actual structure not being limited thereto. In summary, if one of ordinary skill in the art is informed by this disclosure, a structural manner and an embodiment similar to the technical solution should not be creatively devised without departing from the gist of the present invention.
Claims (7)
1. The trench type silicon carbide MOSFET device comprises a high concentration N-type drain electrode (02) and drain metal (01), wherein a low concentration N-type epitaxial layer (03) is arranged on the high concentration N-type drain electrode (02) as a drift region of the MOSFET device, a P-type well region (08) is arranged above the N-type epitaxial layer (03), a high concentration N-type source electrode (09) and a high concentration P-type source electrode (10) are further arranged on the surface of the P-type well region (08), one end surface of the N-type epitaxial layer (03) far away from the high concentration N-type drain electrode (02) is provided with a longitudinal trench (05), polysilicon (06) is arranged inside the longitudinal trench (05), the periphery of the polysilicon (06) is wrapped by a gate oxide layer (07), the implantation depth of the P-type well region (08) in the N-type epitaxial layer (03) is smaller than the depth of the longitudinal trench (05), a P-type doped region (04) is further arranged in the N-type epitaxial layer (03) of a region right below the bottom of the longitudinal trench (05), the P-type doped region (04) is wider than the P-type epitaxial region is equal to the high concentration N-type epitaxial region (02), the P-type epitaxial region is further provided with a P-type doped region (04) in the depth which is close to the high concentration N-type epitaxial region (05) and is close to the high concentration N-type epitaxial region (05), the contact hole (11) is used for connecting a source electrode signal to the source electrode metal (13), and a dielectric layer (12) is arranged in other areas except the contact hole (11) on the surface of the N-type epitaxial layer (03);
at least one P-type body region (16) is arranged in the direction perpendicular to the transverse extending direction of the longitudinal groove (05), when the number of the P-type body regions (16) is greater than one, the P-type body regions (16) are distributed at intervals and in parallel, the upper surface of the P-type body region (16) is overlapped with the P-type well region (08), and the lower surface of the P-type body region (16) is positioned above the lower surface of the P-type doped region (04);
or a P-type body region (16) is arranged on one side of the longitudinal groove (05), the upper surface of the P-type body region (16) is overlapped with the P-type well region (08), and the lower surface of the P-type body region (16) is positioned above the lower surface of the P-type doped region (04).
2. A trench silicon carbide MOSFET device according to claim 1, characterized in that the N-type epitaxial layer (03) comprises a plurality of epitaxial layers, the doping concentrations of the different epitaxial layers being different.
3. The trench silicon carbide MOSFET device of claim 1, wherein the high concentration N-type sources (09) are located on either side of the longitudinal trench (05), and the high concentration P-type sources (10) are interspersed between two adjacent high concentration N-type sources (09).
4. The trench silicon carbide MOSFET device of claim 1, wherein the high concentration N-type source (09) and the high concentration P-type source (10) are spaced apart in a direction perpendicular to a lateral extension direction of the longitudinal trench (05).
5. The trench silicon carbide MOSFET device according to claim 1, characterized in that N-type doped regions are also provided in the N-type epitaxial layer (03) between the adjacent P-type doped regions (04) or adjacent longitudinal trenches (05), the N-type doped regions having a higher concentration than the N-type epitaxial layer (03).
6. A process for preparing a trench silicon carbide MOSFET device according to any one of claims 1 to 5, comprising the steps of:
s1, selecting an N-type substrate material as a high-concentration N-type drain electrode (02) of a device, and epitaxially growing an N-type epitaxial layer (03) for one time or multiple times to obtain a silicon carbide epitaxial wafer (101);
s2, injecting acceptor ions into the surface of the N-type epitaxial layer (03) by using a mask of the P-type well region (08) to form the P-type well region (08), injecting acceptor ions into the surface of the N-type epitaxial layer (03) by using a mask of the P-type body region (16) to form the P-type body region (16), and injecting donor ions into the P-type epitaxial layer to form a high-concentration N-type source electrode (09) and injecting acceptor ions into the P-type epitaxial layer (03) to form a high-concentration P-type source electrode (10);
s3, depositing a first barrier layer (14) on the surface of the N-type epitaxial layer (03), removing the first barrier layer (14) in the area of the longitudinal groove (05) by using a mask, and further etching silicon carbide to form the longitudinal groove (05);
s4, depositing a second barrier layer (15) on the surface of the silicon carbide epitaxial wafer (101), then etching the second barrier layer (15), etching the second barrier layer (15) at the bottom of the longitudinal groove (05), and reserving the second barrier layer (15) on the side wall of the longitudinal groove (05);
s5, implanting acceptor ions on the surface of the silicon carbide epitaxial wafer (101) by using an ion implantation method to form a P-type doped region (04) with the width smaller than or equal to that of the longitudinal groove (05);
step S6, etching the second barrier layer (15) and the first barrier layer (14) remained on the surface of the silicon carbide epitaxial wafer (101), and then performing high-temperature annealing to activate impurity ions implanted into the silicon carbide;
step S7, growing a gate oxide layer (07) in the longitudinal groove (05), and then depositing polysilicon (06) in the groove;
step S8, depositing a dielectric layer (12) on the surface of the silicon carbide epitaxial wafer (101), selectively etching a contact hole (11) on the dielectric layer (12), depositing metal in the contact hole (11), forming ohmic contact between the metal and the high-concentration N-type source electrode (09) and between the metal and the high-concentration P-type source electrode (10) after high-temperature annealing, and selectively etching the metal to form a source electrode metal (13);
and S9, thinning the N-type substrate, depositing drain metal (01) at the bottom of the high-concentration N-type drain electrode (02), and enabling the drain metal (01) and the N-type substrate to form ohmic contact after high-temperature annealing.
7. A process for preparing a trench silicon carbide MOSFET device, which is applied to the trench silicon carbide MOSFET device according to any one of claims 1 to 5, wherein a P-type well region (08) and a P-type doped region (04) are formed simultaneously, comprising the steps of:
firstly, selecting an N-type substrate material as a high-concentration N-type drain electrode (02) of a device, and epitaxially growing an N-type epitaxial layer (03) for one time or multiple times to obtain a silicon carbide epitaxial wafer (101);
injecting acceptor ions into the surface of the N-type epitaxial layer (03) by using a mask plate of the P-type body region (16) to form the P-type body region (16), injecting donor ions into the surface of the N-type epitaxial layer (03) by using the mask plate to form a high-concentration N-type source electrode (09), and injecting acceptor ions to form a high-concentration P-type source electrode (10);
step three, etching the surface of the N-type epitaxial layer (03) by using a mask plate to form a longitudinal groove (05);
depositing a second barrier layer (15) on the surface of the silicon carbide epitaxial wafer (101), etching the second barrier layer (15) at the bottom of the longitudinal groove (05), and reserving the second barrier layer (15) on the side wall of the longitudinal groove (05);
injecting acceptor ions on the surface of the silicon carbide epitaxial wafer (101) by using an ion injection method to form a P-type well region (08) and a P-type doped region (04) simultaneously;
step six, etching the remaining second barrier layer (15) on the surface of the silicon carbide epitaxial wafer (101), and then performing high-temperature annealing to activate impurity ions implanted into the silicon carbide;
step seven to step nine are consistent with step S7 to step S9 in claim 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310461968.3A CN116344587A (en) | 2023-04-26 | 2023-04-26 | Groove type silicon carbide MOSFET device and preparation process thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310461968.3A CN116344587A (en) | 2023-04-26 | 2023-04-26 | Groove type silicon carbide MOSFET device and preparation process thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116344587A true CN116344587A (en) | 2023-06-27 |
Family
ID=86889552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310461968.3A Pending CN116344587A (en) | 2023-04-26 | 2023-04-26 | Groove type silicon carbide MOSFET device and preparation process thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116344587A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007158275A (en) * | 2005-12-08 | 2007-06-21 | Toyota Motor Corp | Insulated gate-type semiconductor device and manufacturing method therefor |
| JP2009194065A (en) * | 2008-02-13 | 2009-08-27 | Denso Corp | Silicon carbide semiconductor device and method of manufacturing the same |
| CN101981701A (en) * | 2008-03-26 | 2011-02-23 | 罗姆股份有限公司 | Semiconductor device, and method for manufacturing the same |
| JP2011101036A (en) * | 2011-01-07 | 2011-05-19 | Denso Corp | Silicon carbide semiconductor device and manufacturing method thereof |
| US20170110571A1 (en) * | 2015-10-20 | 2017-04-20 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| CN110366782A (en) * | 2017-03-06 | 2019-10-22 | 三菱电机株式会社 | The manufacturing method of manufacturing silicon carbide semiconductor device, power-converting device, the manufacturing method of manufacturing silicon carbide semiconductor device and power-converting device |
| CN110797389A (en) * | 2018-08-02 | 2020-02-14 | 意法半导体股份有限公司 | MOSFET device with shielded region and method of making the same |
| CN112186027A (en) * | 2020-08-28 | 2021-01-05 | 派恩杰半导体（杭州）有限公司 | Silicon carbide MOSFET with grid groove structure |
| CN114496784A (en) * | 2022-04-18 | 2022-05-13 | 深圳芯能半导体技术有限公司 | Bottom protection grounding groove type silicon carbide MOSFET and preparation method thereof |
| CN114496783A (en) * | 2022-04-18 | 2022-05-13 | 深圳芯能半导体技术有限公司 | Groove type silicon carbide MOSFET prepared based on buffer layer and preparation method thereof |
-
2023
- 2023-04-26 CN CN202310461968.3A patent/CN116344587A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007158275A (en) * | 2005-12-08 | 2007-06-21 | Toyota Motor Corp | Insulated gate-type semiconductor device and manufacturing method therefor |
| JP2009194065A (en) * | 2008-02-13 | 2009-08-27 | Denso Corp | Silicon carbide semiconductor device and method of manufacturing the same |
| CN101981701A (en) * | 2008-03-26 | 2011-02-23 | 罗姆股份有限公司 | Semiconductor device, and method for manufacturing the same |
| JP2011101036A (en) * | 2011-01-07 | 2011-05-19 | Denso Corp | Silicon carbide semiconductor device and manufacturing method thereof |
| US20170110571A1 (en) * | 2015-10-20 | 2017-04-20 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| CN110366782A (en) * | 2017-03-06 | 2019-10-22 | 三菱电机株式会社 | The manufacturing method of manufacturing silicon carbide semiconductor device, power-converting device, the manufacturing method of manufacturing silicon carbide semiconductor device and power-converting device |
| CN110797389A (en) * | 2018-08-02 | 2020-02-14 | 意法半导体股份有限公司 | MOSFET device with shielded region and method of making the same |
| CN112186027A (en) * | 2020-08-28 | 2021-01-05 | 派恩杰半导体（杭州）有限公司 | Silicon carbide MOSFET with grid groove structure |
| CN114496784A (en) * | 2022-04-18 | 2022-05-13 | 深圳芯能半导体技术有限公司 | Bottom protection grounding groove type silicon carbide MOSFET and preparation method thereof |
| CN114496783A (en) * | 2022-04-18 | 2022-05-13 | 深圳芯能半导体技术有限公司 | Groove type silicon carbide MOSFET prepared based on buffer layer and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106876485B (en) | SiC double-groove MOSFET device integrated with Schottky diode and preparation method thereof | |
| JP5395309B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP5565461B2 (en) | Semiconductor device | |
| JP7243094B2 (en) | semiconductor equipment | |
| US10229969B2 (en) | Power semiconductor device | |
| CN111509035B (en) | Low-cost high-performance groove type power semiconductor device and preparation method thereof | |
| US9276075B2 (en) | Semiconductor device having vertical MOSFET structure that utilizes a trench-type gate electrode and method of producing the same | |
| US11411084B2 (en) | Semiconductor device, inverter circuit, drive device, vehicle, and elevator | |
| US8264036B2 (en) | Power semiconductor device with low on-state voltage and method of manufacturing the same | |
| JP2019003967A (en) | Semiconductor device and method of manufacturing the same | |
| US11355592B2 (en) | Semiconductor device, method of manufacturing semiconductor device, inverter circuit, drive device, vehicle, and elevator | |
| CN115377200A (en) | Semiconductor device and preparation method thereof | |
| JP2021044518A (en) | Semiconductor device, semiconductor device manufacturing method, inverter circuit, drive device, vehicle, and elevator | |
| TWI702722B (en) | Semiconductor device and method of manufacturing semiconductor device | |
| CN115831759A (en) | SGT MOSFET (Metal-oxide-semiconductor field Effect transistor) integrated with SBD (silicon substrate detection) structure and manufacturing method thereof | |
| US11374122B2 (en) | Semiconductor device, inverter circuit, drive device, vehicle, and elevating machine | |
| CN114530504B (en) | High threshold voltage SiC MOSFET device and manufacturing method thereof | |
| US11398556B2 (en) | Semiconductor device, inverter circuit, drive device, vehicle, and elevator | |
| US11201238B2 (en) | Semiconductor device, method of manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator | |
| US11069803B2 (en) | Semiconductor device, method of manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator | |
| CN115241283A (en) | Integrated planar-trench gate power MOSFET | |
| CN116344587A (en) | Groove type silicon carbide MOSFET device and preparation process thereof | |
| CN117238968B (en) | Trench gate silicon carbide MOSFET device and preparation method thereof | |
| US11961904B2 (en) | Semiconductor device including trench gate structure and buried shielding region and method of manufacturing | |
| EP4297100A1 (en) | Method for producing a semiconductor device and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |