JP2011101036A - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain high-pressure resistance by suppressing breakdown at a deep layer, in an SiC semiconductor device arranged with the deep layer so that the semiconductor device intersects with a trench gate structure. <P>SOLUTION: In an entire area of an outer edge of a cell region including an outer peripheral region, p-type deep layers 10 are formed, and a p-type resurf layer 15 which is formed in a boundary position between the cell region of a mesa structure 14 and its periphery has the same depth as the p-type deep layer 10. This causes an equipotential-line distribution to be nearly horizontal to a substrate plane at a junction between the p-type deep layer 10 and the p-type resurf layer 15, thus enabling an electric field to match a direction substantially vertical to the substrate plane, or the azimuth direction of a [0001] plane. As a result, when a drain voltage becomes high, the electric field is concentrated on a guard ring rather than a lower portion of the junction between the p-type deep layer 10 and the p-type resurf layer 15. Therefore, it becomes possible to suppress breakdown at the p-type deep layer 10 and obtain the high-pressure resistance. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a silicon carbide (hereinafter referred to as SiC) semiconductor device having a trench gate and a method for manufacturing the same.

  In recent years, SiC has attracted attention as a power device material that can provide high electric field breakdown strength. Since the SiC semiconductor device has a high electric field breakdown strength, a large current can be controlled. Therefore, it is expected to be utilized for controlling a hybrid car motor.

  In the SiC semiconductor device, it is effective to increase the channel density in order to flow a larger current. For this reason, MOSFETs having a trench gate structure are adopted and put into practical use in silicon transistors. This trench gate structure is naturally applicable to a SiC semiconductor device, but there is a big problem when applied to SiC. That is, since SiC has a breakdown electric field strength 10 times that of silicon, SiC semiconductor devices are used in a state where a voltage nearly 10 times that of silicon devices is applied. Therefore, there is a problem that an electric field 10 times stronger than that of the silicon device is applied to the gate insulating film formed in the trench that has entered SiC, and the gate insulating film is easily broken at the corner of the trench. When this was calculated by simulation, an electric field of 4.9 MV / cm was concentrated on the gate insulating film in the trench when 650 V was applied to the drain. In order to withstand actual use, it is necessary to make it 3 MV / cm or less, and considering long-term reliability, it is desirable to make it 2 MV / cm or less.

  As a solution to such a problem, there is an SiC semiconductor device disclosed in Patent Document 1. In this SiC semiconductor device, the electric field concentration at the bottom of the trench is reduced by designing the bottom of the trench gate to be thicker than the side surface. Specifically, a (1120) plane trench gate structure is fabricated using a 4H—SiC (000-1) c plane substrate. Thus, when a gate insulating film is formed by thermal oxidation in a trench in which a trench side surface is an a surface and a bottom surface is a c surface using a c surface substrate, the oxidation rate of the c surface is 5 times that of the a surface. The oxide film at the bottom of the trench can be five times as thick as the side surface. Thereby, it is possible to alleviate electric field concentration at the bottom of the trench.

JP 9-199724 A

  However, in the structure in which the gate insulating film is thick at the bottom of the trench as described above, for example, when the film thickness on the side surface of the trench is set to 40 nm and the film thickness at the bottom of the trench is designed to 200 nm, calculation is performed by simulation. In this case, it was confirmed that the electric field concentration of the gate insulating film in the trench could be reduced to 3.9 MV / cm. However, it was not yet sufficient, and it was found that further electric field relaxation was necessary.

  Therefore, the present inventors have previously proposed a method for the longitudinal direction of the trench gate as a SiC semiconductor device having a structure capable of further reducing the electric field and capable of preventing a variation in product characteristics and improving the yield. An application has been filed for a structure in which a p-type deep layer extends in the linear direction and in a direction parallel to the substrate plane (see Japanese Patent Application No. 2008-31704). In this earlier application, MOSFETs are proposed among SiC semiconductor devices, but the outer peripheral portion surrounding the outer edge portion of the cell region and the outer periphery of the cell region is not proposed. Therefore, a general peripheral region structure is applied to a SiC semiconductor device in which a p-type deep layer extends in a direction normal to the longitudinal direction of the trench gate and in a direction parallel to the substrate plane. Considered the case. FIG. 14 is a top surface layout of the SiC semiconductor device in that case, and FIGS. 15A and 15B are an X-X ′ sectional view and a Y-Y ′ sectional view in FIG. 14. Although FIG. 14 is not a cross-sectional view, hatching is partially shown for easy understanding of the drawing.

As shown in FIG. 14, a plurality of trenches J1 constituting the trench gate structure are arranged in stripes, and a p-type deep layer J2 is formed in a direction normal to the longitudinal direction of each trench J1 and parallel to the substrate plane. A plurality of stripes are extended. Then, as shown in FIGS. 14 and 15A and 15B, in the outer peripheral region, the recess is deeper than the p-type base region J3 and the p ⁺ -type contact layer J4 and reaches the n ⁻ -type drift layer J5. A mesa structure portion J6 configured as described above is formed. A p-type RESURF layer J7 is formed at the boundary between the cell region and the outer peripheral region so as to surround the outer periphery of the cell region so as to extend from the side wall surface to the bottom surface of the step portion of the mesa structure portion J6. A plurality of p-type guard ring layers J8 are formed so as to surround the p-type RESURF layer J7, and an n ⁺ -type layer J9 surrounding the p-type RESURF layer J7 and the p-type guard ring layer J8. By forming the equipotential ring electrode J10 electrically connected to the n ⁺ -type layer J9, an outer peripheral withstand voltage structure is configured.

  A breakdown voltage test by simulation was performed on the SiC semiconductor device having such a structure. FIG. 16 is a cross-sectional view showing the result of examining the impact ionization rate distribution during breakdown as a durability test, and FIG. 17A is an enlarged view of examining the equipotential line distribution in the region R1 in FIG. FIG. 17B is an enlarged view of the region R2 in FIG.

  As shown in FIG. 16, breakdown occurs in the p-type deep layer J2a in the outer edge of the cell region (near the boundary of the cell region with the outer peripheral region), and the impact ionization rate distribution increases in the vicinity thereof. Yes. That is, as shown in FIGS. 17A and 17B, in the portion where the p-type deep layer J2 is continuously formed, the depletion layer and the p-type base region J3 extending from the adjacent p-type deep layer J2 respectively. Since the withstand voltage is given by the depletion layer extending from, an equipotential line can be prevented from entering the p-type base region J3 side. However, in the p-type deep layer J2a on the outer edge side of the cell region, since the p-type deep layer J2 does not exist on the outer peripheral side, the equipotential line enters to a higher position on the p-type base region J3 side, and the breakdown voltage is reduced. It cannot be held.

  In particular, devices are often created using a SiC substrate having a Si surface as the main surface because it is easy to create a large-diameter SiC wafer, but because SiC has a plane orientation dependency on the breakdown electric field strength, When the Si surface is used, a desired breakdown voltage cannot be provided. That is, in the case of a SiC substrate having a Si surface, the direction from the back surface to the front surface of the SiC substrate, that is, the direction perpendicular to the substrate is the [0001] plane orientation. For this reason, if the electric field is applied such that the direction of the equipotential lines coincides with the substrate plane direction, a high breakdown electric field strength can be expected. However, as shown in FIG. 17B, in the p-type deep layer J2a on the outer edge side of the cell region, the direction of the equipotential lines is greatly inclined with respect to the substrate plane direction. Therefore, as indicated by a vector in the figure, an electric field is applied in a state inclined by about 30 ° with respect to the vertical direction of the substrate, and the breakdown electric field strength is reduced. Specifically, the direction of the equipotential lines is horizontal in the substrate plane direction, and the breakdown electric field strength is reduced by about 20% compared to the case where the direction of the [0001] plane, which is the substrate vertical direction, coincides with the electric field direction.

  In view of the above points, an object of the present invention is to achieve a high breakdown voltage by suppressing breakdown in a deep layer in an SiC semiconductor device provided with a deep layer so as to intersect the trench gate structure. And

  In order to achieve the above object, according to the invention described in claim 1 or 2, it is disposed below the base region (3) and deeper than the trench (6), and the longitudinal direction of the trench (6), And it has the 2nd conductivity type deep layer (10) extended in the stripe form in the direction which cross | intersects with respect to a parallel direction to a substrate plane, and a deep layer (10) is in the outer edge part of a cell area | region. The trench (6) arranged in a stripe shape and the deep layer (10) are extended toward the outer peripheral region so as to surround a portion arranged in the stripe shape. The mesa structure portion (14) formed by a recess deeper than the base region and the bottom surface of the recess forming the mesa structure portion (14) are formed to have a predetermined depth and surround the cell region. Like A second conductivity type RESURF layer formed (15), having a RESURF layer (15) is characterized in that the depth of the bottom deep layer (10) is the same.

  In this way, by extending the deep layer (10) toward the outer peripheral region at the outer edge of the cell region, breakdown is caused by at least the deep layer (10) formed at the outer edge of the cell region. Since the place is moved to the outer peripheral region, it is possible to increase the breakdown voltage.

  Further, if the RESURF layer (15) is formed in the mesa structure (14), the equipotential line distribution is substantially horizontal to the substrate plane between the deep layer (10) and the RESURF layer (15), and the electric field Can be applied substantially in the direction perpendicular to the substrate. As a result, the electric field concentration portion when the drain voltage becomes a high voltage can be arranged not on the lower portion between the deep layer (10) and the RESURF layer (15) but on the outer peripheral side. Therefore, in the SiC semiconductor device in which the deep layer (10) is provided so as to intersect the trench gate structure, it is possible to increase the breakdown voltage by suppressing the breakdown in the deep layer (10). Become.

  Moreover, by making the depth of the deep layer (10) and the RESURF layer (15) the same, the junction between the deep layer (10) and the drift layer (2), and the RESURF layer (15) and the drift layer ( The depletion layer spreading at the junction with 2) is easily connected. Similarly, the equipotential lines in the depletion layer hardly make a step at the junction between the deep layer (10) and the RESURF layer (15), and are almost horizontal to the substrate plane. For this reason, it is possible to prevent the portion where the electric field concentration occurs from being a junction between the deep layer (10) and the RESURF layer (15).

  For example, as described in claim 3, the deep layer (10) may be formed over the entire outer edge of the cell region and connected to the RESURF layer (15) formed in the outer peripheral region.

  Further, as described in claim 4, the deep layer (10) can be formed at a predetermined distance from the RESURF layer (15) formed in the outer peripheral region at the outer edge of the cell region. In this case, if the distance between the deep layer (10) and the RESURF layer (15) is narrower than the distance between the deep layers (10) arranged in stripes. The amount of equipotential lines entering the base region (3) side is smaller between the deep layer (10) and the RESURF layer (15) than between the adjacent deep layers (10) arranged in a stripe. Become. Therefore, it is possible to increase the breakdown voltage as described above.

  For example, as described in claim 5, the deep layer (10) can be formed over the entire outer edge of the cell region. Further, as described in claim 6, the deep layer (10) can be formed at the outer edge of the cell region so as to be separated from the outer peripheral region by a predetermined distance. In this case, the distance from the deep layer (10) to the outer peripheral region may be made narrower than the distance between the deep layers (10) arranged in stripes. Furthermore, as described in claim 7, in the outer edge portion of the cell region, the deep layer (10) includes a gap portion (10a) in which the deep layer (10) is not partially formed, and the gate of the MOSFET The gap (10a) may be filled with a depletion layer extending from the deep layer (10) to the gap (10a) when the voltage is not applied to the electrode (9).

  The SiC semiconductor device as described above is manufactured by, for example, a manufacturing method shown below. For example, as described in claim 8, the first conductivity type silicon carbide having a lower impurity concentration than the substrate (1) on the first or second conductivity type substrate (1) made of silicon carbide. Forming a drift layer (2) comprising: a cell region, a surface layer portion of the drift layer (2) arranged in a stripe extending in one direction, and an outer edge portion of the cell region; A step of forming a second conductivity type deep layer (10) extending toward an outer peripheral region surrounding the periphery of the cell region, and a deep layer (10 ) And the drift layer (2), a step of forming the base region (3) made of silicon carbide of the second conductivity type, and the drift region (2) is exposed by removing the base region (3) in the outer peripheral region. Mesa structure part (14 Forming a second conductive type resurf layer (15) from the side wall surface to the bottom surface of the recess in the mesa structure (14), and the base region (3) in the base region (3) Forming a source region (4) made of silicon carbide of the first conductivity type higher in concentration than the drift layer (2) by ion-implanting a first conductivity type impurity into the surface layer portion of A direction in which the deep layer (10) extends so as to penetrate the base region (3) from the surface of the region (4) to the drift layer (2) and become shallower than the deep layer (10); A step of forming a trench (6) whose longitudinal direction is an intersecting direction, a step of forming a gate insulating film (8) in the trench (6), and a gate insulating film (8) in the trench (6). Process to form gate electrode (9) on top And forming a source electrode (11) electrically connected to the source region (4) and the base region (3), forming a drain electrode (13) on the back side of the substrate (1), The SiC semiconductor device according to claim 1 or 2 can be manufactured by a manufacturing method including:

  Further, as in the invention according to claim 9, in the surface layer portion of the drift layer (2), in the cell region, the portion arranged in a stripe extending in one direction, and the outer edge portion of the cell region A step of forming a second conductivity type deep layer (10) extending toward an outer peripheral region surrounding the periphery of the cell region, and a portion surrounding the portion arranged in a stripe shape, The step of forming the second conductivity type RESURF layer (15) surrounding the periphery of the cell region so as to be connected to the deep layer (10) can be performed simultaneously.

  Thus, if the RESURF layer (15) is formed simultaneously with the deep layer (10), the manufacturing process of the RESURF layer (15) and the deep layer (10) can be simplified. Further, the RESURF layer (15) and the deep layer (10) are superposed to increase the concentration, and the equipotential lines can be prevented from being distorted and the electric field concentration.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

1 is a front layout view of a SiC semiconductor device including a MOSFET having an inverted trench gate structure according to a first embodiment of the present invention. FIG. 2 is a perspective sectional view of one cell of the MOSFET having an inverted trench gate structure shown in FIG. 1. It is AA sectional drawing of FIG. It is BB sectional drawing of FIG. It is CC sectional drawing of FIG. It is DD sectional drawing of FIG. (A) is E-E 'sectional drawing of FIG. 1, (b) is F-F' sectional drawing of FIG. (A)-(e) is sectional drawing which showed the result of investigating the equipotential line distribution in the junction part of the p-type deep layer 10 and the p-type RESURF layer 15, and the impact ionization rate distribution at the time of breakdown as a durability test. is there. FIG. 6 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device including the trench gate type MOSFET shown in FIG. 1. It is a front layout figure of the SiC semiconductor device provided with MOSFET of the inversion type trench gate structure concerning 2nd Embodiment of this invention. (A) is G-G 'sectional drawing of FIG. 7, (b) is H-H' sectional drawing of FIG. It is a front layout figure of the SiC semiconductor device provided with MOSFET of the inversion type trench gate structure concerning 3rd Embodiment of this invention. (A) is I-I 'sectional drawing of FIG. 9, (b) is J-J' sectional drawing of FIG. It is sectional drawing of the SiC semiconductor device provided with MOSFET of the inversion type trench gate structure concerning 4th Embodiment of this invention. FIG. 12 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device including the trench gate type MOSFET shown in FIG. 11. It is a perspective sectional view for 1 cell of MOSFET of accumulation type trench gate structure explained in other embodiments. It is a top surface layout figure at the time of applying the structure of a general perimeter field to the SiC semiconductor device which the present inventors applied earlier. 14A is a cross-sectional view taken along the line X-X ′ of FIG. 14, and FIG. 14B is a cross-sectional view taken along the line Y-Y ′ of FIG. 14. It is sectional drawing which showed the result of having investigated the impact ionization rate distribution at the time of a breakdown as an endurance test. (A) is the enlarged view which investigated equipotential line distribution of area | region R1 in FIG. 16, (b) is the enlarged view of area | region R2 in (a).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
FIG. 1 is a front layout view of an SiC semiconductor device including a MOSFET having an inverted trench gate structure according to the present embodiment. Although FIG. 1 is not a cross-sectional view, hatching is partially shown for easy understanding of the drawing.

  FIG. 2 is a perspective sectional view of one MOSFET extracted in a region Ra surrounded by a broken line in FIG. 3A to 3D are cross-sectional views of the MOSFET of FIG. 2, and FIG. 3-A is a cross-sectional view taken along line AA in FIG. 2 parallel to the xz plane. 3-b is a cross section when cut in parallel to the xz plane along the line BB in FIG. 2, and FIG. 3-c is a cross section when cut along the line CC in FIG. 2 in parallel with the yz plane. 3D is a cross section when cut in parallel with the yz plane along the line DD in FIG.

  As shown in FIG. 1, the SiC semiconductor device includes a cell region in which a MOSFET is formed and an outer peripheral region in which an outer peripheral withstand voltage structure is formed so as to surround the cell region.

As shown in FIG. 2 and FIGS. 3A to 3D, the n-type impurity concentration of phosphorus or the like is, for example, 1.0 × 10 ¹⁹ / cm ³ and the thickness is about 300 μm, and the main surface is an Si plane (that is, An n ⁺ type substrate 1 made of SiC with the substrate vertical direction being the [0001] plane orientation) is used as a semiconductor substrate. An n ⁻ type drift layer 2 made of SiC having an n type impurity concentration such as phosphorus of 3.0 to 7.0 × 10 ¹⁵ / cm ³ and a thickness of about 10 to ¹⁵ μm is formed on the surface of the n ⁺ type substrate 1. Has been. The impurity concentration of the n ⁻ type drift layer 2 may be constant in the depth direction, but the concentration distribution is inclined, and the n ⁺ type substrate 1 side of the n ⁻ type drift layer 2 is n ⁺ type. It is preferable that the concentration be higher than that on the side away from the substrate 1. For example, the impurity concentration in the portion of about 3 to 5 μm from the surface of the n ⁺ -type substrate 1 in the n ⁻ -type drift layer 2 is preferably higher than that in other portions by about 2.0 × 10 ¹⁵ / cm ³ . In this way, since the internal resistance of the n ⁻ type drift layer 2 can be reduced, the on-resistance can be reduced.

A p-type base region 3 is formed in the surface layer portion of the n ⁻ -type drift layer 2, and an n ⁺ -type source region 4 and a p ⁺ -type contact layer 5 are formed in an upper layer portion of the p-type base region 3. ing.

The p-type base region 3 has a p-type impurity concentration such as boron or aluminum having a thickness of about 5.0 × 10 ^{15 to} 5.0 × 10 ¹⁶ / cm ³ and about 2.0 μm. The n ⁺ -type source region 4 is configured such that the n-type impurity concentration (surface concentration) such as phosphorus in the surface layer portion is, for example, 1.0 × 10 ²¹ / cm ³ and the thickness is about 0.3 μm. The p ⁺ -type contact layer 5 has a p-type impurity concentration (surface concentration) such as boron or aluminum in the surface layer portion of, for example, 1.0 × 10 ²¹ / cm ³ and a thickness of about 0.3 μm.

The n ⁺ -type source region 4 is disposed on both sides of a trench gate structure described later, and the p ⁺ -type contact layer 5 is provided on the opposite side of the trench gate structure with the n ⁺ -type source region 4 interposed therebetween.

Further, it penetrates the p-type base region 3 and the n ⁺ -type source region 4 and reaches the n ⁻ -type drift layer 2. For example, the width is 1.4 to 2.0 μm and the depth is 2.0 μm or more (for example, 2.4 μm). ) To form the trench 6. The p-type base region 3 and the n ⁺ -type source region 4 are arranged so as to be in contact with the side surface of the trench 6.

  Further, the surface of the trench 6 is covered with a gate oxide film 8, and the inside of the trench 6 is filled with the gate electrode 9 made of doped Poly-Si formed on the surface of the gate oxide film 8. Yes. The gate oxide film 8 is formed by thermally oxidizing the inner wall surface of the trench 6, and the thickness of the gate oxide film 8 is about 100 nm on both the side surface side and the bottom side of the trench 6, for example.

In this way, a trench gate structure is configured. This trench gate structure extends with the y direction in FIG. 2 as the longitudinal direction. A plurality of trench gate structures are arranged in parallel in the x direction in FIG. Further, the n ⁺ type source region 4 and the p ⁺ type contact layer 5 are also extended along the longitudinal direction of the trench gate structure.

Further, in the n ⁻ type drift layer 2 below the p-type base region 3, the normal direction to the portion of the side surface of the trench 6 in the trench gate structure where the channel region is formed (the x direction in FIG. 2). That is, the p-type deep layer 10 is provided so as to extend in a direction perpendicular to the longitudinal direction of the trench 6 and in a direction parallel to the substrate plane. The p-type deep layer 10 is deeper than the bottom of the trench 6, and the depth from the surface of the n ⁻ -type drift layer 2 is, for example, about 2.6 to 3.0 μm (from the bottom of the p-type base region 3). The depth is set to 0.6 to 1.0 μm, for example. Moreover, the width | variety (y direction dimension in FIG. 2) of the p-type deep layer 10 shall be 0.6-1.0 micrometer. The concentration of p-type impurities such as boron or aluminum in the p-type deep layer 10 is 1.0 × 10 ¹⁷ / cm ^{3 to} 1.0 × 10 ¹⁹ / cm ³ , for example, 5.0 × 10 ¹⁷ / cm ^3. ing. The p-type deep layers 10 are arranged in stripes by arranging a plurality of p-type deep layers 10 in parallel along the longitudinal direction of the trench gate structure in the inner peripheral portion of the cell region. Is, for example, 1.5 to 3 μm. The p-type deep layer 10 is formed all the way to the outer peripheral region of the trench 6 at the outer edge of the cell region.

Incidentally, the outer edge, i.e. have p-type base region 3 and the p ⁺ -type contact layer 5 is formed above the p-type deep layer 10 to the portion not active, the p ⁺ -type contact even at portions not its active cell area The source electrode 11 is electrically connected to the layer 5.

A source electrode 11 and a gate wiring (not shown) are formed on the surface of the n ⁺ type source region 4 and the p ⁺ type contact layer 5 and the surface of the gate electrode 9. The source electrode 11 and the gate wiring are composed of a plurality of metals (for example, Ni / Al, etc.), and at least n-type SiC (specifically, the n ⁺ -type source region 4 and the gate electrode 9 in the case of n doping) The portion in contact with n-type SiC is made of a metal capable of ohmic contact with n-type SiC, and the portion in contact with at least p-type SiC (specifically, p ⁺ -type contact layer 5 or gate electrode 9 in the case of p-doping) is p-type. It is made of a metal capable of ohmic contact with SiC. The source electrode 11 and the gate wiring are electrically insulated by being formed on the interlayer insulating film 12, and the source electrode 11 is connected to the n ⁺ -type source region through the contact hole formed in the interlayer insulating film 12. 4 and the p ⁺ -type contact layer 5 are in electrical contact, and the gate wiring is in electrical contact with the gate electrode 9.

Then, on the back side of the n ⁺ -type substrate 1 n ⁺ -type substrate 1 and electrically connected to the drain electrode 13 are formed. With such a structure, an n-channel storage type MOSFET with a trench gate structure is formed.

  On the other hand, the outer edge and the outer peripheral region surrounding the MOSFET in the cell region are configured as follows. 4A is a cross-sectional view taken along line EE in FIG. 1, and FIG. 4B is a cross-sectional view taken along line FF in FIG.

As shown in FIGS. 4A and 4B, the outer peripheral region is deeper than the p-type base region 3 and the p ⁺ -type contact layer 5 formed in the cell region, and is formed in the n ⁻ -type drift layer 2. A mesa structure portion 14 is formed which is constituted by a recessed portion having a depth of about 2.1 to 2.5 μm. A p-type RESURF layer 15 surrounding the outer periphery of the cell region is formed at the boundary between the cell region and the outer peripheral region so as to extend from the side wall surface to the bottom surface of the step portion of the mesa structure portion 14. A plurality of p-type guard ring layers 16 are formed so as to surround 15. Then, the n ⁺ -type layer 17 and the equipotential ring electrode 18 electrically connected to the n ⁺ -type layer 17 are formed so as to surround the periphery of the p-type RESURF layer 15 and the p-type guard ring layer 16. A breakdown voltage structure is configured.

The p-type RESURF layer 15 is formed so as to protrude, for example, about 20 μm from the boundary between the cell region and the outer peripheral region toward the outside of the cell region. The portion of the p-type RESURF layer 15 formed on the side wall surface of the step portion of the mesa structure portion 14 has a thickness in the horizontal direction of the substrate of 0.7 μm and a p-type impurity concentration of about 1 × 10 ¹⁷ / cm ^3. The portion formed on the bottom surface of the concave portion constituting the mesa structure portion 14 has a depth from the bottom surface of the concave portion of about 0.7 μm and about 4 × 10 ¹⁷ / cm ³ . As described above, the p-type deep layer 10 has a depth from the surface of the n ⁻ -type drift layer 2 of, for example, about 2.6 to 3.0 μm. The depths of the p-type deep layer 10 and the p-type RESURF layer 15 from the bottom surface are substantially the same.

  Further, as described above, the p-type deep layer 10 is formed all over the outer edge of the cell region up to the outer peripheral region. For this reason, the trench gate structure and the portion arranged in a stripe shape in the p-type deep layer 10 are surrounded by the portion formed in the outer edge portion of the cell region in the p-type deep layer 10, and The p-type deep layer 10 has a structure in which the outer edge of the p-type deep layer 10 is connected to the p-type RESURF layer 15 at the boundary between the cell region and the outer peripheral region.

The p-type guard ring layer 16 that is located on the innermost peripheral side is formed, for example, by 0.5 μm away from the p-type RESURF layer 15, has a radial width of 2 μm, and an interval of 1 μm. Is formed. Thereby, the guard ring part is comprised. The depth of each p-type guard ring layer 16 is, for example, 0.7 μm, and the p-type impurity concentration is, for example, about 1 × 10 ¹⁸ / cm ³ . With such a structure, the SiC semiconductor device according to the present embodiment is configured.

  Such an accumulation type MOSFET having a trench gate structure operates as follows.

First, in the state before the gate voltage is applied to the gate electrode 9, the channel region is not formed in the portion of the p-type base region 3 located on the side surface of the trench 6. For this reason, even if a positive voltage is applied to the drain electrode 13, electrons cannot move due to the PNP junction structure formed by the n ⁻ type drift layer 2, the p type base region 3, and the n ⁺ type source region 4. No current flows between the drain electrode 13.

Next, when on (gate voltage = 20 V, drain voltage = 1 V, source voltage = 0 V), 20 V is applied as the gate voltage to the gate electrode 9, so that the p-type base region 3 is inverted on the side surface of the trench 6. Thus, a channel region is formed. Therefore, electrons injected from the source electrode 11 reach the n ⁻ type drift layer 2 after passing through the channel region in the p type base region 3 from the n ⁺ type source region 4. As a result, a current can flow between the source electrode 11 and the drain electrode 13.

When off (gate voltage = 0 V, drain voltage = 650 V, source voltage = 0 V), since a reverse bias is applied even if a voltage is applied to the drain electrode 13, the p-type deep layer 10 and the n ⁻ -type drift layer 2 The depletion layer spreads at the junction between the p-type RESURF layer 15 and the n ⁻ -type drift layer 2. At this time, in this embodiment, the impurity concentration of the p-type deep layer 10 is, for example, 5.0 × 10 ¹⁷ / cm ^3, and the impurity concentration of the p-type RESURF layer 15 is, for example, 4.0 × 10 ¹⁷ / cm ³ . Therefore, the impurity concentration of the n ⁻ type drift layer 2 is about 100 times as high as that of the n ⁻ type drift layer 2. For this reason, the depletion layer almost extends to the n ⁻ type drift layer 2 side.

Further, since the depths of the p-type deep layer 10 and the p-type resurf layer 15 are substantially the same, the junction between the p-type deep layer 10 and the n ⁻ -type drift layer 2, and the p-type resurf layer 15 A depletion layer extending at the junction with the n ⁻ -type drift layer 2 is easily connected and extends to the p-type guard ring layer 16. Similarly, the equipotential lines in the depletion layer hardly make a step at the junction between the p-type deep layer 10 and the p-type RESURF layer 15 and are almost horizontal to the substrate plane. For this reason, the portion where the electric field concentration occurs is not the junction between the p-type deep layer 10 and the p-type RESURF layer 15 but in the vicinity of the p-type guard ring layer 16.

  5 (a) to 5 (e) are cross-sectional views showing the results of examining the equipotential line distribution at the junction between the p-type deep layer 10 and the p-type RESURF layer 15 and the impact ionization rate distribution during breakdown as a durability test. FIG. Specifically, FIG. 5A is a cross-sectional view of the vicinity of the junction between the p-type deep layer 10 and the p-type RESURF layer 15 of the SiC semiconductor device of the present embodiment that is the subject of the experiment, and FIG. (D) shows equipotential distribution in the cross section shown in FIG. 5 (a) when the drain voltage (Vd) is 200V, 400V, 1200V, and FIG. 5 (e) shows the impact ionization rate distribution during breakdown. FIG.

  As shown in FIGS. 5B to 5D, the equipotential line distribution is substantially horizontal to the substrate plane at the junction between the p-type deep layer 10 and the p-type RESURF layer 15. Since the electric field is applied in the vertical direction of the equipotential lines, the electric field is applied substantially in the vertical direction of the substrate, that is, in the direction of the [0001] plane, below the junction portion of the p-type deep layer 10 and the p-type RESURF layer 15. In addition, since the equipotential lines terminate in a sufficiently broad manner in the p-type guard ring layer 16, the electric field concentration when the drain voltage becomes high while the electric field is sufficiently relaxed by the guard ring portion. The portion can be a guard ring portion, not a lower portion of the junction portion of the p-type deep layer 10 and the p-type RESURF layer 15.

  As described above, the electric field can be applied to the direction of the [0001] plane where the breakdown electric field intensity is highest at the lower part of the junction between the p-type deep layer 10 and the p-type RESURF layer 15. As a result, as shown in FIG. 5E, the place where breakdown occurs is not the outermost p-type deep layer 10 but the guard ring portion. As a result of simulation, the breakdown voltage was 1100 V in the case of the conventional structure, but the breakdown voltage was improved to 1450 V by using the structure of this embodiment. Therefore, in the SiC semiconductor device in which the p-type deep layer 10 is provided so as to intersect the trench gate structure as in the present embodiment, the breakdown voltage is increased by suppressing the breakdown in the p-type deep layer 10. Can be achieved.

  Next, a manufacturing method of the SiC semiconductor device including the MOSFET having the inverted trench gate structure according to the present embodiment will be described. FIG. 6 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device of the present embodiment. The cross section shown in this figure corresponds to the F-F 'cross section of FIG. Hereinafter, a description will be given with reference to this figure.

[Step shown in FIG. 6A]
First, after preparing an n ⁺ type substrate 1 made of SiC whose main surface is an Si plane (that is, the orientation of the substrate perpendicular direction is the [0001] plane), a drain electrode 13 is formed on the back side of the n ⁺ type substrate 1. . Then, an n ⁻ type drift layer 2 made of SiC is epitaxially grown on the surface of the n ⁺ type substrate 1.

[Step shown in FIG. 6B]
After a mask (not shown) made of LTO or the like is formed on the surface of n ⁻ type drift layer 2, the mask is formed in a region where p type deep layer 10 and p type guard ring layer 16 are to be formed through a photolithography process. Open. Then, the p-type deep layer 10 and the p-type guard ring layer 16 are formed by ion implantation and activation of a p-type impurity (for example, boron or aluminum) from above the mask. Thereafter, the mask is removed.

[Step shown in FIG. 6 (c)]
A p-type base region 3 is formed by epitaxially growing a p-type impurity layer on the surface of the n ⁻ -type drift layer 2.

[Step shown in FIG. 6 (d)]
After disposing an etching mask (not shown) on the p-type base region 3, the etching mask is opened in the outer peripheral region. Then, by etching the outer peripheral region using an etching mask, forming a recess deeper than the p-type base region 3 and exposing the p-type guard ring layer 16 by reaching the n ⁻ -type drift layer 2, The mesa structure portion 14 is formed. Then, after removing the etching mask, a mask (not shown) made of LTO or the like is formed again, and the mask is opened in a region where the p-type RESURF layer 15 is to be formed. A p-type RESURF layer 15 is formed by ion implantation and activation of p-type impurities from above the mask. Thereafter, the mask is removed.

[Step shown in FIG. 6 (e)]
After forming a mask (not shown) made of, for example, LTO on the p-type base region 3 or the like, the mask is opened on the formation region of the n ⁺ -type source region 4 through a photolithography process. Let Thereafter, n-type impurities (for example, nitrogen) are ion-implanted. Further, after removing the previously used mask, a mask (not shown) is formed again, and the mask is opened on a region where the p ⁺ -type contact layer 5 is to be formed through a photolithography process. Thereafter, a p-type impurity (for example, nitrogen) is ion-implanted. Then, by activating the implanted ions, the n ⁺ type source region 4 and the p ⁺ type contact layer 5 are formed.

Further, after forming an etching mask (not shown) on the p-type base region 3, the n ⁺ -type source region 4 and the p ⁺ -type contact layer 5, the etching mask is opened in the region where the trench 6 is to be formed. And after performing anisotropic etching using an etching mask, the trench 6 is formed by performing an isotropic etching and a sacrificial oxidation process as needed. Thereafter, the etching mask is removed.

  Subsequently, a gate oxide film 8 is formed on the entire surface of the substrate including the inside of the trench 6 by performing a gate oxide film forming step. Specifically, the gate oxide film 8 is formed by gate oxidation (thermal oxidation) by a pyrogenic method using a wet atmosphere. Further, after a polysilicon layer doped with n-type impurities is formed on the surface of the gate oxide film 8 at a temperature of about 440 nm, for example, at a temperature of 600 ° C., an etch back process or the like is performed to thereby form the gate oxide film 8 in the trench 6. And the gate electrode 9 is left.

The subsequent steps are the same as in the prior art and are not shown. However, after the interlayer insulating film 12 is formed, the interlayer insulating film is patterned to contact the n ⁺ type source region 4 and the p ⁺ type contact layer 5. While forming a hole, the contact hole connected with the gate electrode 9 is formed in another cross section. Subsequently, after depositing an electrode material so as to fill the contact hole, the source electrode 11 and the gate wiring are formed by patterning the electrode material. Thereby, the SiC semiconductor device shown in FIG. 1 is completed.

  As described above, the SiC semiconductor device according to the present embodiment has a structure in which the p-type deep layer 10 is formed all the way to the outer peripheral region in the outer edge portion of the cell region. For this reason, at the junction between the p-type deep layer 10 and the p-type RESURF layer 15, the equipotential line distribution is substantially horizontal to the substrate plane, and the electric field can be applied to the substrate perpendicular direction, that is, the orientation of the [0001] plane. . Thereby, the electric field concentration portion when the drain voltage becomes a high voltage can be a guard ring portion instead of a lower portion of the junction portion between the p-type deep layer 10 and the p-type RESURF layer 15.

  For this reason, the place to break down is not the outermost p-type deep layer 10 but the guard ring portion. Therefore, in the SiC semiconductor device in which the p-type deep layer 10 is provided so as to intersect the trench gate structure, it is possible to increase the breakdown voltage by suppressing the breakdown at the p-type deep layer 10. Become.

(Second Embodiment)
A second embodiment of the present invention will be described. The SiC semiconductor device according to the present embodiment is obtained by changing the structure of the p-type deep layer 10 with respect to the first embodiment, and the basic structure is the same as that of the first embodiment, so that it is different from the first embodiment. Only the parts that are present will be described.

  FIG. 7 is a front layout view of the SiC semiconductor device including the MOSFET having the inverted trench gate structure according to the present embodiment. Although FIG. 7 is not a cross-sectional view, hatching is partially shown for easy understanding of the drawing. 8A is a cross-sectional view taken along the line G-G ′ in FIG. 7, and FIG. 8B is a cross-sectional view taken along the line H-H ′ in FIG. 7.

  As shown in FIGS. 7 and 8, in the present embodiment, the p-type deep layer 10 is not formed all the way to the outer peripheral region at the outer edge of the cell region, but is predetermined from the p-type RESURF layer 15. The structure is formed up to a position far away. The distance from the p-type deep layer 10 to the p-type RESURF layer 15 is narrower than the interval between the portions of the p-type deep layer 10 arranged in a stripe shape in the cell region.

  In the case of such a structure, since the distance from the p-type deep layer 10 to the p-type RESURF layer 15 is narrower than the interval between the portions of the p-type deep layer 10 arranged in stripes, A depletion layer extending between the p-type deep layer 10 and the p-type RESURF layer 15 is connected. Further, the amount of equipotential lines entering the p-type base region 3 side between the p-type deep layer 10 and the p-type RESURF layer 15 rather than between the adjacent p-type deep layers 10 arranged in a stripe shape. Get smaller.

  Therefore, as in the first embodiment, the equipotential line distribution is substantially horizontal to the substrate plane between the p-type deep layer 10 and the p-type RESURF layer 15, and the electric field is substantially in the direction perpendicular to the substrate, that is, the [0001] plane. It can be placed in the direction of Therefore, the same effect as that of the first embodiment can be obtained.

  Furthermore, in the case of the SiC semiconductor device of the present embodiment, since the gap is formed between the p-type deep layer 10 and the p-type resurf layer 15, the p-type deep layer 10 and the p-type resurf layer 15 are formed to overlap each other. It is also possible to suppress this. That is, since the formation process of the p-type deep layer 10 and the formation process of the p-type RESURF layer 15 are separate processes, there is a possibility that these formation positions are shifted due to mask displacement. However, if a gap is provided between the p-type deep layer 10 and the p-type RESURF layer 15, it is possible to prevent them from overlapping due to mask displacement. When the p-type deep layer 10 and the p-type RESURF layer 15 overlap each other due to mask misalignment, the equipotential lines may be distorted and the electric field may be concentrated. If a gap is provided in the gap, the occurrence of electric field concentration can be suppressed.

(Third embodiment)
A third embodiment of the present invention will be described. The SiC semiconductor device of the present embodiment is also a modification of the structure of the p-type deep layer 10 with respect to the first embodiment, and the basic structure is the same as that of the first embodiment, so that it differs from the first embodiment. Only the parts that are present will be described.

  FIG. 9 is a front layout view of the SiC semiconductor device including the MOSFET having the inverted trench gate structure according to the present embodiment. Although FIG. 9 is not a cross-sectional view, hatching is partially shown for easy understanding of the drawing. 10A is a cross-sectional view taken along the line I-I ′ of FIG. 9, and FIG. 10B is a cross-sectional view taken along the line J-J ′ of FIG. 9.

  As shown in FIGS. 9 and 10, this embodiment also reaches the p-type RESURF layer 15 instead of forming the p-type deep layer 10 all the way to the outer peripheral region at the outer edge of the cell region. Although it is formed up to the position, a gap portion 10a in which the p-type deep layer 10 is not formed is formed at various locations on the outer edge portion. The dimension of the gap portion 10a is narrower than the interval between the portions of the p-type deep layer 10 arranged in a stripe shape in the cell region. In FIG. 9, since the gap 10a has a square shape, the length of each side thereof is narrower than the interval between the portions arranged in a stripe shape in the p-type deep layer 10, but other shapes, for example, In the case where the gap portion 10a is circular, the diameter may be narrower than the interval between the portions of the p-type deep layer 10 arranged in stripes.

  Thus, the gap 10a may be formed in the p-type deep layer 10 at the outer edge of the cell region. Even if such a gap portion 10a is formed, the size of the gap portion 10a is narrower than the interval between the portions of the p-type deep layer 10 arranged in a stripe shape, so that the p around the gap portion 10a. If the depletion layer extends from the mold deep layer 10, the gap 10 a is also filled up by the depletion layer. For this reason, even if it is set as such a structure, it becomes possible to acquire the effect similar to 1st Embodiment.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. The SiC semiconductor device of this embodiment is obtained by changing the formation process of the p-type deep layer 10 and the p-type RESURF layer 15 with respect to the first embodiment, and the basic structure is the same as that of the first embodiment. Only the parts different from the first embodiment will be described.

  The SiC semiconductor device of this embodiment has the same front layout as that of the first embodiment, that is, the same as that of FIG. However, in this embodiment, since the formation process of the p-type deep layer 10 and the p-type resurf layer 15 is changed with respect to the first embodiment, the structure of the p-type deep layer 10 and the p-type resurf layer 15 is the first. Slightly different from one embodiment. The difference will be described with reference to FIG.

  FIGS. 11A and 11B are cross-sectional views of the SiC semiconductor device of the present embodiment, corresponding to the E-E ′ cross section and the F-F ′ cross section of FIG. 1, respectively.

  As shown in this figure, in this embodiment, the p-type deep layer 10 and the p-type RESURF layer 15 are connected and formed with the same depth and the same impurity concentration. In this embodiment, the p-type RESURF layer 15 is not formed on the side wall surface of the step portion of the mesa structure portion 14, but the p-type base region 3 is formed between the cell region, the outer peripheral region, and the outer edge portion of the cell region. It is in the state formed to the boundary part.

The SiC semiconductor device of this embodiment having such a structure is manufactured as follows. FIG. 12 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device of this embodiment. As shown in this figure, in the process shown in FIG. 12A, the same process as in FIG. 6A is performed, and in the process shown in FIG. 12B, the cross section is the same as that in FIG. 6B. Perform the process. However, at this time, in addition to the p-type deep layer 10 and the p-type guard ring layer 16, the p-type RESURF layer 15 is also formed to be connected to the p-type deep layer 10 at the surface layer portion of the n ⁻ -type drift layer 2. . Then, after performing the same process as in FIG. 6C in the process shown in FIG. 12C, the mesa structure portion 14 in the process shown in FIG. 6D is formed in the process shown in FIG. Thereafter, the SiC semiconductor device of the present embodiment is completed by performing the same process as in FIG. 6E in the process of FIG. 12E without performing the process of forming the p-type RESURF layer 15.

  Thus, the p-type RESURF layer 15 can be formed simultaneously with the p-type deep layer 10. Even if it does in this way, while being able to acquire the effect similar to 1st Embodiment, it becomes possible to aim at simplification of the manufacturing process of the p-type RESURF layer 15 and the p-type deep layer 10. FIG. Further, the p-type RESURF layer 15 and the p-type deep layer 10 can be prevented from being concentrated, and the equipotential lines can be prevented from being distorted and the electric field concentrated. Therefore, the same effect as the second embodiment can be obtained.

(Other embodiments)
(1) In the first embodiment, an n-channel type MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the conductivity type of each component is reversed. The present invention can also be applied to p-channel type MOSFETs. In the above description, a MOSFET having a trench gate structure has been described as an example. However, the present invention can also be applied to an IGBT having a similar trench gate structure. The IGBT only changes the conductivity type of the substrate 1 from the n-type to the p-type with respect to the first embodiment, and the other structure and manufacturing method are the same as those of the first embodiment.

  (2) The structure shown in the first embodiment is merely an example, and settings can be changed as appropriate. For example, the gate oxide film 8 formed by thermal oxidation has been described as an example of the gate insulating film, but may include an oxide film or nitride film that is not thermally oxidized. The drain electrode 13 may be formed after the source electrode 11 is formed.

  (3) Although the p-type deep layer 10 has been described in the first embodiment as extending in the normal direction of the side surface of the trench 6, the p-type deep layer 10 inclined in one direction with respect to the side surface of the trench 6. A structure in which a plurality of p-type deep layers 10 inclined in one direction with respect to the normal direction of the side surface of the trench 6 are arranged in a stripe shape and p is inclined in the opposite direction. A plurality of the deep mold layers 10 may be arranged in a stripe shape, and each stripe may intersect to form a lattice shape. That is, it is sufficient that the longitudinal direction of the p-type deep layer 10 intersects at least the longitudinal direction of the trench 6. In that case, each p-type deep layer 10 in which the gap between the p-type deep layer 10 and the p-type RESURF layer 15 described in the second embodiment or the size of the gap 10a described in the third embodiment forms a stripe. What is necessary is just to make it narrower than the clearance gap between each other.

  (4) In each of the above embodiments, the case where the outer peripheral withstand voltage structure provided in the outer peripheral region is configured by the p-type RESURF layer 15, the p-type guard ring layer 16, and the like has been described, but these are not necessarily required. That is, any structure may be used as long as it is generally used as an outer peripheral pressure resistant structure. Even in such a case, as shown in the first embodiment, the p-type deep layer 10 is formed so as to fill the entire outer edge of the cell region, or as shown in the second embodiment, the p-type deep layer is formed. 10 extends toward the outer peripheral region at the outer edge of the cell region, and is formed so as to be separated from the outer peripheral region by a predetermined distance, or as shown in the third embodiment, the p-type deep layer 10 is formed as a gap portion. 10a can be formed. As a result, the breakdown location is moved to the outer peripheral region by at least the p-type deep layer 10 formed at the outer edge of the cell region, so that a high breakdown voltage can be achieved.

(5) In each of the above embodiments, the case where the present invention is applied to an SiC semiconductor device including a MOSFET having an inverted trench gate structure has been described. However, the present invention can also be applied to a MOSFET having a storage type trench gate structure. FIG. 13 is a perspective cross-sectional view of one cell of a storage type trench gate structure MOSFET. As shown in this figure, an accumulation-type trench has a structure in which an n ⁻ -type channel layer 20 is provided in a trench 6 and a gate electrode 9 is formed on the surface of the n ⁻ -type channel layer 20 via a gate oxide film 8. A MOSFET having a gate structure is formed. The present invention can also be applied to a SiC semiconductor device including such a storage type trench gate MOSFET. In this case, the MOSFET in each of the above embodiments may be replaced from the inversion type to the storage type.

  (6) In addition, when indicating the orientation of a crystal, a bar (-) should be attached above a desired number, but in this specification, there is a limitation in expression based on a personal computer application. , And a bar before the desired number.

1 n ⁺ type substrate 2 n ⁻ type drift layer 3 p type base region 4 n ⁺ type source region 5 p ⁺ type contact layer 6 trench 8 gate oxide film 9 gate electrode 10 p type deep layer 11 source electrode 12 interlayer insulating film 13 Drain electrode 14 Mesa structure 15 p-type RESURF layer 16 p-type guard ring layer

Claims (9)

A first or second conductivity type substrate (1) made of silicon carbide;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate (1) and having a lower impurity concentration than the substrate (1);
A base region (3) made of silicon carbide of the second conductivity type formed on the drift layer (2) in the cell region;
A source region (4) formed on the base region (3) and made of silicon carbide of the first conductivity type having a higher concentration than the drift layer (2);
Deeper than the source region (4) and the base region (3) and reaches the drift layer (3), and the source region (4) and the base region (3) are disposed on both sides. A trench (6) having one direction as a longitudinal direction;
A gate insulating film (8) formed on the surface of the trench (6);
A gate electrode (9) formed on the gate insulating film (8) in the trench (6);
A source electrode (11) electrically connected to the source region (4) and the base region (3);
A drain electrode (13) formed on the back side of the substrate (1),
A plurality of the trenches (6) are extended in stripes, and the surface of the base region (3) located on the side surface of the trench (6) by controlling the voltage applied to the gate electrode (9) An inversion type channel region is formed in the inversion type, and an electric current is passed between the source electrode (11) and the drain electrode (13) through the source region (4) and the drift layer (2). MOSFET,
A silicon carbide semiconductor device comprising an outer peripheral pressure-resistant portion formed in an outer peripheral region surrounding the cell region,
Arranged below the base region (3) and at a position deeper than the trench (6), and in a direction intersecting the longitudinal direction of the trench (6) and parallel to the substrate plane A deep layer (10) of the second conductivity type extending in a stripe shape;
The outer periphery of the deep layer (10) surrounds the trench (6) arranged in a stripe shape and a portion of the deep layer (10) arranged in a stripe shape at the outer edge of the cell region. Extended towards the area,
The outer pressure resistance structure is
A mesa structure (14) formed of a recess deeper than the base region in the outer peripheral region of the cell region;
A second conductivity type RESURF layer (15) formed so as to have a predetermined depth from the bottom surface of the recess constituting the mesa structure (14) and surrounding the cell region;
The RESURF layer (15) has the same bottom depth as the deep layer (10). A first or second conductivity type substrate (1) made of silicon carbide;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate (1) and having a lower impurity concentration than the substrate (1);
A base region (3) made of silicon carbide of the second conductivity type formed on the drift layer (2) in the cell region;
A source region (4) formed on the base region (3) and made of silicon carbide of the first conductivity type having a higher concentration than the drift layer (2);
Deeper than the source region (4) and the base region (3) and reaches the drift layer (3), and the source region (4) and the base region (3) are disposed on both sides. A trench (6) having one direction as a longitudinal direction;
A channel layer (20) of a first conductivity type having a lower concentration than the source region on the surface of the trench (6);
A gate insulating film (8) formed on the surface of the channel layer (20) in the trench (6);
A gate electrode (9) formed on the gate insulating film (8) in the trench (6);
A source electrode (11) electrically connected to the source region (4) and the base region (3);
A drain electrode (13) formed on the back side of the substrate (1),
A plurality of the trenches (6) are extended in stripes, and a storage channel region is formed in the channel layer (20) by controlling a voltage applied to the gate electrode (9), A storage-type MOSFET for passing a current between the source electrode (11) and the drain electrode (13) via the source region (4) and the drift layer (2);
A silicon carbide semiconductor device comprising an outer peripheral pressure-resistant portion formed in an outer peripheral region surrounding the cell region,
Arranged below the base region (3) and at a position deeper than the trench (6), and in a direction intersecting the longitudinal direction of the trench (6) and parallel to the substrate plane A deep layer (10) of the second conductivity type extending in a stripe shape;
The outer periphery of the deep layer (10) surrounds the trench (6) arranged in a stripe shape and a portion of the deep layer (10) arranged in a stripe shape at the outer edge of the cell region. Extended towards the area,
The outer pressure resistance structure is
A mesa structure (14) formed of a recess deeper than the base region in the outer peripheral region of the cell region;
A second conductivity type RESURF layer (15) formed so as to have a predetermined depth from the bottom surface of the recess constituting the mesa structure (14) and surrounding the cell region;
The RESURF layer (15) has the same bottom depth as the deep layer (10).   The said deep layer (10) is formed in the outer peripheral part whole region of the said cell area | region, and is connected with the said RESURF layer (15) formed in the said outer peripheral area | region. Silicon carbide semiconductor device.   The deep layer (10) is formed at a predetermined distance from the resurf layer (15) formed in the outer peripheral region at an outer edge portion of the cell region, and the deep layer (10) and the resurf layer ( 15. The silicon carbide according to claim 1, wherein an interval between the first and second deep layers is narrower than an interval between the deep layers arranged in the stripe shape. Semiconductor device.   The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the deep layer (10) is formed over the entire outer edge portion of the cell region.   The deep layer (10) is formed at a predetermined distance from the outer peripheral region at an outer edge portion of the cell region, and an interval between the deep layer (10) and the outer peripheral region is the deep layer (10). 5. The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is narrower than an interval between the ones arranged in the stripe shape.   In the outer edge portion of the cell region, the deep layer (10) is provided with a gap portion (10a) where the deep layer (10) is not partially formed, to the gate electrode (9) of the MOSFET. The gap (10a) is filled with a depletion layer extending from the deep layer (10) to the gap (10a) when the voltage is not applied. The silicon carbide semiconductor device as described in any one of these. Forming a drift layer (2) made of silicon carbide of the first conductivity type having a lower impurity concentration than the substrate (1) on the first or second conductivity type substrate (1) made of silicon carbide; When,
In the cell region, on the surface layer portion of the drift layer (2), a portion arranged in a stripe extending in one direction, and a portion surrounding the portion arranged in the stripe at the outer edge of the cell region Forming a second conductivity type deep layer (10) extending toward an outer peripheral region surrounding the periphery of the cell region;
Forming a base region (3) made of silicon carbide of the second conductivity type on the deep layer (10) and the drift layer (2);
Forming a mesa structure (14) composed of a recess that removes the base region (3) and exposes the drift layer (2) in the outer peripheral region;
Forming a second conductivity type RESURF layer (15) from the side wall surface in the mesa structure portion (14) to the bottom surface of the recess;
By ion-implanting the first conductivity type impurity into the surface layer portion of the base region (3) in the base region (3), the first conductivity type silicon carbide having a higher concentration than the drift layer (2) is obtained. Forming a configured source region (4);
The deep layer (10) extends from the surface of the source region (4) to the drift layer (2) through the base region (3) and shallower than the deep layer (10). Forming a trench (6) having a longitudinal direction in a direction intersecting with the extending direction;
Forming a gate insulating film (8) in the trench (6);
Forming a gate electrode (9) on the gate insulating film (8) in the trench (6);
Forming a source electrode (11) electrically connected to the source region (4) and the base region (3);
Forming a drain electrode (13) on the back side of the substrate (1). A method for manufacturing a silicon carbide semiconductor device, comprising: Forming a drift layer (2) made of silicon carbide of the first conductivity type having a lower impurity concentration than the substrate (1) on the first or second conductivity type substrate (1) made of silicon carbide; When,
In the surface layer portion of the drift layer (2), in the cell region, a portion arranged in a stripe extending in one direction, and a portion surrounding the portion arranged in the stripe in the outer edge portion of the cell region; And forming a second conductivity type deep layer (10) extending toward an outer peripheral region surrounding the periphery of the cell region, and being connected to the deep layer (10) in the outer peripheral region. Forming the second conductivity type RESURF layer (15) surrounding the cell region at the same time,
Forming a base region (3) made of silicon carbide of the second conductivity type on the deep layer (10) and the drift layer (2);
Forming a mesa structure (14) composed of a recess that removes the base region (3) and exposes the drift layer (2) in the outer peripheral region;
By ion-implanting the first conductivity type impurity into the surface layer portion of the base region (3) in the base region (3), the first conductivity type silicon carbide having a higher concentration than the drift layer (2) is obtained. Forming a configured source region (4);
The deep layer (10) extends from the surface of the source region (4) to the drift layer (2) through the base region (3) and shallower than the deep layer (10). Forming a trench (6) having a longitudinal direction in a direction intersecting with the extending direction;
Forming a gate insulating film (8) in the trench (6);
Forming a gate electrode (9) on the gate insulating film (8) in the trench (6);
Forming a source electrode (11) electrically connected to the source region (4) and the base region (3);
Forming a drain electrode (13) on the back side of the substrate (1). A method for manufacturing a silicon carbide semiconductor device, comprising:

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