JPH06151867A - Vertical mos transistor and manufacture thereof - Google Patents

Vertical mos transistor and manufacture thereof

Info

Publication number
JPH06151867A
JPH06151867A JP4303981A JP30398192A JPH06151867A JP H06151867 A JPH06151867 A JP H06151867A JP 4303981 A JP4303981 A JP 4303981A JP 30398192 A JP30398192 A JP 30398192A JP H06151867 A JPH06151867 A JP H06151867A
Authority
JP
Japan
Prior art keywords
diffusion layer
source
type
diffusion
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4303981A
Other languages
Japanese (ja)
Other versions
JP2912508B2 (en
Inventor
Masatake Okada
正剛 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP4303981A priority Critical patent/JP2912508B2/en
Publication of JPH06151867A publication Critical patent/JPH06151867A/en
Application granted granted Critical
Publication of JP2912508B2 publication Critical patent/JP2912508B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Abstract

PURPOSE:To reduce an ON resistance of a vertical MOS transistor having a trench structure and obtain a high breakdown strength and simplify a process. CONSTITUTION:P-type well diffusion layers 5 and N-type source diffusion layers 6 formed by stacking the layers in a netted shape and gates of polysilicon layers 4 buried in insulating films 17 of trenches between the layers are installed on the surface of an N-type semiconductor substrate 1. Deep p-type diffusion layers 14 extending below the well diffusion layers 5 of the bottom of the source diffusion layers 6 are installed. The wall diffusion layers 5 and the source diffusion layers 6 are formed by an ion implantation and a thermal diffusion.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、縦型ＭＯＳトランジス
タ特にトレンチ構造を有するパワー用高耐圧低オン抵抗
の縦型ＭＯＳトランジスタおよびその製造方法の改良に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical MOS transistor, and more particularly to a power MOS high withstand voltage low on-resistance vertical MOS transistor having a trench structure and an improvement in its manufacturing method.

【０００２】[0002]

【従来の技術】縦型ＭＯＳトランジスタには、図８〜図
１０に示されるものがある。2. Description of the Related Art Some vertical MOS transistors are shown in FIGS.

【０００３】図８は、ゲート部にＶ字状の溝を形成した
ＶＭＯＳの略断面図である。Ｎ+ 型の基板２１の表面に
Ｎ- 型のエピタキシャル層２２を形成し、その表面にＰ
型拡散層２３，２３−１が形成されている。左側のＰ型
拡散層２３−１はガードリング用である。右側のＰ型拡
散層２３の表面には複数の領域のＮ+ 型拡散層２４，２
４…が形成されている。各Ｎ+ 型拡散層２４，２４…に
はＮ- 型エピタキシャル層２２に達するＶ字形の溝２
５，２５…が設けられている。全面にＳｉＯ2 のような
酸化膜２６が形成され、必要な場所に穴をあけ金属膜２
７を蒸着し、ゲート電極およびソース電極を形成し、ゲ
ート端子Ｇおよびソース端子Ｓとなる。裏面にも金属膜
２８を蒸着し、ドレイン電極が形成されドレイン端子Ｄ
となる。FIG. 8 is a schematic sectional view of a VMOS in which a V-shaped groove is formed in the gate portion. An N − type epitaxial layer 22 is formed on the surface of an N + type substrate 21, and P is formed on the surface.
The type diffusion layers 23 and 23-1 are formed. The P-type diffusion layer 23-1 on the left side is for the guard ring. On the surface of the P-type diffusion layer 23 on the right side, a plurality of N + -type diffusion layers 24 and 2 are formed.
4 are formed. Each of the N + type diffusion layers 24, 24 ... Has a V-shaped groove 2 reaching the N − type epitaxial layer 22.
5, 25 ... Are provided. An oxide film 26 such as SiO 2 is formed on the entire surface, and holes are formed where necessary to form the metal film 2.
7 is vapor-deposited to form a gate electrode and a source electrode, which serve as a gate terminal G and a source terminal S. A metal film 28 is also vapor-deposited on the back surface to form a drain electrode and a drain terminal D
Becomes

【０００４】図９は、二重拡散構造のＤＭＯＳの略断面
図である。Ｎ+ 型の基板２１の表面にＮ- 型のエピタキ
シャル層２２を形成し、その表面に複数のＰ型拡散層２
３，２３−１が形成されている。左側のＰ型拡散層２３
−１はガードリング用である。右側のＰ型拡散層２３の
表面には複数のＮ+ 型拡散層２４，２４…が二重拡散に
より形成されている。隣接するＰ型拡散層２３，２３の
表面に形成されたＮ+型拡散層２４，２４にまたがるよ
うにＳｉＯ2 のような酸化膜２６に埋設されたポリシリ
コン層２９が形成されゲートとなる。全面は酸化膜２６
で覆われ必要な場所に穴をあけ、金属膜２７を蒸着し、
ソース電極を形成する。裏面にも金属膜２８を蒸着しド
レイン電極が形成される。それぞれの電極はゲート端子
Ｇ，ソース端子Ｓおよびドレイン端子Ｄとなる。FIG. 9 is a schematic sectional view of a DMOS having a double diffusion structure. An N − type epitaxial layer 22 is formed on the surface of an N + type substrate 21, and a plurality of P type diffusion layers 2 are formed on the surface.
3, 23-1 is formed. Left P-type diffusion layer 23
-1 is for a guard ring. A plurality of N + type diffusion layers 24, 24 ... Are formed by double diffusion on the surface of the P type diffusion layer 23 on the right side. A polysilicon layer 29 embedded in an oxide film 26 such as SiO 2 is formed so as to straddle the N + type diffusion layers 24, 24 formed on the surfaces of the adjacent P type diffusion layers 23, 23 to serve as a gate. Oxide film 26 on the entire surface
Covered with a hole in the required place, the metal film 27 is vapor-deposited,
A source electrode is formed. The drain electrode is also formed by depositing the metal film 28 on the back surface. Each electrode serves as a gate terminal G, a source terminal S, and a drain terminal D.

【０００５】前述のＶＭＯＳおよびＤＭＯＳは、通常、
いずれも多数個のＦＥＴが素子内で並列接続されたマル
チセル構造を持つ。The aforementioned VMOS and DMOS are usually
Each has a multi-cell structure in which a large number of FETs are connected in parallel within the device.

【０００６】図１０は、トレンチ構造のゲートを有する
ＴＤＭＯＳの略断面図である。Ｎ+型の基板２１の表面
にＮ- 型エピタキシャル層２２を形成し、その表面にウ
ェル拡散層となるＰ型拡散層２３およびソース拡散層と
なるＮ+ 型拡散層２４を二重拡散により形成する。表面
から複数のトレンチ３０，３０…を形成し、酸化膜２６
を形成しゲート用のポリシリコン層２９を埋め込み、さ
らに全面に酸化膜２６を形成した後必要な場所に穴をあ
け、表面に金属膜２７を蒸着し、ソース電極およびゲー
ト電極を形成し、ソース端子Ｓおよびゲート端子Ｇとな
る。裏面にも金属膜２８を蒸着しドレイン電極を形成し
ドレイン端子Ｄとなる。ソース電極の一部はＰ型拡散層
２３に達しており、ゲート電極は酸化膜２６を貫いて埋
設されたポリシリコン層２９に接続されている。FIG. 10 is a schematic sectional view of a TDMOS having a gate having a trench structure. An N − type epitaxial layer 22 is formed on the surface of an N + type substrate 21, and a P type diffusion layer 23 to be a well diffusion layer and an N + type diffusion layer 24 to be a source diffusion layer are formed on the surface by double diffusion. To do. A plurality of trenches 30, 30 ... Are formed from the surface, and the oxide film 26 is formed.
Is formed, a polysilicon layer 29 for a gate is buried, an oxide film 26 is further formed on the entire surface, holes are formed at necessary places, a metal film 27 is deposited on the surface, a source electrode and a gate electrode are formed, and a source is formed. It becomes the terminal S and the gate terminal G. A metal film 28 is also vapor-deposited on the back surface to form a drain electrode, which serves as a drain terminal D. A part of the source electrode reaches the P-type diffusion layer 23, and the gate electrode is connected to the polysilicon layer 29 embedded through the oxide film 26.

【０００７】ＶＭＯＳはＶ字形の溝を形成するため微細
化が困難であり、ＤＭＯＳは微細化すればウェルとウェ
ルとの間の抵抗が大きくなり、低オン抵抗化が困難であ
る。VMOS is difficult to be miniaturized because it forms a V-shaped groove, and DMOS is difficult to reduce the on-resistance because the resistance between the wells becomes large if it is miniaturized.

【０００８】微細化および低オン抵抗化のためＴＤＭＯ
Ｓが使用されつつある。TDMO for miniaturization and low on-resistance
S is being used.

【０００９】[0009]

【発明が解決しようとする課題】トレンチ構造のＴＤＭ
ＯＳは、微細化および低オン抵抗化のためには有利であ
るが、トレンチを深く形成できないため、Ｐ型拡散層２
３のウェル拡散を浅くする必要があり、高耐圧化が困難
であり、また、工程が複雑であった。A TDM having a trench structure
OS is advantageous for miniaturization and low on-resistance, but the trench cannot be formed deeply, so the P-type diffusion layer 2
Since it was necessary to make the well diffusion of 3 shallow, it was difficult to increase the breakdown voltage, and the process was complicated.

【００１０】本発明の目的は、トレンチ構造のＭＯＳト
ランジスタのオン抵抗を低くし、抗耐圧化し、さらに工
程を簡略化することにある。An object of the present invention is to reduce the on-resistance of a MOS transistor having a trench structure, to withstand the breakdown voltage, and to further simplify the process.

【００１１】[0011]

【課題を解決するための手段】本発明の縦型ＭＯＳトラ
ンジスタにおいては、ソース部直下の深い拡散層とチッ
プ周辺部のガードリングを同時に形成し、高耐圧化を図
るとともに、ウェル拡散およびソース拡散をイオン注入
と熱酸化により半導体基板の主表面全面に行ない、その
後ゲートのトレンチ形成時にチップ周辺の不要なウェル
拡散およびソース拡散を取除く。また、ソースのコンタ
クトホールとゲートのコンタクトホールを同時にエッチ
ングにより形成し、工程を簡素化する。In the vertical MOS transistor of the present invention, a deep diffusion layer directly under the source portion and a guard ring in the peripheral portion of the chip are formed at the same time to achieve a high breakdown voltage, and well diffusion and source diffusion. Is performed on the entire main surface of the semiconductor substrate by ion implantation and thermal oxidation, and then unnecessary well diffusion and source diffusion around the chip are removed when the gate trench is formed. Further, the source contact hole and the gate contact hole are simultaneously formed by etching to simplify the process.

【００１２】[0012]

【作用】ソース拡散層と積層されたウェル拡散層の下部
の第２の導電型の拡散層の拡散を深くすることで、ウェ
ルの曲率が大きくなり、また、チップ周辺部にガードリ
ングを配置することで、半導体表面付近の空乏層の延び
を促進し、電界が緩和され高耐圧化が図られる。しか
も、ウェル拡散およびソース拡散は主表面全面に行なう
ので、この工程でのフォトエッチングが不必要となり、
さらに、ゲートコンタクトホール形成をソースコンタク
トホール形成と同時に行なうことで、従来のトレンチ構
造のＭＯＳトランジスタより大幅な工程短縮が図られ
る。By increasing the diffusion of the second conductive type diffusion layer below the well diffusion layer laminated with the source diffusion layer, the curvature of the well is increased and the guard ring is arranged in the peripheral portion of the chip. As a result, the extension of the depletion layer near the semiconductor surface is promoted, the electric field is relaxed, and the breakdown voltage is increased. Moreover, since well diffusion and source diffusion are performed on the entire main surface, photoetching in this step is unnecessary,
Further, by forming the gate contact hole at the same time as forming the source contact hole, the number of steps can be significantly shortened as compared with the conventional MOS transistor having the trench structure.

【００１３】[0013]

【実施例】図１（ａ）は本発明の一実施例の平面図であ
り、図１（ｂ）は図１（ａ）のＡ−Ａ′断面図である。
半導体基板のエッチング形状および拡散形状をわかりや
すくするため、図１（ａ）では、図１（ｂ）の表面の電
極配線を省略してある。1 (a) is a plan view of an embodiment of the present invention, and FIG. 1 (b) is a sectional view taken along the line AA 'of FIG. 1 (a).
In order to facilitate understanding of the etching shape and diffusion shape of the semiconductor substrate, the electrode wiring on the surface of FIG. 1B is omitted in FIG.

【００１４】図１（ａ）および（ｂ）において、Ｎ+ 型
の半導体基板１の表面には、Ｎ- 型のエピタキシャル層
２が形成されており、さらに、その表面には網目状に積
層して形成されたＰ型のウェル拡散層５，５…とＮ型の
ソース拡散層６，６…が設けられている。ウェル拡散層
５の下部およびガードリング部の下部には予め深い拡散
層のＰ型拡散層１４，１４…が形成されている。ただ
し、ガードリング部のＰ型拡散層１４はその上部を削り
取られている。Ｐ型拡散層１４，１４…の間に形成され
た溝には酸化膜１７よりなる絶縁層に埋設されたゲート
となるポリシリコン層４が設けられている。In FIGS. 1A and 1B, an N − type epitaxial layer 2 is formed on the surface of an N + type semiconductor substrate 1. Further, a N - type epitaxial layer 2 is laminated on the surface in a mesh shape. The P-type well diffusion layers 5, 5 ... And the N-type source diffusion layers 6, 6 ... .., which are deep diffusion layers, are formed in advance under the well diffusion layer 5 and under the guard ring portion. However, the upper portion of the P-type diffusion layer 14 of the guard ring portion is scraped off. A polysilicon layer 4 serving as a gate embedded in an insulating layer made of an oxide film 17 is provided in the groove formed between the P type diffusion layers 14, 14.

【００１５】ガードリング部とソース部との境界にはポ
リシリコンのサイドウォール７が形成されている。A polysilicon sidewall 7 is formed at the boundary between the guard ring portion and the source portion.

【００１６】表面は酸化膜１７とＰＳＧ膜８で覆われ、
必要な箇所に穴をあけ金属膜１８および１９を蒸着して
ゲート電極およびソース電極を形成し、ゲート端子Ｇお
よびソース端子Ｓが設けられている。ソース電極はウェ
ル拡散層５に達しており、ゲート電極はポリシリコン層
４に達している。The surface is covered with an oxide film 17 and a PSG film 8,
A hole is formed in a required place, metal films 18 and 19 are vapor-deposited to form a gate electrode and a source electrode, and a gate terminal G and a source terminal S are provided. The source electrode reaches the well diffusion layer 5, and the gate electrode reaches the polysilicon layer 4.

【００１７】裏面にも金属膜２０を蒸着しドレイン電極
を形成しドレイン端子Ｄが設けられている。A metal film 20 is vapor-deposited on the back surface to form a drain electrode, and a drain terminal D is provided.

【００１８】図２〜図７は、図１（ａ）および（ｂ）の
構造のＭＯＳトランジスタの製造工程の略断面図であ
る。2 to 7 are schematic cross-sectional views of the manufacturing process of the MOS transistor having the structure shown in FIGS. 1 (a) and 1 (b).

【００１９】図２に示されるように、たとえばＮ型不純
物であるアンチモン（Ｓｂ）を約７×１０18atoms/cm3
の濃度で含むＮ型シリコン基板１上に、同じくＮ型不純
物であるリン（Ｐ）を約３×１０14atoms/cm3 の濃度で
含むエピタキシャル層２を約４５μm 成長させた後、ソ
ース部およびチップ周辺のガードリング部に、Ｐ型不純
物であるボロン（Ｂ）を拡散深さが５〜６μm となるよ
うに拡散し、Ｐ型拡散層１４，１４…を形成する。全面
は酸化膜１３で覆われる。As shown in FIG. 2, for example, about 7 × 10 18 atoms / cm 3 of antimony (Sb), which is an N-type impurity, is added.
After the epitaxial layer 2 containing phosphorus (P), which is also an N-type impurity at a concentration of about 3 × 10 14 atoms / cm 3 , is grown on the N-type silicon substrate 1 at a concentration of about 45 μm, the source portion and Boron (B), which is a P-type impurity, is diffused in the guard ring portion around the chip to a diffusion depth of 5 to 6 μm to form P-type diffusion layers 14, 14. The entire surface is covered with the oxide film 13.

【００２０】次に、図３に示されるように、酸化膜１３
を一旦剥離した後、約１５０〜３００Åの酸化膜１５を
ウェハ表面に均一に形成した後、ボロン（Ｂ）をたとえ
ば加速電圧５０ｋｅｖ，ドーズ量５×１０13 ions/cm3
で、砒素（Ａｓ）をたとえば加速電圧８０ｋｅｖ，ドー
ズ量５×１０15 ions/cm3 で、連続してイオン注入す
る。Next, as shown in FIG. 3, the oxide film 13 is formed.
And then an oxide film 15 having a thickness of about 150 to 300 Å is uniformly formed on the wafer surface, and then boron (B) is added, for example, at an acceleration voltage of 50 kev and a dose amount of 5 × 10 13 ions / cm 3.
Then, arsenic (As) is continuously ion-implanted at an acceleration voltage of 80 kev and a dose amount of 5 × 10 15 ions / cm 3 .

【００２１】次に図４に示すように、熱拡散によりボロ
ンの拡散深さが１．５〜１．８μm，砒素の拡散深さが
０．３〜０．５μm となるようにドライブインすると、
表面には全面にわたりウェル拡散層５およびソース拡散
層６が形成される。その後全面に窒化膜３をデポジショ
ンし、周知のフォトリソグラフィ技術により、図１
（ａ）に示すように網目状に開口し、窒化膜３をエッチ
ングした後、四塩化炭素（ＣＣｌ4 ）と酸素（Ｏ2 ）の
混合ガスを用いて反応性イオンエッチングを行ない、ソ
ース部およびゲート配線部のＰ型拡散層１４，１４…の
間のエピタキシャル層２に、２，０〜２．２μm の溝
（トレンチ）１６，１６…を形成する。このときガード
リング部の上部のエピタキシャル層２の一部およびＰ型
拡散層１４の一部ならびにウェル拡散層５およびソース
拡散層の延長された不要な部分も除去する。溝１６の周
辺を含む全面には、膜厚が約６００Åとなるように酸化
膜１７を形成する。そして、全面にデポジションによ
り、ドープされたポリシリコン層４を、約２．５μm の
厚さに形成する。これは溝１６，１６…の中にも入り込
む。Next, as shown in FIG. 4, drive-in is performed so that the diffusion depth of boron is 1.5 to 1.8 μm and the diffusion depth of arsenic is 0.3 to 0.5 μm by thermal diffusion.
A well diffusion layer 5 and a source diffusion layer 6 are formed on the entire surface. After that, a nitride film 3 is deposited on the entire surface, and the well-known photolithography technique is used to form the nitride film 3 shown in FIG.
As shown in (a), after opening in a mesh shape to etch the nitride film 3, reactive ion etching is performed using a mixed gas of carbon tetrachloride (CCl 4 ) and oxygen (O 2 ). .. are formed in the epitaxial layer 2 between the P-type diffusion layers 14, 14 of the gate wiring portion. At this time, a part of the epitaxial layer 2 and a part of the P-type diffusion layer 14 on the upper part of the guard ring part and an unnecessary extended part of the well diffusion layer 5 and the source diffusion layer are also removed. An oxide film 17 is formed on the entire surface including the periphery of the groove 16 so as to have a film thickness of about 600 Å. Then, a doped polysilicon layer 4 is formed on the entire surface to a thickness of about 2.5 μm. This also goes into the grooves 16, 16.

【００２２】次に図５に示すように、四塩化炭素（ＣＣ
ｌ4 ）と六フッ化硫黄（ＳＦ6 ）の混合ガスを用いて反
応性イオンエッチングを行ない、窒化膜３が現われるま
でポリシリコン層４のエッチングを行なう。このとき溝
１６の深さを適切にしておけば、この溝１６の部分のポ
リシリコン層４は厚いから、表面から一様にエッチング
したとき溝１６，１６…の部分のポリシリコン層は残
る。また同様に、チップ周辺のエピタキシャル層をエッ
チングした部分とソース部のエピタキシャル層を除去し
なかった部分との境界には、ポリシリコンのサイドウォ
ール７，７が形成される。このサイドウォール７は、以
降の工程でのレジスト，電極等の段切れを防止する。そ
の後局所酸化を行ない、窒化膜３を剥離する。表面は再
び酸化膜１７で覆われる。Next, as shown in FIG. 5, carbon tetrachloride (CC
reactive ion etching is performed using a mixed gas of l 4 ) and sulfur hexafluoride (SF 6 ), and the polysilicon layer 4 is etched until the nitride film 3 appears. At this time, if the depth of the groove 16 is set appropriately, the polysilicon layer 4 in the portion of the groove 16 is thick, so that the polysilicon layer in the portions of the grooves 16, 16 ... Remains when uniformly etched from the surface. Similarly, polysilicon sidewalls 7, 7 are formed at the boundary between the portion around the chip where the epitaxial layer is etched and the portion where the epitaxial layer at the source portion is not removed. The side wall 7 prevents breakage of the resist, electrodes, etc. in the subsequent steps. After that, local oxidation is performed to peel off the nitride film 3. The surface is again covered with the oxide film 17.

【００２３】次に図６に示されるように、全面にデポジ
ションによりＰＳＧ膜８を形成し、ダイシングライン部
９，ガードリング部コンタクトホール１０，ソース部コ
ンタクトホール１１，ゲート部コンタクトホール１２等
を同時に反応性イオンエッチングにより形成する。この
とき、ソース部コンタクトホール１１は、ソース拡散層
６のＮ+ 部の厚み０．３〜０．５μm を超えるようにエ
ッチングする必要があるが、ソース部コンタクトホール
１１の上にあった酸化膜は、図５に示されるように、他
の部分より局所酸化の厚み分だけ薄いので、ガスの種
類，流量，温度等を適切に選ぶことによって、ソース部
コンタクトホールは深く、他の部分は浅くエッチングす
ることができる。Next, as shown in FIG. 6, a PSG film 8 is formed on the entire surface by deposition, and a dicing line part 9, a guard ring part contact hole 10, a source part contact hole 11, a gate part contact hole 12, etc. are formed. At the same time, it is formed by reactive ion etching. At this time, the source contact hole 11 needs to be etched so that the thickness of the N + portion of the source diffusion layer 6 exceeds 0.3 to 0.5 μm. As shown in FIG. 5, since it is thinner than other portions by the thickness of local oxidation, the source portion contact hole is deep and the other portions are shallow by appropriately selecting the kind, flow rate, temperature, etc. of gas. It can be etched.

【００２４】最後に図７に示すように、表面にたとえば
Ａｌ−Ｓｉ膜のような金属膜１８，１９を蒸着により形
成してゲート電極およびソース電極を形成し、裏面にた
とえばＡｌ−Ｍｏ−Ｎｉ膜のような金属膜２０を蒸着に
より形成しゲート電極とし、図１（ｂ）に示されるよう
に、ゲート端子Ｇ，ソース端子Ｓ，ドレイン端子Ｄを設
ける。Finally, as shown in FIG. 7, metal films 18, 19 such as Al-Si films are formed on the front surface by vapor deposition to form gate electrodes and source electrodes, and on the back surface, for example, Al-Mo-Ni. A metal film 20 such as a film is formed by vapor deposition to serve as a gate electrode, and a gate terminal G, a source terminal S, and a drain terminal D are provided as shown in FIG.

【００２５】なお、図２〜図７の例では、ウェル拡散層
５の数が図１（ａ）および（ｂ）の場合と異なってい
る。In the examples of FIGS. 2 to 7, the number of well diffusion layers 5 is different from that in FIGS. 1 (a) and 1 (b).

【００２６】[0026]

【発明の効果】本発明によれば、トレンチ構造でウェル
拡散層が１．５〜１．８μm と浅いが、ソース拡散層６
の中央下部に５〜６μm の深いＰ型拡散層１４があるた
め、ドレインとソースとの間に電圧を印加した場合、こ
の深いＰ型拡散層１４より空乏層がトレンチ部を覆うよ
うに延び、空乏層の曲率がこの深い拡散層で決定される
ことと、チップ周辺部にガードリングを配置すること
で、チップ表面付近の空乏層の延びが促進されることに
よって、高耐圧化が図れる。According to the present invention, the source diffusion layer 6 has a trench structure having a shallow well diffusion layer of 1.5 to 1.8 μm.
Since there is a deep P-type diffusion layer 14 of 5 to 6 μm in the lower central part of the, when a voltage is applied between the drain and the source, a depletion layer extends from the deep P-type diffusion layer 14 so as to cover the trench portion, Since the curvature of the depletion layer is determined by this deep diffusion layer and the guard ring is arranged in the peripheral portion of the chip, the extension of the depletion layer near the chip surface is promoted, so that the breakdown voltage can be increased.

【００２７】また、ウェル拡散層，ソース拡散層は、イ
オン注入と熱拡散によって行なわれるから、フォトエッ
チングを用いる必要がなく、ソース部のコンタクトホー
ル形成をガードリング部およびゲート配線部のコンタク
トホール形成およびダイシング部の形成と同時にできる
から、大幅な工程短縮が図られ製造コストを安くするこ
とができる。Further, since the well diffusion layer and the source diffusion layer are formed by ion implantation and thermal diffusion, it is not necessary to use photoetching, and the contact hole in the source portion is formed in the guard ring portion and the gate wiring portion. Also, since it can be performed at the same time as the formation of the dicing portion, the process can be significantly shortened and the manufacturing cost can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図１】（ａ）は本発明の一実施例の平面図であり、
（ｂ）はそのＡ−Ａ′断面図である。FIG. 1A is a plan view of an embodiment of the present invention,
(B) is the AA 'sectional view.

【図２】本発明の一実施例の一工程の略断面図である。FIG. 2 is a schematic cross-sectional view of a step in one example of the present invention.

【図３】本発明の一実施例の一工程の略断面図である。FIG. 3 is a schematic cross-sectional view of a step of an example of the present invention.

【図４】本発明の一実施例の一工程の略断面図である。FIG. 4 is a schematic cross-sectional view of a step of an example of the present invention.

【図５】本発明の一実施例の一工程の略断面図である。FIG. 5 is a schematic cross sectional view of a step of an example of the present invention.

【図６】本発明の一実施例の一工程の略断面図である。FIG. 6 is a schematic cross-sectional view of a step of an example of the present invention.

【図７】本発明の一実施例の一工程の略断面図である。FIG. 7 is a schematic sectional view of a step of an example of the present invention.

【図８】従来のＶＭＯＳトランジスタの略断面図であ
る。FIG. 8 is a schematic cross-sectional view of a conventional VMOS transistor.

【図９】従来のＤＭＯＳトランジスタの略断面図であ
る。FIG. 9 is a schematic cross-sectional view of a conventional DMOS transistor.

【図１０】従来のＴＤＭＯＳの略断面図である。FIG. 10 is a schematic cross-sectional view of a conventional TDMOS.

【符号の説明】[Explanation of symbols]

１ シリコン基板 ２ エピタキシャル層 ３ 窒化膜 ４ ポリシリコン層 ５ ウェル拡散層 ６ ソース拡散層 ７ サイドウォール ８ ＰＳＧ膜 １０ ガードリング部コンタクトホール １１ ソース部コンタクトホール １２ ゲート配線部コンタクトホール １３，１５，１７ 酸化膜 １４ Ｐ型拡散層 １６ 溝 1 Silicon substrate 2 Epitaxial layer 3 Nitride film 4 Polysilicon layer 5 Well diffusion layer 6 Source diffusion layer 7 Sidewall 8 PSG film 10 Guard ring part contact hole 11 Source part contact hole 12 Gate wiring part contact hole 13, 15, 17 Oxidation Membrane 14 P-type diffusion layer 16 Groove

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 第１の導電型の半導体基板の表面に網目
状に積層して形成された第２の導電型のウェル拡散層と
第１の導電型のソース拡散層と、これらの間の溝の絶縁
膜に埋設されたゲートとを有するトレンチ構造の縦型Ｍ
ＯＳトランジスタにおいて、ソース拡散層の下部のウェ
ル拡散層の下方に延長する深い第２の導電型の拡散層を
有することを特徴とする縦型ＭＯＳトランジスタ。1. A second-conductivity-type well diffusion layer and a first-conductivity-type source diffusion layer, which are formed by laminating in a mesh shape on the surface of a first-conductivity-type semiconductor substrate, and between these well diffusion layers. Vertical type M of trench structure having gate buried in insulating film of trench
A vertical MOS transistor, wherein the OS transistor has a deep second conductivity type diffusion layer extending below the well diffusion layer below the source diffusion layer. 【請求項２】 第１の導電型の半導体基板の表面のソー
ス部とガードリング部に複数の第２の導電型の深い拡散
層を形成する工程と、 表面に第１の導電型の不純物と第２の導電型の不純物を
イオン注入し熱拡散によりウェル拡散層とソース拡散層
を形成する工程と、 エッチングによりゲート部のトレンチを形成し同時にチ
ップ周辺部の不要なウェル拡散層とソース拡散層とを除
去しガードリング部を残す工程とを有することを特徴と
する請求項１記載の縦型ＭＯＳトランジスタの製造方
法。2. A step of forming a plurality of second conductivity type deep diffusion layers on a source portion and a guard ring portion of a surface of a first conductivity type semiconductor substrate, and an impurity of the first conductivity type on the surface. A step of forming a well diffusion layer and a source diffusion layer by thermal diffusion by ion-implanting a second conductivity type impurity, and a trench of a gate portion is formed by etching and unnecessary well diffusion layer and source diffusion layer at the periphery of the chip are also formed. 2. The method of manufacturing a vertical MOS transistor according to claim 1, further comprising: 【請求項３】 ソース部コンタクトホールとしてソース
拡散層の拡散深さより深くかつウェル拡散層の拡散深さ
より浅くなるようなトレンチと、ゲート部コンタクトホ
ールとして絶縁膜を貫きゲートに達するトレンチとを同
時にエッチングにより形成する工程を有する請求項１記
載の縦型ＭＯＳトランジスタの製造方法。3. A trench which is deeper than a diffusion depth of a source diffusion layer and shallower than a diffusion depth of a well diffusion layer as a source contact hole and a trench which penetrates an insulating film and reaches a gate as a gate contact hole are simultaneously etched. 2. The method for manufacturing a vertical MOS transistor according to claim 1, further comprising the step of:
JP4303981A 1992-11-13 1992-11-13 Method of manufacturing vertical MOS transistor Expired - Fee Related JP2912508B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4303981A JP2912508B2 (en) 1992-11-13 1992-11-13 Method of manufacturing vertical MOS transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4303981A JP2912508B2 (en) 1992-11-13 1992-11-13 Method of manufacturing vertical MOS transistor

Publications (2)

Publication Number Publication Date
JPH06151867A true JPH06151867A (en) 1994-05-31
JP2912508B2 JP2912508B2 (en) 1999-06-28

Family

ID=17927606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4303981A Expired - Fee Related JP2912508B2 (en) 1992-11-13 1992-11-13 Method of manufacturing vertical MOS transistor

Country Status (1)

Country Link
JP (1) JP2912508B2 (en)

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19620021A1 (en) * 1995-05-19 1996-11-21 Nissan Motor U=shaped trench MOS semiconductor power transistor device
EP0813250A2 (en) * 1996-06-13 1997-12-17 Plessey Semiconductors Limited Trench semiconductor device
JPH1098188A (en) * 1996-08-01 1998-04-14 Kansai Electric Power Co Inc:The Insulated gate semiconductor device
KR100241050B1 (en) * 1996-12-31 2000-02-01 김덕중 Method for manufacturing power transistor
US6037633A (en) * 1996-11-01 2000-03-14 Nissan Motor Co., Ltd. Semiconductor device
JP2000332246A (en) * 1999-05-10 2000-11-30 Intersil Corp Process of forming mos gate device having self-aligned trench
WO2001008226A3 (en) * 1999-07-22 2001-09-13 Koninkl Philips Electronics Nv Cellular trench-gate field-effect transistors
EP1191603A2 (en) * 2000-09-22 2002-03-27 GENERAL SEMICONDUCTOR, Inc. Trench MOS device and termination structure
EP1191602A2 (en) 2000-09-22 2002-03-27 GENERAL SEMICONDUCTOR, Inc. Method of forming trench MOS device and termination structure
JP2002164541A (en) * 2000-11-29 2002-06-07 Denso Corp Semiconductor device and its fabricating method
JP2002368221A (en) * 2001-06-08 2002-12-20 Nec Corp Semiconductor device equipped with longitudinal mosfet and manufacturing method therefor
JP2005019734A (en) * 2003-06-26 2005-01-20 Renesas Technology Corp Semiconductor device and its manufacturing method
US7037788B2 (en) 2000-05-30 2006-05-02 Denso Corporation Manufacturing method of semiconductor device
JP2007281515A (en) * 1994-08-15 2007-10-25 Siliconix Inc Trench type dmos transistor manufactured by relatively small number of masking processes and having thick oxide layer in distal region, and its manufacturing method
JP2011101036A (en) * 2011-01-07 2011-05-19 Denso Corp Silicon carbide semiconductor device and manufacturing method thereof
JP4771694B2 (en) * 2002-05-03 2011-09-14 フェアチャイルド・セミコンダクター・コーポレーション Trench gate power device and its edge termination technology
JP2012009502A (en) * 2010-06-22 2012-01-12 Denso Corp Semiconductor device
ITTO20100724A1 (en) * 2010-08-30 2012-03-01 St Microelectronics Srl INTEGRATED ELECTRONIC DEVICE WITH ON-BOARD TERMINATION STRUCTURE AND ITS MANUFACTURING METHOD
CN102884631A (en) * 2010-03-16 2013-01-16 威世通用半导体公司 Trench DMOS device with improved termination structure for high voltage applications
CN103180958A (en) * 2010-10-21 2013-06-26 威世通用半导体公司 Trench dmos device with improved termination structure for high voltage applications
EP2672517A1 (en) * 2011-02-02 2013-12-11 Rohm Co., Ltd. Semiconductor device and method for producing same
US8653590B2 (en) 2010-08-30 2014-02-18 Stmicroelectronics S.R.L. Vertical-conduction integrated electronic device and method for manufacturing thereof
CN104380471A (en) * 2012-06-13 2015-02-25 株式会社电装 Silicon carbide semiconductor device and method for producing same
US9142666B2 (en) 2010-08-30 2015-09-22 Stmicroelectronics S.R.L. Integrated electronic device and method for manufacturing thereof
CN109801978A (en) * 2019-03-13 2019-05-24 捷捷半导体有限公司 Low pressure drop diode and preparation method thereof
WO2020247013A1 (en) * 2019-06-05 2020-12-10 Microchip Technology Inc. Space efficient high-voltage termination and process for fabricating the same

Cited By (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007281515A (en) * 1994-08-15 2007-10-25 Siliconix Inc Trench type dmos transistor manufactured by relatively small number of masking processes and having thick oxide layer in distal region, and its manufacturing method
DE19620021A1 (en) * 1995-05-19 1996-11-21 Nissan Motor U=shaped trench MOS semiconductor power transistor device
US5682048A (en) * 1995-05-19 1997-10-28 Nissan Motor Co., Ltd. Groove-type semiconductor device
DE19620021B4 (en) * 1995-05-19 2005-06-02 Nissan Motor Co., Ltd., Yokohama Semiconductor device of the trench type
EP0813250A2 (en) * 1996-06-13 1997-12-17 Plessey Semiconductors Limited Trench semiconductor device
EP0813250A3 (en) * 1996-06-13 1998-10-07 Mitel Semiconductor Limited Trench semiconductor device
JPH1098188A (en) * 1996-08-01 1998-04-14 Kansai Electric Power Co Inc:The Insulated gate semiconductor device
US6037633A (en) * 1996-11-01 2000-03-14 Nissan Motor Co., Ltd. Semiconductor device
KR100241050B1 (en) * 1996-12-31 2000-02-01 김덕중 Method for manufacturing power transistor
JP2000332246A (en) * 1999-05-10 2000-11-30 Intersil Corp Process of forming mos gate device having self-aligned trench
WO2001008226A3 (en) * 1999-07-22 2001-09-13 Koninkl Philips Electronics Nv Cellular trench-gate field-effect transistors
US7037788B2 (en) 2000-05-30 2006-05-02 Denso Corporation Manufacturing method of semiconductor device
JP2002208711A (en) * 2000-09-22 2002-07-26 General Semiconductor Inc Method of forming trench mos devices and termination structure
EP1191603A2 (en) * 2000-09-22 2002-03-27 GENERAL SEMICONDUCTOR, Inc. Trench MOS device and termination structure
JP2010161395A (en) * 2000-09-22 2010-07-22 General Semiconductor Inc Method of fabricating trench metal oxide semiconductor device and termination structure
EP1191603A3 (en) * 2000-09-22 2004-11-17 GENERAL SEMICONDUCTOR, Inc. Trench MOS device and termination structure
EP1191602A3 (en) * 2000-09-22 2004-12-29 GENERAL SEMICONDUCTOR, Inc. Method of forming trench MOS device and termination structure
JP4685297B2 (en) * 2000-09-22 2011-05-18 ゼネラル セミコンダクター，インク． Trench metal oxide semiconductor device and method of manufacturing termination structure
JP2010157761A (en) * 2000-09-22 2010-07-15 General Semiconductor Inc Termination structure and trench metal oxide film semiconductor device
JP4702822B2 (en) * 2000-09-22 2011-06-15 ゼネラル セミコンダクター，インク． Termination structure and trench metal oxide semiconductor device
EP1191602A2 (en) 2000-09-22 2002-03-27 GENERAL SEMICONDUCTOR, Inc. Method of forming trench MOS device and termination structure
JP2002217426A (en) * 2000-09-22 2002-08-02 General Semiconductor Inc Termination structure and trench metal oxide film semiconductor device
JP4736180B2 (en) * 2000-11-29 2011-07-27 株式会社デンソー Semiconductor device and manufacturing method thereof
JP2002164541A (en) * 2000-11-29 2002-06-07 Denso Corp Semiconductor device and its fabricating method
JP2002368221A (en) * 2001-06-08 2002-12-20 Nec Corp Semiconductor device equipped with longitudinal mosfet and manufacturing method therefor
JP4771694B2 (en) * 2002-05-03 2011-09-14 フェアチャイルド・セミコンダクター・コーポレーション Trench gate power device and its edge termination technology
US6885061B2 (en) 2003-06-26 2005-04-26 Renesas Technology Corp. Semiconductor device and a method of manufacturing the same
US7518183B2 (en) 2003-06-26 2009-04-14 Renesas Technology Corp. Semiconductor device
US7042048B2 (en) 2003-06-26 2006-05-09 Renesas Technology Corporation Semiconductor device and a method of manufacturing the same
JP2005019734A (en) * 2003-06-26 2005-01-20 Renesas Technology Corp Semiconductor device and its manufacturing method
US8928065B2 (en) 2010-03-16 2015-01-06 Vishay General Semiconductor Llc Trench DMOS device with improved termination structure for high voltage applications
EP2548230A4 (en) * 2010-03-16 2014-01-15 Vishay Gen Semiconductor Llc Trench dmos device with improved termination structure for high voltage applications
US8853770B2 (en) 2010-03-16 2014-10-07 Vishay General Semiconductor Llc Trench MOS device with improved termination structure for high voltage applications
CN102884631A (en) * 2010-03-16 2013-01-16 威世通用半导体公司 Trench DMOS device with improved termination structure for high voltage applications
EP2548230A1 (en) * 2010-03-16 2013-01-23 Vishay General Semiconductor LLC Trench dmos device with improved termination structure for high voltage applications
JP2013522909A (en) * 2010-03-16 2013-06-13 ビシャイ・ジェネラル・セミコンダクター・エルエルシー Trench DMOS device with improved termination structure for high voltage application
JP2012009502A (en) * 2010-06-22 2012-01-12 Denso Corp Semiconductor device
US9257550B2 (en) 2010-08-30 2016-02-09 Stmicroelectronics S.R.L. Integrated electronic device and method for manufacturing thereof
US9018635B2 (en) 2010-08-30 2015-04-28 Stmicroelectronics S.R.L. Integrated electronic device with edge-termination structure and manufacturing method thereof
US8653590B2 (en) 2010-08-30 2014-02-18 Stmicroelectronics S.R.L. Vertical-conduction integrated electronic device and method for manufacturing thereof
ITTO20100724A1 (en) * 2010-08-30 2012-03-01 St Microelectronics Srl INTEGRATED ELECTRONIC DEVICE WITH ON-BOARD TERMINATION STRUCTURE AND ITS MANUFACTURING METHOD
US8921211B2 (en) 2010-08-30 2014-12-30 Stmicroelectronics S.R.L. Vertical-conduction integrated electronic device and method for manufacturing thereof
US9142666B2 (en) 2010-08-30 2015-09-22 Stmicroelectronics S.R.L. Integrated electronic device and method for manufacturing thereof
US9142646B2 (en) 2010-08-30 2015-09-22 Stmicroelectronics S.R.L. Integrated electronic device with edge-termination structure and manufacturing method thereof
EP2630661A2 (en) * 2010-10-21 2013-08-28 Vishay General Semiconductor LLC Trench dmos device with improved termination structure for high voltage applications
EP2630661A4 (en) * 2010-10-21 2014-01-22 Vishay Gen Semiconductor Llc Trench dmos device with improved termination structure for high voltage applications
CN103180958A (en) * 2010-10-21 2013-06-26 威世通用半导体公司 Trench dmos device with improved termination structure for high voltage applications
JP2011101036A (en) * 2011-01-07 2011-05-19 Denso Corp Silicon carbide semiconductor device and manufacturing method thereof
US10068964B2 (en) 2011-02-02 2018-09-04 Rohm Co., Ltd. Semiconductor device
US11804520B2 (en) 2011-02-02 2023-10-31 Rohm Co., Ltd. Semiconductor device
EP2672517A1 (en) * 2011-02-02 2013-12-11 Rohm Co., Ltd. Semiconductor device and method for producing same
EP2672517A4 (en) * 2011-02-02 2014-08-13 Rohm Co Ltd Semiconductor device and method for producing same
US11133377B2 (en) 2011-02-02 2021-09-28 Rohm Co., Ltd. Semiconductor device
US9136322B2 (en) 2011-02-02 2015-09-15 Rohm Co., Ltd. Semiconductor device
US9620593B2 (en) 2011-02-02 2017-04-11 Rohm Co., Ltd. Semiconductor device
US10680060B2 (en) 2011-02-02 2020-06-09 Rohm Co., Ltd. Semiconductor device
EP3460855A1 (en) * 2011-02-02 2019-03-27 Rohm Co., Ltd. Semiconductor device
EP2863440A4 (en) * 2012-06-13 2016-03-16 Denso Corp Silicon carbide semiconductor device and method for producing same
US9818860B2 (en) 2012-06-13 2017-11-14 Denso Corporation Silicon carbide semiconductor device and method for producing the same
CN104380471B (en) * 2012-06-13 2017-10-27 株式会社电装 Manufacturing silicon carbide semiconductor device and its manufacture method
US9543428B2 (en) 2012-06-13 2017-01-10 Denso Corporation Silicon carbide semiconductor device and method for producing the same
CN104380471A (en) * 2012-06-13 2015-02-25 株式会社电装 Silicon carbide semiconductor device and method for producing same
CN109801978A (en) * 2019-03-13 2019-05-24 捷捷半导体有限公司 Low pressure drop diode and preparation method thereof
CN109801978B (en) * 2019-03-13 2024-03-19 捷捷半导体有限公司 Low-voltage drop diode and preparation method thereof
WO2020247013A1 (en) * 2019-06-05 2020-12-10 Microchip Technology Inc. Space efficient high-voltage termination and process for fabricating the same
US11158703B2 (en) 2019-06-05 2021-10-26 Microchip Technology Inc. Space efficient high-voltage termination and process for fabricating same

Also Published As

Publication number Publication date
JP2912508B2 (en) 1999-06-28

Similar Documents

Publication Publication Date Title
JP2912508B2 (en) Method of manufacturing vertical MOS transistor
US11075297B2 (en) Semiconductor device and method of manufacturing semiconductor device
KR100400079B1 (en) Method for fabricating trench-gated power semiconductor device
US8237221B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP2689606B2 (en) Method for manufacturing insulated gate field effect transistor
US5689128A (en) High density trenched DMOS transistor
KR100727452B1 (en) Process For Forming MOS-Gated Devices Having Self-Aligned Trenches
US6236099B1 (en) Trench MOS device and process for radhard device
JP5298565B2 (en) Semiconductor device and manufacturing method thereof
JP2008103563A (en) Superjunction semiconductor device manufacturing method
CN110620152A (en) Trench type metal oxide semiconductor field effect transistor
JP4183620B2 (en) Semiconductor device and manufacturing method thereof
JP2004064063A (en) High voltage vertical type dmos transistor, and method for producing the same
JP2005510088A (en) Trench metal oxide semiconductor field effect transistor device with polycrystalline silicon source contact structure
US8017494B2 (en) Termination trench structure for mosgated device and process for its manufacture
JP2009505434A (en) Power semiconductor device manufacturing method
US8022475B2 (en) Semiconductor device optimized to increase withstand voltage and reduce on resistance
US7230300B2 (en) Semiconductor device with peripheral trench
JP2002026323A (en) Method of manufacturing trench gate type mis device having thick polysilicon insulating layer at bottom of trench
JP2003243655A (en) Insulated gate type transistor and method for manufacturing the same
WO2006082618A1 (en) Semiconductor device and method for manufacturing the same
JP2006332232A (en) Semiconductor device and manufacturing method thereof
KR20010013918A (en) Manufacture of field-effect semiconductor devices
CN113964038B (en) Method for manufacturing trench gate MOSFET device
JP2006196583A (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19990330

LAPS Cancellation because of no payment of annual fees