JPH08255902A - Insulated gate semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE: To obtain an insulated gate semiconductor device in which the polysilicon gate is protected against cracking by rounding the opposite ends at the upper part of a gate electrode buried in a trench part. CONSTITUTION: A gate electrode 5 is buried in a trench part made in a semiconductor layer 3 of one conductivity type. In such a trench gate insulated gate semiconductor device, the gate electrode 5 buried in the trench part is rounded at the upper opposite ends thereof. For example, a polysilicon gate buried in a trench is etched back and then subjected to isotropic etching, i.e., chemical dry polysilicon etching. Consequently, the trench side wall part A is not sharpened but rounded at the upper part of the polysilicon gate 5. Alternatively, an N source layer 4 is diffused with phosphorus from an insulating oxide 7, i.e., a silicon oxide added, at least to the lowermost layer thereof, with phosphorus exhibiting stress relaxing action.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device in which a gate electrode is embedded in a trench (groove) provided in a semiconductor substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art As an example of a conventional trench gate type semiconductor device, a trench gate type (Insulated G type) is used.
ate Bipolar Transistor) IG
A cross-sectional view of the element region of the BT is shown in FIG. Here 1
01 is a P emitter, 102 is an N base, 103 is a P base, 104 is an N source, 105 is a polysilicon gate buried in a trench, 106 is a gate oxide film, 107
Is an insulating oxide film, 108 is a source electrode, and 109 is a drain electrode.

This device is used to turn on and off the device current by the gate electrode in the state where a positive voltage is applied to the drain electrode. The operating principle is to apply zero or negative voltage to the gate electrode. In this state, the MOS channel 110 is off, the drain voltage is maintained by the depletion layer extending from the P base 103 to the N base 102, and the device current does not flow. Here, when a voltage higher than the threshold value is applied to the gate electrode, the MOS channel 110 turns on and the N source 104
At the same time that electrons are injected from N to N base 102, holes are injected from P emitter 101, and the device becomes conductive.
Next, when the gate electrode is set to zero or a negative potential again,
The MOS channel 110 is closed, the injection of electrons is stopped,
The device current turns off.

In FIG. 11, the P base 103 and the source electrode 1
The region 111 where 08 contacts is when the device current is turned off,
In addition to being necessary for discharging the holes accumulated inside the device, it is necessary for preventing the N source 104 from latching up due to the hole current. FIG. 12 is a plan view of the element surface from which the insulating oxide film 107 and the source electrode 108 have been removed, as viewed from above. For this purpose, the N source 104 is a ladder formed by the P base 103 (111) exposed on the surface. It is formed into a shape.

An example of the manufacturing method will be described with reference to FIG. 13. A P-emitter layer 101 is formed on the back surface of a N-type high-resistance wafer serving as an N-base 102, and a P base layer 103 and an N source layer 104 are formed on the front surface by photolithography. It is formed by an implantation process, a thermal diffusion process, etc. (13 (a)). Here, as shown in FIG. 12, the N source layer 104 is formed in a shape including a portion 112 where a trench groove will be formed later. Next, a trench groove 113 is formed in the center of the N source layer 104 by the reactive ion etching method (13 (b)).
After forming the trench groove, an appropriate process is performed, a gate oxide film is formed, and polysilicon that is a gate electrode is deposited so as to fill the trench groove (13 (c)). next,
Although not shown in the figure, after the area where the polysilicon is left on the surface side, such as the gate wiring area and the bonding pad, is protected by the photo-etching method, the polysilicon deposit other than the predetermined portion is anisotropically etched. It is removed by the reactive ion etching method. This is a process called an etch bag, and the element region is etched without being protected by the photo-etching method. By this etch back, the trench groove has a shape in which the upper portion thereof is filled with polysilicon (13 (d)). Next, a silicon oxide film, to which no impurities are added, is formed as an insulating film on the entire surface by chemical vapor deposition, and then a portion contacting with the cathode electrode is insulated from a region (not shown) where the gate electrode is taken out. The oxide film is selectively etched (13 (e)), and finally electrodes are formed on the front and back sides respectively, and the trench gate type I
GBT is obtained. (13 (f)).

[0006]

In the trench gate type IGBT manufactured by the above-described manufacturing method, the shape of the upper portion of the polysilicon filled in the trench groove is actually the same as that shown in FIG.
As shown in (f), when viewed in cross section, the central portion is shallow, and the shape becomes an acute angle toward the gate oxide films on both sides. This is because in the reactive ion etching method, since the amount of vertical etching is constant, polysilicon having an acute-angled side wall shape remains on the side wall portion which is the step portion of the trench groove. Therefore, there is a problem that cracks occur in the acute-angled polysilicon due to thermal stress during use of the device.

By the way, the above-mentioned trench gate type IGB
In the figure, T is, for example, a trench interval A of 10 μm,
The distance B from the trench end to the contact end is 2 μm, the distance C from the contact end to the N source end is 1 μm, and the P base length D exposed on the surface is 4 μm. Assuming that the trench width E is 1 μm, the N source width F may be formed to 7 μm in FIG. 13A.
Even if there is a um shift, the N source is 2u in the final element state.
Therefore, there is no particular problem in device characteristics.

However, this type of semiconductor element is required to have a small on-resistance when conducting a current, and one of the methods is to reduce the channel resistance of MOS.
The channel resistance is reduced by increasing the total length of the MOS channel. To increase the total length of the MOS channel in the same device area, it is necessary to reduce the trench interval A.
Therefore, for example, in FIG.
To obtain um, the distance B between the trench end and the contact end is 0.5 μm, and the distance C between the contact end and the N source end is 0.5 μm.
um, and the P base length D exposed on the surface must be 2 um. However, in this case, since the size is small, the allowable range of deviation with respect to a predetermined position at the time of forming the trench groove is remarkably small. For example, the N source width F in FIG. 8 is 3 μm. At that time, if the position shifts by 1 μm, the N source region on the side wall of the trench disappears in the completed element state, and MOS is not formed. Similarly, for example, when the trench groove is formed, the position is 0. 5um
If there is a deviation, the contact state between the N source and the cathode electrode becomes unbalanced between the left and right sides of the trench, and the current during conduction becomes uneven, which adversely affects the dynamic characteristics of the device. Therefore, in the device structure that requires a small trench interval, the above-mentioned ladder-shaped N source shape cannot be adopted, and actually, as shown in FIG. 9, a stripe-shaped N source shape orthogonal to the trench is adopted. I had to do it. In this case, the portion of the sidewall of the trench where the N source is not formed does not function as a vertical MOS transistor, so that MO
There is a problem that the total length of the S channel becomes smaller by that amount. Therefore, the present invention has been made in view of the above-mentioned problems, and provides a new insulated gate type semiconductor device which does not reduce the total length of a MOS channel.

[0009]

SUMMARY OF THE INVENTION One of the present invention is to eliminate the acute-angled shape of the upper portion of polysilicon, which is a gate electrode buried in a trench groove, from the so-called polysilicon upper end by making it arc-shaped. The present invention provides an insulated gate semiconductor device in which a silicon gate is not cracked and a method for manufacturing the same.

Further, according to the present invention, by depositing an insulating oxide film to which phosphorus is added on the upper surface of the polysilicon which becomes the gate electrode buried in the trench groove and the wiring region formed on the device surface, (EN) Provided is an insulated gate type semiconductor device which realizes a low resistance of silicon and does not cause a crack in the vicinity of a polysilicon gate or a silicon shoulder, and a manufacturing method thereof.

Further, the present invention uses an insulating oxide film to which phosphorus is added to reduce the resistance of polysilicon formed inside the trench groove (trench portion) and the wafer surface, and at the same time, phosphorus is added to the N source region. By forming the insulating oxide film as a source in a self-aligned manner, even in a trench gate type semiconductor device having a small trench interval, stable N
It is intended to provide a method for manufacturing an insulated gate semiconductor device capable of forming a source region.

[0012]

According to the present invention, it is possible to obtain an insulated gate semiconductor device in which cracks are not generated in the vicinity of the polysilicon gate and the silicon shoulder. Further, according to the present invention, the resistance of the polysilicon gate electrode is reduced, and at the same time, the formation of the N source region on both sides of the trench groove becomes suppurative in a self-aligned manner, which is stable even in a trench gate type semiconductor device having a small trench interval. It is possible to form the N source region.

[0013]

Embodiments of the present invention will be described by taking a trench gate type IGBT, which is a type of insulated gate type semiconductor device, as an example. FIG. 1 is a sectional view of an element region of a trench gate type IGBT showing an embodiment of the present invention. Here, 1 is a P emitter, 2 is an N base, 4 is an N source, 5 is a polysilicon gate buried in a trench, 6 is a gate oxide film, and 7 is a gate oxide film.
Is an insulating oxide film, 8 is a source electrode, and 9 is a drain electrode. Here, the shape of the trench side wall portion A above the polysilicon gate embedded in the trench groove (trench portion) is not sharp but rounded (arc-shaped). The polysilicon near the position A receives stress from the vicinity of the trench shoulder of the silicon substrate and the insulating oxide film 7, but the shape at the trench sidewall A is rounded rather than acute, which means that the device is in use. It is possible to obtain a trench gate structure having a high resistance to crack generation due to the thermal stress of.

Further, in FIG. 1, a silicon oxide film to which impurities are not intentionally added is usually used as the insulating oxide film 7, but as another embodiment, the insulating oxide film 7 is at least the lowest layer thereof. By using a silicon oxide film to which phosphorus is added, which has a stress relaxation effect, it becomes possible to obtain a trench gate type IGBT having a higher resistance to thermal stress.

The structure of the trench portion shown in FIG. 1 is different between (a) and (b), but it is different depending on the manufacturing method. In FIG. 1 (b), impurities are intentionally used as an insulating film. When a silicon oxide film not added is used, the N source layer 4 is used on the left side using a silicon oxide film to which phosphorus is added.
This is an example of a case in which is diffused by phosphorus in the oxide film.

Next, an example of a method of manufacturing a trench gate type IGBT as shown in FIG. 1A will be described with reference to FIG. FIGS. 2A to 2D up to the etching back of the polysilicon gate buried in the trench groove are the same as the above-described conventional example. The polysilicon after etching back by the reactive ion etching method is shown in FIG.
As shown in (d), it remains in a sidewall shape on the side wall portion of the upper portion of the trench groove serving as a step portion, and the tip shape is
It is sharp. Next, when the polysilicon is etched by a chemical dry etching method which is isotropic etching, the sidewall-shaped polysilicon on the sidewall of the trench groove is etched quickly because of its thin thickness, and as a result, the polysilicon gate upper portion is etched. The shape at the side wall of the trench is not an acute angle but an arc shape (FIG. 2E). Furthermore, if oxidation is performed after chemical dry etching of polysilicon, oxygen is supplied from both the gate oxide film and the oxidizing gas to the trench sidewalls above the polysilicon gate, so that a better rounded shape can be obtained. Therefore, it is desirable to perform oxidation. After that, the trench structure shown in FIG.
It becomes possible to obtain a trench gate type IGBT.

Next, in FIG. 3, as the insulating oxide film 7 on polysilicon, at least the lowermost layer thereof is a silicon oxide film (PSG) to which phosphorus is added, which tends to relieve stress.
An example of the production method of the present invention using a film will be described. In the above description of the manufacturing method of the present invention, the same applies up to the chemical dry etching of polysilicon or the subsequent polysilicon oxidizing step. afterwards,
N-type impurities are diffused only on the polysilicon upper surface embedded in the trench groove and on the polysilicon left on the element surface side such as a gate wiring region and a bonding pad (not shown) or in the region and the silicon surface. The oxide film on the desired region is selectively removed (FIG. 3A). Next, a phosphorus-added silicon oxide film (PSG film) 7 is deposited on the entire surface of the silicon wafer by, for example, vapor phase epitaxy (FIG. 3B). Next, for example, the PSG film is annealed by holding it at a high temperature in a nitrogen atmosphere. At this time, at the same time, the phosphorus in the PSG film is thermally diffused into the polysilicon and silicon which are in direct contact with the PSG film, so that the resistance of the polysilicon left in the upper part of the trench groove and the element surface side is reduced, and the silicon is also reduced. It is possible to selectively diffuse the N-type high concentration layer also on the front surface side. In the region where the N-type high concentration layer is not formed, phosphorus is not diffused by the gate oxide film existing between the silicon and the PSG film. After that, the trench gate type IGBT having the trench structure of FIG. 1B can be obtained by the same steps as the above-mentioned conventional example.

Another embodiment will be described. In the above description of the manufacturing method of the present invention, the same applies up to the chemical dry etching of polysilicon or the subsequent polysilicon oxidizing step. The oxide film on the silicon surface in the element region is peeled off from the polysilicon upper surface embedded in the groove, the polysilicon left on the element surface side such as the gate wiring region and the bonding pad (FIG. 4).
(A)). Next, a phosphorus-added silicon oxide film (PS
G film) is deposited on the entire surface of the silicon wafer by, for example, a vapor phase growth method. After that, the PSG film on the region where phosphorus is not diffused is selectively stripped (FIG. 4B), and is then held at a high temperature, for example, in a nitrogen atmosphere. Trench gate type IGBT as shown in FIG.
It is possible to obtain According to this method, since there is no PSG film on the region where the N-type high-concentration layer is not formed, a polysilicon gate having high crack resistance and low resistance can be obtained, and at the same time, the N-type high-concentration layer can be obtained in a self-aligned manner. It becomes possible. Although the N source layer is formed before the PSG film is deposited in FIGS. 3 and 4, it is not formed before the PSG film is deposited.
It is also possible to form it only by diffusing phosphorus from the SG film. This point will be described in detail in Examples described later.

FIG. 5 is a sectional view of an element region of a trench gate type IGBT showing another embodiment of the present invention. The shape of the trench side wall A above the polysilicon gate embedded in the trench groove is sharp. Instead, it is characterized by being rounded (having an arc shape). The difference from the embodiment of FIG. 1 is that the upper portion of the polysilicon 5 embedded in the trench groove is located inside the silicon substrate surface, and the upper portion is covered with the insulating film 7 to almost the same height as the substrate surface. That is, the source electrode 8 is formed substantially flat on the film 7 and the silicon substrate. In this case as well, the trench side wall portion A above the polysilicon gate receives stress from the vicinity of the trench shoulder of the silicon substrate and the insulating oxide film 7. However, according to the present invention, it is possible to obtain a trench structure having high resistance to stress. Further, as described above, if a silicon oxide film having phosphorus added to at least its lowermost layer is used as the insulating film 7, it is possible to obtain a trench structure having a higher resistance to stress. In this case, the PSG film may be formed by leaving the gate oxide film on the side wall of the trench like the trench of FIG. 5B, or the gate oxidation of the portion where the PSG film is embedded like the trench of FIG. 5A. It is also possible to peel off the film and bring the PSG film and silicon into direct contact with each other to use as a source of the N-type high concentration layer (N source layer). Further, as shown in FIGS. 6 (a) and 6 (b), the silicon substrate at the shoulder portion of the trench groove may be rounded (arcuate) like B, and in the case of FIG. 1, the silicon substrate may be rounded like B. May be attached (FIGS. 7A and 7B).

Next, as an example of the manufacturing method of the present invention, a manufacturing method of the trench gate type IGBT having the structure of FIG. 5 will be described. The process is the same as that of FIG. 2 until polysilicon is deposited on the trench groove and the wafer surface (FIG. 8A).
Then, by reactive ion etching, etching back is performed to a position where the upper portion of the polysilicon in the trench is inside the surface of the silicon substrate and shallower than the depth of the source layer. At this time, the polysilicon remains on the sidewalls of the trench in the shape of sidewalls. (FIG. 8B) Next, the sidewall-shaped polysilicon is removed by a chemical dry etching and oxidation process to form a roundness at the upper end thereof (FIG. 8C). After that, the upper part of the trench and the entire surface of the wafer are formed. An insulating oxide film 7 is deposited (FIG. 8 (d)), the oxide film is etched back to the wafer surface (FIG. 8 (e)), and then a metal electrode is formed to form the trench gate shown on the right side of FIG. It is possible to obtain a type IGBT.

Next, a silicon oxide film to which phosphorus is added is used as an insulating film, which is used to reduce the resistance of polysilicon, and
Another embodiment of the present invention in which the N source layer is formed by diffusion in a self-aligned manner will be described. After the P emitter layer 1 is formed on the back surface of the N-type high-resistance wafer that becomes the N base 2, the P of a depth of 2 μm is formed on the front surface.
The base layer 3 and the N source layer 4 having a depth of 0.5 μm are formed by photolithography, implantation, thermal diffusion, etc., respectively (FIG. 9A). FIG. 9B shows the wafer surface state at this time. Here, the N source layer 4 is formed so as to be perpendicular to the broken line a portion which will be a trench groove in the future, and the N source of the portion along the trench groove is formed. The layer is not formed, the P base layer 3 is exposed on the surface, and the bb ′ cross section is shown in FIG.
It is (a). Next, trenches having a width of 1 μm and a depth of 3 μm are formed at predetermined positions at predetermined intervals, for example, every 4 μm by the reactive ion etching method. Next, after depositing a gate oxide film and a polysilicon gate, a polysilicon gate having an upper portion located inside the wafer surface and rounded upper end sides is formed by the method described above. (Fig. 9
(C)). Note that FIG. 9C shows a cc ′ cross section in which the N source layer is not formed in FIG. 9B, and in the case of the present embodiment, the N source layer near the sidewall of the trench is polysilicon. Since the PSG film is formed by diffusion in a self-aligned manner, the margin for the positional deviation of the upper portion of the polysilicon at this point is not severe. Next, after removing the polysilicon and the oxide film on the surface of the element, an insulating oxide film 5 to which phosphorus is added is formed on the entire surface by a vapor phase epitaxy method. The insulating oxide film is left only in the region where the source layer is formed, and the insulating oxide film in the other regions is selectively stripped (FIG. 9D). At this time, the distance G from the trench end to the contact end is 0.5 μm. Next, for example, when annealing is performed for 30 minutes in a nitrogen atmosphere at 900 ° C., phosphorus is diffused in the polysilicon to realize a low resistance, and the phosphorus added to the insulating oxide film 7 is in contact. A source layer is diffused inward from the silicon surface along all side surfaces on both sides inside the trench groove, and at the same time, an N source layer is formed from the surface side as well. A source layer is formed. At this time, since phosphorus diffuses about 80% in the vertical direction in the horizontal direction as well, an N source layer is formed on the silicon surface from the edge of the insulating oxide film to about 0.4 μm, and on the trench sidewall, about 0% from the polysilicon upper portion. The N source layer is formed to a depth of 0.4 μm, and the vertical MOSFET is formed in a self-aligned manner (FIG. 9E). Therefore, the N source layer comes into contact with the cathode electrode only about 0.4 μm from the end of the insulating oxide film on the entire side surface of the trench groove, in addition to the ladder-shaped cross section.
There is no problem that the N source layer on one side of the trench groove is lost or the portion contacting the cathode electrode becomes unbalanced inside the element region due to the positional deviation when forming the trench groove as in the conventional case. Next, after performing an appropriate treatment, a cathode electrode and a drain electrode are formed, and as shown in FIG.
The trench gate type IGBT shown in (f) is obtained. In addition, in this embodiment, after the diffusion by the PSG film is finished,
When the PSG film on the element region is peeled off to a position on the wafer surface by etch back and then a cathode electrode and a drain electrode are formed after appropriate treatment, the upper portion of the polysilicon 5 embedded in the trench groove is a silicon substrate. It is located on the inside of the surface, the upper part thereof is covered with the insulating film 7 to almost the same height as the surface of the substrate, and the source electrode 8 is formed substantially flat on the insulating film 7 and the silicon substrate. A trench gate type IGBT is obtained.

FIG. 10 shows the surface plane of the IGBT of FIG. 9 (f) from which the electrodes and the insulating oxide film have been removed. Here, the completed N source region is formed in a ladder shape by a portion 4a formed by implantation and diffusion and a portion 4b formed by diffusion from an insulating oxide film to which phosphorus is added.

According to the present invention, when phosphorus in the insulating oxide film 7 is diffused, not only a uniform N source region is formed on all sidewalls of the trench groove, but also on the polysilicon gate inside the trench. Also phosphorus is diffused. This contributes to the reduction of the gate wiring resistance required for high-speed operation of the device, and is characterized in that two effects can be obtained at the same time in one process.

In the case of this embodiment, the N source layer along the trench groove is formed in a self-aligned manner using the phosphorus-doped insulating oxide film as a diffusion source. Even at the position, it is possible to form a uniform N source layer having the same depth, the shape of the portion in contact with the cathode electrode, and the same concentration. At the same time, the wiring resistance of the polysilicon gate can be reduced, and both sides of the trench can be realized. It is possible to obtain a trench gate type IGBT in which all sides are capable of MOS operation and the channel resistance of the MOS is small, and at the same time, the wiring resistance of the polysilicon gate is small and high-speed operation is possible, and the element characteristics do not vary.

If the N source layer formed before the trench is formed by using arsenic as a source, the diffusion depth of the portion formed by the insulating oxide film to which phosphorus is added is different from the finished diffusion depth due to the difference in thermal diffusion coefficient. It is possible to do the same.

The phosphorous-added insulating oxide film 7 described in the embodiment may be any phosphorous-added insulating oxide film at the lowermost layer in contact with silicon. The film may be deposited. The source layer is P
In the case of a mold, the present invention can be applied by using an insulating oxide film to which BORONN is added.
Further, the present invention can be applied to, for example, the manufacture of a power IC in which the power element region and the logic element region are integrally formed into one element, and the insulating oxide film 7 containing phosphorus is
By using it simultaneously as a sidewall insulating film when forming the LDD structure of the lateral MOS in another region in the element, the feature of the present invention can be realized without increasing the number of steps. The present invention is IGB
Although T has been described as an example, the present invention can be applied to other trench gate type devices where it is desired that the trench interval is small.

[0027]

As described above, according to the present invention,
Even in a trench gate type semiconductor device with a high crack resistance of the polysilicon embedded in the trench and a small trench interval, the concentration and shape are uniform on all side surfaces of the trench groove without being affected by misalignment during trench formation. Thus, it is possible to form the N-type source layer having the same contact state with the cathode electrode, and at the same time, it is possible to reduce the wiring resistance of the polysilicon gate.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining an embodiment of a semiconductor device of the present invention.

2A to 2D are process cross-sectional views for explaining one embodiment of the manufacturing method of the present invention.

FIG. 3 is a sectional view for explaining another embodiment of the semiconductor device of the present invention.

FIG. 4 is a sectional view for explaining another embodiment of the semiconductor device of the present invention.

FIG. 5 is a sectional view for explaining another embodiment of the semiconductor device of the present invention.

FIG. 6 is a sectional view for explaining another embodiment of the semiconductor device of the present invention.

FIG. 7 is a sectional view for explaining another embodiment of the semiconductor device of the present invention.

FIG. 8 is a process sectional view for explaining another embodiment of the manufacturing method of the present invention.

FIG. 9 is a view for explaining another embodiment of the manufacturing method of the present invention.

FIG. 10 is a plan view of FIG.

FIG. 11 is a diagram for explaining a conventional example.

FIG. 12 is a diagram for explaining a conventional example.

FIG. 13 is a diagram for explaining a conventional example.

[Explanation of symbols]

 1, 101 ... P-type emitter layer 2, 102 ... N-type base layer 3, 103 ... P-type base layer 4, 4a, 4b, 104 ... N-type source layer 5, 105 ... Polysilicon 6, 106 ... Gate insulating film 7 , 107 ... Insulating oxide film 8, 108 ... Cathode electrode 9, 109 ... Anode electrode

Claims (13)

[Claims] 1. In a trench gate type insulated gate semiconductor device in which a gate electrode is embedded in a trench portion provided in a semiconductor layer of one conductivity type, both ends of an upper portion of the gate electrode embedded in the trench portion are An insulated gate semiconductor device having an arc shape. 2. The shoulder opening of the semiconductor layer of the trench portion is formed in an arc shape.
The insulated gate semiconductor device described. 3. The upper portion of the gate electrode embedded in the trench portion is located inward of the surface of the semiconductor substrate, and the upper portion of the gate electrode is covered with an insulating film up to approximately the same height as the surface of the semiconductor substrate. 2. The insulated gate semiconductor device according to claim 1, wherein the source electrode metal is laminated on the surface of the semiconductor substrate. 4. An insulated gate semiconductor device of a trench gate type in which a gate electrode is embedded in a trench portion provided in a semiconductor layer of one conductivity type, and an element above the gate electrode embedded in the trench portion and an element. An insulated gate semiconductor device, wherein the upper surface of the gate electrode other than the gate bonding pad portion on the surface is in direct contact with the phosphorus-doped insulating oxide film. 5. The insulated gate semiconductor device according to claim 4, wherein the semiconductor layer near the shoulder of the trench is in direct contact with the phosphorus-doped insulating oxide film. 6. A step of forming a predetermined diffusion layer on a semiconductor substrate, a step of selectively forming a trench groove, a step of treating a side wall of the trench groove, and a step of forming an insulating film to be a gate film, A step of filling the inside of the trench groove and depositing a gate electrode material also on the surface of the semiconductor substrate; an unnecessary semiconductor substrate surface portion; a step of removing the gate electrode material to a predetermined depth of the trench groove; Insulation comprising: a step of rounding the upper part of the gate electrode; a step of filling the upper part of the trench groove and forming an insulating film also on the surface of the semiconductor substrate; and a step of selectively forming a contact hole. Method of manufacturing gate type semiconductor device. 7. The step of rounding is a step of anisotropically etching the gate electrode material and a step of anisotropically etching the gate electrode material remaining on the upper wall of the trench groove. A method of manufacturing an insulated gate semiconductor device according to claim 1. 8. The method for manufacturing an insulated gate semiconductor device according to claim 6, wherein the insulating film filling the upper portion of the trench groove and formed also on the surface of the semiconductor substrate is an insulating oxide film to which phosphorus is added. . 9. A step of forming a predetermined diffusion layer on a semiconductor substrate, a step of selectively forming a trench groove, a step of treating a sidewall of the trench groove, a step of forming an insulating film to be a gate film, and a trench. A step of filling the inside of the groove and depositing a gate electrode material also on the semiconductor substrate surface; an unnecessary semiconductor substrate surface portion; and a step of removing the gate electrode material from the semiconductor substrate surface above the trench groove to a predetermined position, A step of selectively peeling off the insulating film on the upper part of the gate electrode in the trench groove and on the gate electrode remaining on the element surface, and on the semiconductor substrate surface, or on the semiconductor substrate surface and the upper wall of the trench groove forming the source diffusion layer; , A step of filling an upper part of the trench groove and depositing an impurity-added insulating film which becomes a diffusion source of the source layer also on the surface of the semiconductor substrate, and it becomes a diffusion source by keeping it at a high temperature. And a step of diffusing impurities according to the present invention. 10. The method of manufacturing an insulated gate semiconductor device according to claim 9, wherein the insulating film to which an impurity serving as a diffusion source of the source layer is added is an insulating oxide film to which phosphorus is added. 11. A step of removing an unnecessary portion of the semiconductor substrate surface and a gate electrode material from the semiconductor substrate surface above the trench groove to the inside, and heat of the source layer from an insulating film doped with an impurity serving as a diffusion source. 10. The method according to claim 9, further comprising a step of etching the insulating film in the element region to the substrate surface after the diffusion step, and a step of forming the source electrode substantially flat on the substrate surface in the element region. Insulated gate type semiconductor device manufacturing method. 12. The method of manufacturing an insulated gate semiconductor device according to claim 9, further comprising the step of selectively forming a source layer in a direction perpendicular to the trench gate. 13. The method according to claim 9, further comprising the step of rounding an upper portion of the gate electrode inside the trench groove.
A method of manufacturing an insulated gate semiconductor device according to claim 1.