CN117497602B - Split gate trench MOSFET, preparation method thereof and chip - Google Patents

Split gate trench MOSFET, preparation method thereof and chip Download PDF

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CN117497602B
CN117497602B CN202311848200.8A CN202311848200A CN117497602B CN 117497602 B CN117497602 B CN 117497602B CN 202311848200 A CN202311848200 A CN 202311848200A CN 117497602 B CN117497602 B CN 117497602B
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CN117497602A (en
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贺俊杰
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Shenzhen Sirius Semiconductor Co ltd
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

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Abstract

The application belongs to the technical field of power devices and provides a split gate trench MOSFET, a preparation method and a chip thereof, wherein a drain electrode layer, an N-type substrate layer, a cubic silicon carbide doped layer, an N-type buffer layer and an N-type drift layer are arranged in a stacked mode, the N-type drift layer is of a concave structure, a split gate polysilicon layer and a control gate polysilicon layer are formed in a groove of the N-type drift layer, a first P well and a second P well are respectively formed above two side parts of the N-type drift layer, a first N-type source region and a second N-type source region are respectively formed on the first P well and the second P well, and the pressure-resistant breakdown voltage between a split gate and a drain electrode can be improved by utilizing the high-critical breakdown voltage of a cubic silicon carbide material, so that the breakdown voltage of the device is improved.

Description

Split gate trench MOSFET, preparation method thereof and chip
Technical Field
The application belongs to the technical field of power devices, and particularly relates to a split gate trench MOSFET, a preparation method thereof and a chip.
Background
The split gate trench (SHIELD GATE TRENCH, SGT) structure metal oxide semiconductor (Metal Oxide Semiconductor, MOS) device is widely used as a switching device in a power management system, and is a core power control component. The gate structure of the split gate trench MOSFET comprises a shielding polysilicon structure and a polysilicon gate structure which are positioned in the deep trench, wherein the shielding polysilicon structure is positioned at the lower part of the deep trench, and the polysilicon gate structure is positioned at the upper part of the deep trench. The shielding polysilicon structure, the polysilicon gate structure and the deep trench are isolated from each other. The top layer of the active region forms a channel region, and the surface layer of the epitaxial layer on the channel region forms the source region. The source electrode is connected with the source region through a contact hole, and a heavily doped contact region is formed around the bottom end of the contact hole for leading out the source electrode, and the heavily doped contact region is in contact with the channel region.
However, in the current split gate trench MOSFET, the oxide layer between the split gate and the drift region bears a larger voltage, so that the position determines the breakdown of the device, which results in SGTMOS being only suitable for medium-low voltage application scenarios, and greatly limits the application scenarios of SGTMOS devices.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the application provides a split gate trench MOSFET, a preparation method thereof and a chip, and aims to improve the breakdown voltage of a device.
A first aspect of an embodiment of the present application provides a split gate trench MOSFET, including: the semiconductor device comprises a drain electrode layer, an N-type substrate layer, a cubic silicon carbide doped layer, an N-type buffer layer, an N-type drift layer, a split gate polysilicon layer, a control gate polysilicon layer, a first P well, a second P well, a first N-type source region, a second N-type source region, a first P-type source region, a second P-type source region, a source electrode layer, a grid electrode layer and a grid electrode dielectric layer;
the drain electrode layer, the N-type substrate layer, the cubic silicon carbide doped layer, the N-type buffer layer and the N-type drift layer are stacked, and the N-type drift layer is of a concave structure; wherein the cubic silicon carbide doped layer is N-type doped;
the separation gate polysilicon layer and the control gate polysilicon layer are formed in the groove of the N-type drift layer, and the control gate polysilicon layer is formed above the separation gate polysilicon layer and is isolated from the separation gate polysilicon layer, the first P well, the second P well, the first N-type source region and the second N-type source region by the gate dielectric layer;
the first P well and the second P well are respectively arranged above two side parts of the N-type drift layer, and the first N-type source region and the second N-type source region are respectively arranged on the first P well and the second P well;
The first P-type doped region is formed between the first P-well and the source electrode layer, and the second P-type doped region is formed between the second P-well and the source electrode layer;
the grid electrode layer is contacted with the control grid polycrystalline silicon layer through a through hole on the grid electrode dielectric layer, and the source electrode layer is contacted with the first N-type source region and the second N-type source region.
In some embodiments, the thickness of the cubic silicon carbide doped layer is greater than the thickness of the N-type buffer layer.
In some embodiments, the ratio of the thickness of the cubic silicon carbide doped layer to the thickness of the N-type buffer layer is between 3:1 and 9:1.
In some embodiments, the N-type buffer layer is comprised of a germanium layer and a silicon layer.
In some embodiments, the ratio of the doping concentration of the N-type buffer layer to the doping concentration of the N-type drift layer is 3:5.
In some embodiments, the doping concentration of the N-type buffer layer increases gradually in a direction of the drain layer toward the source layer.
In some embodiments, the split gate trench MOSFET further comprises: the first N-type doped region and the second N-type doped region; the first N-type doped region and the second N-type doped region are respectively formed on two side walls of the groove of the N-type drift layer;
In some embodiments, the split gate trench MOSFET further comprises: and the P-type heavily doped layer is formed at the bottom of the groove of the N-type drift layer.
The second aspect of the embodiment of the application also provides a preparation method of the split gate trench MOSFET, which comprises the following steps:
Epitaxially growing a cubic silicon carbide layer on the front surface of the N-type substrate layer, and injecting N-type doping ions to form a cubic silicon carbide doping layer;
Forming an N-type buffer layer on the cubic silicon carbide doped layer, and performing N-type doped ion implantation to form an N-type drift layer after epitaxially growing a silicon material on the N-type buffer layer;
Etching the N-type drift layer to form a groove, filling a dielectric material in the groove of the N-type drift layer, etching to form a gate dielectric layer, and forming a separation gate polysilicon layer in the gate dielectric layer;
Continuously filling dielectric materials in the grooves of the N-type drift layer and forming a control gate polysilicon layer after etching treatment;
Forming a first P well and a second P well above two side parts of the N-type drift layer, and forming a first N-type source region and a second N-type source region on the first P well and the second P well respectively;
Etching partial areas of the first N-type source region and the second N-type source region, and injecting P-type doping ions into the partial areas of the first N-type source region and the second N-type source region to form a first P-type doping region and a second P-type doping region; the control gate polysilicon layer is isolated from the separation gate polysilicon layer, the first P well, the second P well, the first N type source region and the second N type source region by the gate dielectric layer; the first P-type doped region is formed between the first P-well and the source electrode layer, and the second P-type doped region is formed between the second P-well and the source electrode layer;
And forming a source electrode layer on the first N-type source region and the second N-type source region, and forming a drain electrode layer on the back surface of the N-type substrate layer.
The third aspect of the embodiment of the present application further provides a chip, which includes the split gate trench MOSFET according to any one of the embodiments above.
The embodiment of the application has the beneficial effects that: the semiconductor device comprises a drain electrode layer, an N-type substrate layer, a cubic silicon carbide doped layer, an N-type buffer layer and an N-type drift layer, wherein the N-type drift layer is in a concave structure, a separation gate polycrystalline silicon layer and a control gate polycrystalline silicon layer are formed in a groove of the N-type drift layer, a first P well and a second P well are formed above two side parts of the N-type drift layer respectively, a first N-type source region and a second N-type source region are formed on the first P well and the second P well respectively, and the cubic silicon carbide doped layer is formed between the separation gate polycrystalline silicon layer and the drain electrode layer, so that the high critical breakdown voltage of a cubic silicon carbide material can be utilized, the withstand voltage between the separation gate and the drain electrode is improved, and the purpose of improving the breakdown voltage of the device is achieved.
Drawings
Fig. 1 is a schematic structural diagram of a split gate trench MOSFET according to an embodiment of the present application;
Fig. 2 is a schematic structural diagram of a split gate trench MOSFET according to an embodiment of the present application;
Fig. 3 is a schematic structural diagram of a split gate trench MOSFET according to an embodiment of the present application;
Fig. 4 is a schematic flow chart of a method for manufacturing a split gate trench MOSFET according to an embodiment of the present application;
FIG. 5 is a schematic illustration of an embodiment of the present application after forming a cubic silicon carbide doped layer 140 on an N-type substrate layer 120;
FIG. 6 is a schematic diagram of an embodiment of the present application after forming an N-type buffer layer 150;
fig. 7 is a schematic diagram of an N-type drift layer 130 formed and etched according to an embodiment of the present application;
fig. 8 is a schematic diagram of a split gate polysilicon layer 310 and a control gate polysilicon layer 320 according to an embodiment of the present application;
fig. 9 is a schematic diagram of a first P-well 410, a second P-well 420, a first N-type source region 510, and a second N-type source region 520 according to an embodiment of the present application;
Fig. 10 is a schematic diagram of a source layer 610 and a drain layer 110 formed according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In the current split gate trench MOSFET, an oxide layer between a split gate and a drift region bears larger voltage, so that the position determines breakdown of the device, and SGTMOS is only suitable for medium-low voltage application scenes, and the application scenes of SGTMOS devices are greatly limited.
In order to solve the above technical problem, an embodiment of the present application provides a split gate trench MOSFET, as shown in fig. 1, where the split gate trench MOSFET includes: the semiconductor device comprises a drain layer 110, an N-type substrate layer 120, an N-type drift layer 130, a cubic silicon carbide doped layer 140, an N-type buffer layer 150, a split gate polysilicon layer 310, a control gate polysilicon layer 320, a first P-well 410, a second P-well 420, a first N-type source region 510, a second N-type source region 520, a first P-type source region 431, a second P-type source region 432, a source layer 610 and a gate dielectric layer 230.
In this embodiment, the drain layer 110, the N-type substrate layer 120, the cubic silicon carbide doped layer 140, the N-type buffer layer 150, and the N-type drift layer 130 are stacked, and the N-type drift layer 130 has a concave structure, and the split gate polysilicon layer 310 is formed in a groove of the N-type drift layer 130 and is isolated from the N-type drift layer 130 by the gate dielectric layer 230. The first P-well 410 and the second P-well 420 are respectively disposed above two sides of the N-type drift layer 130, and the first N-type source region 510 and the second N-type source region 520 are respectively disposed on the first P-well 410 and the second P-well 420. The control gate polysilicon layer 320 is formed over the split gate polysilicon layer 310, and the control gate polysilicon layer 320 is isolated from the split gate polysilicon layer 310, the first P-well 410, the second P-well 420, the first N-type source region 510, and the second N-type source region 520 by the gate dielectric layer 230. The first P-type doped region 431 is formed between the first P-well 410 and the source layer 610, and the second P-type doped region 432 is formed between the second P-well 420 and the source layer 610; the gate layer contacts the control gate polysilicon layer 320 through the via hole on the gate dielectric layer 230 and the source layer 610 contacts the first N-type source region 510 and the second N-type source region 520.
The cubic silicon carbide doped layer 140 may be formed by implanting N-type dopant ions into 3C-type silicon carbide, which is a structure having a cubic lattice in which silicon atoms and carbon atoms are composed in a ratio of 1:1. In this embodiment, in order to avoid the problem that the N-type drift layer 130 with thicker epitaxy directly on the 3C-type silicon carbide material causes more defects in the drift region, a layer of N-type buffer layer 150 may be formed on the 3C-type silicon carbide material, and in the process, an N-type drift region with higher quality may be obtained, and by forming the cubic silicon carbide doped layer 140 between the separation gate polysilicon layer 310 and the drain layer 110, the breakdown voltage between the separation gate and the drain may be improved by using the high critical breakdown voltage of the cubic silicon carbide material, thereby achieving the purpose of improving the breakdown voltage of the device.
In some embodiments, the thickness of the cubic silicon carbide doped layer 140 is greater than the thickness of the N-type buffer layer 150.
In some embodiments, the ratio of the thickness of the cubic silicon carbide doped layer 140 to the thickness of the N-type buffer layer 150 is between 3:1 and 9:1.
In some embodiments, N-type buffer layer 150 is composed of a germanium layer and a silicon layer.
In some embodiments, the ratio of the doping concentration of the N-type buffer layer 150 to the doping concentration of the N-type drift layer 130 is 3:5.
In some embodiments, the doping concentration of the N-type buffer layer 150 gradually increases in the direction of the drain layer 110 toward the source layer.
In some embodiments, referring to fig. 2, the split gate trench MOSFET further comprises: the first N-type doped region 121 and the second N-type doped region 122, the first N-type doped region 121 and the second N-type doped region 122 are respectively formed on two sidewalls of the groove of the N-type drift layer 130.
In some embodiments, referring to fig. 3, the split gate trench MOSFET further comprises: the P-type heavily doped layer 210, the P-type heavily doped layer 210 is formed at the bottom of the groove of the N-type drift layer 130.
In this embodiment, the cubic silicon carbide (Cubic Silicon Carbide, 3C-SiC) is a silicon carbide with a cubic crystal structure, and by disposing the P-type heavily doped layer 210 between the bottom of the N-type drift layer 130 with a concave structure and the separation gate polysilicon layer 310, a depletion layer can be formed at the bottom of the concave groove of the N-type drift layer 130, so as to reduce the peak electric field at the bottom of the separation gate polysilicon layer 310, and achieve the purpose of increasing the breakdown voltage of the device.
On the other hand, by forming the first N-type doped region 121 and the second N-type doped region 122 on two sides of the concave groove of the N-type drift layer 130, the first N-type doped region 121 and the second N-type doped region 122 are respectively located on two sides of the split gate polysilicon layer 310, and the first N-type doped region 121, the second N-type doped region 122 and the split gate polysilicon layer 310 are isolated by the gate dielectric layer 230, the shielding effect of the P-type heavily doped layer 210 can be assisted, so that the electric field distribution in the vertical direction is more uniform, and the stability of the breakdown voltage of the device is improved.
In one embodiment, the P-type heavily doped layer 210 may have a concave shape or a "U" shape, and may form a depletion layer at the bottom of the concave groove of the N-type drift layer 130, so as to reduce the peak electric field at the bottom of the split gate polysilicon layer 310, achieve the purpose of improving the breakdown voltage of the device, and also reduce the parasitic capacitance between the gate and the drain in the device, and reduce the switching loss.
In one embodiment, in the case that the shape of the P-type heavily doped layer 210 may be concave or "U" shaped, the split gate polysilicon layer 310 may extend into the grooves of the P-type heavily doped layer 210, and keep the same distance from the groove sidewalls of the P-type heavily doped layer 210 on both sides thereof, and the split gate polysilicon layer 310 is isolated from the groove sidewalls of the P-type heavily doped layer 210 on both sides thereof by the gate dielectric layer 230.
In one embodiment, the first N-type doped region 121 and the second N-type doped region 122 have the same height.
In this embodiment, the heights of the first N-type doped region 121 and the second N-type doped region 122 are the same, and a uniform electric field can be formed between two sidewalls of the concave groove of the N-type drift layer 130, so as to assist in shielding the P-type heavily doped layer 210 and improve the stability of the breakdown voltage of the device.
In one embodiment, the height of the split gate polysilicon layer 310 is less than the heights of the first and second N-type doped regions 121 and 122.
In this embodiment, after the voltage is applied to the gate layer, an electric field is generated between two sidewalls of the concave groove of the N-type drift layer 130, and the height of the split gate polysilicon layer 310 is set to be smaller than the heights of the first N-type doped region 121 and the second N-type doped region 122, so that the whole split gate polysilicon layer 310 is located in the electric field between two sidewalls of the concave groove of the N-type drift layer 130, and the shapes of the first N-type doped region 121 and the second N-type doped region 122 are designed according to the application scenario of the split gate trench MOSFET, so that the electric field between the first N-type doped region 121 and the second N-type doped region 122 is uniformly distributed.
For example, after the voltage is applied to the gate layer of the split gate trench MOSFET, the electric field intensity between the first N-type doped region 121 and the second N-type doped region 122 and the distance between the position and the control gate polysilicon layer 320 are related, so by designing the shapes of the first N-type doped region 121 and the second N-type doped region 122, the electric field between the first N-type doped region 121 and the second N-type doped region 122 is uniformly distributed, the breakdown voltage of the device can be stabilized within a specific voltage range, and the problem that the device is broken down at any time due to a smaller electric field or uneven electric field is avoided.
In one embodiment, the widths of the first N-type doped region 121 and the second N-type doped region 122 gradually increase from bottom to top.
In this embodiment, by setting the widths of the first N-type doped region 121 and the second N-type doped region 122 to gradually increase from bottom to top, a uniform electric field can be formed between two sidewalls of the concave groove of the N-type drift layer 130, thereby assisting in the shielding effect of the P-type heavily doped layer 210 and improving the stability of the breakdown voltage of the device.
In one embodiment, the first N-type doped region 121 and the second N-type doped region 122 have a trapezoid structure.
In this embodiment, by setting the first N-type doped region 121 and the second N-type doped region 122 to have a trapezoid structure, a uniform electric field can be formed between two sidewalls of the concave groove of the N-type drift layer 130, thereby assisting in the shielding effect of the P-type heavily doped layer 210 and improving the stability of the breakdown voltage of the device.
In one embodiment, the first N-type doped region 121 and the second N-type doped region 122 are disposed in parallel, and the heights of the first N-type doped region 121 and the second N-type doped region 122 are greater than the width of the P-type heavily doped layer 210.
In one embodiment, the concentration of the N-type doping element in the first N-type doped region 121 and the second N-type doped region 122 is at least 100 times that in the N-type drift layer 130.
In one embodiment, the concentration of the N-type doping element in the N-type substrate is greater than the concentration of the N-type doping element in the N-type drift layer 130 and less than the concentrations of the N-type doping elements in the first N-type doping region 121 and the second N-type doping region 122.
In one embodiment, by setting the concentration gradient of the N-type doping element in the first N-type doped region 121 and the second N-type doped region 122, a uniform electric field is formed between two sidewalls of the concave groove of the N-type drift layer 130, thereby assisting in the shielding effect of the P-type heavily doped layer 210 and improving the stability of the breakdown voltage of the device.
For example, in one embodiment, the doping concentration of the first N-type doped region 121 and the second N-type doped region 122 gradually increases in the direction approaching the control gate polysilicon layer 320, so that a uniform electric field is formed between two sidewalls of the concave groove of the N-type drift layer 130, thereby assisting in the shielding effect of the P-type heavily doped layer 210 and improving the stability of the breakdown voltage of the device.
In one embodiment, the concentration of the P-type doping element in the P-type heavily doped layer 210 is greater than the concentration of the P-type doping element in the first P-well 410 and the second P-well 420.
In one embodiment, the first N-type doped region 121 and the second N-type doped region 122 are respectively contacted with two ends of the P-type heavily doped layer 210.
In one embodiment, the width of the control gate polysilicon layer 320 is greater than the width of the split gate polysilicon layer 310.
In one embodiment, gate dielectric layer 230 may be silicon oxide or silicon nitride.
In one embodiment, the metal electrode materials used for the source layer 610 and the gate layer may be the same.
In one embodiment, the concentration of the P-type doping element in the P-type heavily doped layer 210 is at least 100 times the concentration of the P-type doping element in the first P-well 410 and the second P-well 420.
In one embodiment, the P-type doping element may be magnesium element, aluminum element, or the like.
In one embodiment, the concentration of the N-type doping element in the first N-type doped region 121 and the second N-type doped region 122 is at least 10 times that in the N-type drift layer 130, and the N-type doping element may be nitrogen or phosphorus.
The embodiment of the application also provides a preparation method of the split gate trench MOSFET, which is shown in FIG. 4, and comprises the following steps: step S100 to step S700.
In step S100, as shown in fig. 5, a cubic silicon carbide layer is epitaxially grown on the front surface of the N-type substrate layer 120, and N-type dopant ions are implanted to form a cubic silicon carbide doped layer 140.
In step S200, as shown in fig. 6, an N-type buffer layer 150 is formed on the cubic silicon carbide doped layer 140, and an N-type drift layer 130 is formed by performing N-type doping ion implantation after epitaxially growing a silicon material on the N-type buffer layer 150, as shown in fig. 7.
In this embodiment, a germanium layer may be grown on the cubic silicon carbide doped layer 140 as a buffer layer between the silicon material and the silicon carbide material, and N-type dopant ions may be implanted to form an N-type buffer layer 150.
In some embodiments, the N-type buffer layer may be composed of a germanium layer and a silicon layer, which may be alternately stacked, and the germanium layer and the silicon layer are implanted with N-type doping ions.
In step S300, etching the N-type drift layer to form a groove, filling a dielectric material in the groove of the N-type drift layer, etching to form a gate dielectric layer, and forming a split gate polysilicon layer in the gate dielectric layer.
In this embodiment, as shown in fig. 7, the N-type drift layer 130 may be grown on the front surface of the N-type buffer layer 150 by an epitaxial growth process, and the N-type drift layer 130 is etched to form the recess 131, thereby forming the N-type drift layer 130 with a concave structure. As shown in fig. 8, a dielectric material is filled in the recess 131 of the N-type drift layer 130 and etched to form a gate dielectric layer 230, and a split gate polysilicon layer 310 is formed in the gate dielectric layer 230.
In step S400, as shown in fig. 8, the control gate polysilicon layer 320 is formed after the recess of the N-type drift layer 130 is filled with a dielectric material and etched.
In step S500, as shown in fig. 9, a first P-well 410 and a second P-well 420 are formed over both sides of the N-type drift layer 130, and a first N-type source region 510 and a second N-type source region 520 are formed on the first P-well 410 and the second P-well 420, respectively.
In step S600, as shown in fig. 10, partial regions of the first N-type source region 510 and the second N-type source region 520 are etched, and P-type doping ions are implanted into the partial regions of the first N-type source region 510 and the second N-type source region 520 to form a first P-type doped region 431 and a second P-type doped region 432.
The control gate polysilicon layer 320 is isolated from the split gate polysilicon layer 310, the first P-well 410, the second P-well 420, the first N-type source region 510, and the second N-type source region 520 by the gate dielectric layer 230.
In step S700, a source layer 610 is formed on the first N-type source region 510 and the second N-type source region 520, and a drain layer 110 is formed on the back surface of the N-type substrate layer 120.
In the present embodiment, a first P-type doped region 431 is formed between the first P-well 410 and the source layer 610, and a second P-type doped region 432 is formed between the second P-well 420 and the source layer 610.
In some embodiments, the first P-type doped region 431 and the second P-type doped region 432 are L-shaped, the first P-well 410 is connected to the source layer 610 by the first P-type doped region 431, and the second P-well 420 is connected to the source layer 610 by the second P-type doped region 432.
In some embodiments, the concentration of P-type dopant ions in the first P-type doped region 431 is at least 10 times that in the first P-well 410.
In some embodiments, the concentration of P-type dopant ions in the second P-type doped region 432 is at least 10 times the concentration of P-type dopant ions in the second P-well 420.
In some embodiments, P-type doped ions may be implanted into the bottom of the recess 131 through an ion implantation process, thereby forming a P-type heavily doped layer 210, and the first N-type doped region 121 and the second N-type doped region 122 are respectively formed on two sidewalls of the recess of the N-type drift layer 130 through oblique ion implantation.
In one embodiment, N-type doping ions may be implanted into both sidewalls of the recess 131 of the N-type drift layer 130 through an inclined ion implantation process, so that the first and second N-type doping regions 121 and 122 are formed to be in contact with the P-type heavily doped layer 210.
In some embodiments, the gate dielectric layer 230 may be formed on the sidewall of the recess by filling a dielectric material in the recess of the N-type drift layer 130 and etching to remove the dielectric material in the center, and then filling a gate polysilicon material to form the split gate polysilicon layer 310, where the split gate polysilicon layer 310 is isolated from the first N-type doped region 121 and the second N-type doped region 122 by the gate dielectric layer 230.
In one embodiment, the recess of the N-type drift layer 130 may also be oxidized by an oxidation process to form a silicon oxide layer as the gate dielectric layer 230.
In some embodiments, the first and second N-type source regions 510 and 520 may be formed by implanting P-type dopant ions over the two sides of the N-type drift layer 130, forming the first and second P-wells 410 and 420 over the two sides of the N-type drift layer 130, and continuing to implant N-type dopant ions over the two sides of the N-type drift layer 130. The energy of the N-type dopant ions injected when forming the first and second N-type source regions 510, 520 is smaller than the energy of the P-type dopant ions injected when forming the first and second P-wells 410, 420, such that the first and second N-type source regions 510, 520 are formed on the first and second P-wells 410, 420, respectively.
In some embodiments, the gate dielectric layer 230 may be formed above the split gate polysilicon layer 310 by a dielectric material filling and etching method or an oxidation process after the split gate polysilicon layer 310 is formed, and the control gate polysilicon layer 320 is formed after the N-type drift layer 130 is filled with a dielectric material and etched, where the control gate polysilicon layer 320 is isolated from the split gate polysilicon layer 310, the first P-well 410, the second P-well 420, the first N-type source region 510, and the second N-type source region 520 by the gate dielectric layer 230.
In one embodiment, the dielectric material may be a silicon nitride material or a silicon oxide material.
In some embodiments, source layers 610 are formed on the first and second N-type source regions 510, 520, respectively, and the gate layer is in contact with the control gate polysilicon layer 320 through a via hole on the gate dielectric layer 230.
The embodiment of the application also provides a chip, which comprises the split gate trench MOSFET prepared by the preparation method of the split gate trench MOSFET.
In this embodiment, the chip includes a chip substrate, and one or more split gate trench MOSFETs are disposed on the substrate, where the split gate trench MOSFETs may be manufactured by the manufacturing method in any of the above embodiments, or the split gate trench MOSFETs in any of the above embodiments may be disposed on the chip substrate.
In one embodiment, other related semiconductor devices may also be integrated on the chip substrate to form an integrated circuit with the split gate trench MOSFET.
In one specific application embodiment, the chip may be a switching chip or a driving chip.
The embodiment of the application has the beneficial effects that: the semiconductor device comprises a drain electrode layer, an N-type substrate layer, a cubic silicon carbide doped layer, an N-type buffer layer and an N-type drift layer, wherein the N-type drift layer is in a concave structure, a separation gate polycrystalline silicon layer and a control gate polycrystalline silicon layer are formed in a groove of the N-type drift layer, a first P well and a second P well are formed above two side parts of the N-type drift layer respectively, a first N-type source region and a second N-type source region are formed on the first P well and the second P well respectively, and the cubic silicon carbide doped layer is formed between the separation gate polycrystalline silicon layer and the drain electrode layer, so that the high critical breakdown voltage of a cubic silicon carbide material can be utilized, the withstand voltage between the separation gate and the drain electrode is improved, and the purpose of improving the breakdown voltage of the device is achieved.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of each doped region and device is illustrated, and in practical application, the above-described function allocation may be performed by different doped regions and devices according to needs, i.e. the internal structure of the device is divided into different doped regions, so as to perform all or part of the above-described functions. The doped regions and the devices in the embodiments can be integrated in one unit, or each unit can exist alone physically, or two or more units can be integrated in one unit.
In addition, the specific names of the doped regions and the devices are only used for distinguishing the doped regions and the devices from each other, and are not used for limiting the protection scope of the application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
In addition, each doped region in the embodiments of the present application may be integrated in one unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (10)

1. A split gate trench MOSFET, the split gate trench MOSFET comprising: the semiconductor device comprises a drain electrode layer, an N-type substrate layer, a cubic silicon carbide doped layer, an N-type buffer layer, an N-type drift layer, a split gate polysilicon layer, a control gate polysilicon layer, a first P well, a second P well, a first N-type source region, a second N-type source region, a first P-type source region, a second P-type source region, a source electrode layer, a grid electrode layer and a grid electrode dielectric layer;
the drain electrode layer, the N-type substrate layer, the cubic silicon carbide doped layer, the N-type buffer layer and the N-type drift layer are stacked, and the N-type drift layer is of a concave structure; wherein the cubic silicon carbide doped layer is N-type doped;
the separation gate polysilicon layer and the control gate polysilicon layer are formed in the groove of the N-type drift layer, and the control gate polysilicon layer is formed above the separation gate polysilicon layer and is isolated from the separation gate polysilicon layer, the first P well, the second P well, the first N-type source region and the second N-type source region by the gate dielectric layer;
the first P well and the second P well are respectively arranged above two side parts of the N-type drift layer, and the first N-type source region and the second N-type source region are respectively arranged on the first P well and the second P well;
A first P-type doped region is formed between the first P-well and the source electrode layer, and a second P-type doped region is formed between the second P-well and the source electrode layer;
the grid electrode layer is contacted with the control grid polycrystalline silicon layer through a through hole on the grid electrode dielectric layer, and the source electrode layer is contacted with the first N-type source region and the second N-type source region.
2. The split gate trench MOSFET of claim 1 wherein the thickness of the cubic silicon carbide doped layer is greater than the thickness of the N-type buffer layer.
3. The split gate trench MOSFET of claim 2 wherein the ratio of the thickness of the cubic silicon carbide doped layer to the thickness of the N-type buffer layer is between 3:1 and 9:1.
4. The split gate trench MOSFET of claim 1 wherein the N-type buffer layer is comprised of a germanium layer and a silicon layer.
5. The split gate trench MOSFET of claim 1 wherein the ratio of the doping concentration of the N-type buffer layer to the doping concentration of the N-type drift layer is 3:5.
6. The split gate trench MOSFET of claim 1 wherein the doping concentration of the N-type buffer layer increases gradually in a direction from the drain layer to the source layer.
7. The split gate trench MOSFET of claim 1, further comprising: the first N-type doped region and the second N-type doped region; the first N-type doped region and the second N-type doped region are respectively formed on two side walls of the groove of the N-type drift layer.
8. The split gate trench MOSFET of claim 1, further comprising: and the P-type heavily doped layer is formed at the bottom of the groove of the N-type drift layer.
9. A method of fabricating a split gate trench MOSFET comprising:
Epitaxially growing a cubic silicon carbide layer on the front surface of the N-type substrate layer, and injecting N-type doping ions to form a cubic silicon carbide doping layer;
Forming an N-type buffer layer on the cubic silicon carbide doped layer, and performing N-type doped ion implantation to form an N-type drift layer after epitaxially growing a silicon material on the N-type buffer layer;
Etching the N-type drift layer to form a groove, filling a dielectric material in the groove of the N-type drift layer, etching to form a gate dielectric layer, and forming a separation gate polysilicon layer in the gate dielectric layer;
Continuously filling dielectric materials in the grooves of the N-type drift layer and forming a control gate polysilicon layer after etching treatment;
Forming a first P well and a second P well above two side parts of the N-type drift layer, and forming a first N-type source region and a second N-type source region on the first P well and the second P well respectively;
Etching partial areas of the first N-type source region and the second N-type source region, and injecting P-type doping ions into the partial areas of the first N-type source region and the second N-type source region to form a first P-type doping region and a second P-type doping region; the control gate polysilicon layer is isolated from the separation gate polysilicon layer, the first P well, the second P well, the first N type source region and the second N type source region by the gate dielectric layer;
forming a source electrode layer on the first N-type source region and the second N-type source region, and forming a drain electrode layer on the back surface of the N-type substrate layer; the first P-type doped region is formed between the first P-well and the source electrode layer, and the second P-type doped region is formed between the second P-well and the source electrode layer.
10. A chip comprising a split gate trench MOSFET as claimed in any one of claims 1 to 8; or a split gate trench MOSFET prepared by the method of preparing a split gate trench MOSFET as claimed in claim 9.
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CN103258721A (en) * 2012-02-16 2013-08-21 住友电气工业株式会社 Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device
CN116344346A (en) * 2023-04-14 2023-06-27 飞锃半导体（上海）有限公司 Semiconductor structure and forming method thereof
CN116741837A (en) * 2023-05-25 2023-09-12 天狼芯半导体(成都)有限公司 Stepped grid silicon carbide MOSFET, preparation method thereof and chip
CN116759454A (en) * 2023-05-25 2023-09-15 天狼芯半导体(成都)有限公司 Silicon carbide trench MOSFET, preparation method thereof and chip

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103258721A (en) * 2012-02-16 2013-08-21 住友电气工业株式会社 Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device
CN116344346A (en) * 2023-04-14 2023-06-27 飞锃半导体（上海）有限公司 Semiconductor structure and forming method thereof
CN116741837A (en) * 2023-05-25 2023-09-12 天狼芯半导体(成都)有限公司 Stepped grid silicon carbide MOSFET, preparation method thereof and chip
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