JP2001085687A - Silicon carbide semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a recrystallization and activation heat treatment technique which changes an ion implanted region into a single crystal type and to enhance the breakdown strength of a silicon carbide semiconductor device. SOLUTION: P-type impurities are implanted at an acceleration energy of 1 MeV or higher. After that, a heat treatment is executed by a laser. Thereby, the implanted impurities are activated, and p- type base regions 3a, 3b are recrystallized. For example, by an excimer laser, the laser is irradiated sequentially toward upper-side ends from lower-side ends of the p- type base regions 3a, 3b. Thereby, the crystal type of an n+ type epitaxial layer 2 which is situated under the p- type base regions 3a, 3b is made to succeed, and the p- type base regions 3a, 3b are formed to be of the same crystal type. Consequently, the breakdown strength of the silicon carbide semiconductor device is enhanced more than in a case in which the central part of the p- type base regions 3a, 3b is formed of 3C-SiC.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device and a method of manufacturing the same, and more particularly, to an insulated gate field effect transistor, particularly a vertical power MOSF for high power.
It is about ET.

[0002]

2. Description of the Related Art Conventionally, a planar type MOSFET disclosed in JP-A-10-308510 is known.

FIG. 8 shows a cross-sectional view of this planar type MOSFET. The structure of the planar MOSFET will be described with reference to FIG.

An n ⁺ -type silicon carbide semiconductor substrate (hereinafter referred to as an n ⁺ -type substrate) 1 has an upper surface as a main surface 1a and a lower surface opposite to the main surface as a back surface 1b. This n ⁺ type substrate 1
Is formed on main surface 1a of n ⁻ -type silicon carbide epitaxial layer (hereinafter referred to as n ⁻⁾ having a dopant concentration lower than that of substrate 1.
2 (referred to as a mold epi layer).

[0005] n^-Region in the surface layer portion of the mold epi layer 2
Has a predetermined depth p^--Type silicon carbide base region 3a
And p^--Type silicon carbide base region 3b (hereinafter, p^-Type
Source regions 3a and 3b) are formed apart from each other.
You. Also, p^-Predetermined at the surface portion of the mold base region 3a
The region contains p^-N shallower than mold base region 3a⁺Mold saw
Region 4a also has p^-On the surface of the mold base region 3b
The predetermined area in the ^-Shallower than mold base region 3b
n⁺The mold source regions 4b are respectively formed.

Further, the n ⁻ type epi layer 2 and the p ⁻ layer between the n ⁺ type source region 4a and the n ⁺ type source region 4b are provided.
An n ^-- type SiC layer 5 composed of an n ^-- type layer 5a and an n ⁺ -type layer 5b extends on the surface of the mold base regions 3a and 3b. That is, the n ⁻ -type SiC layer 5 is arranged so as to connect the source regions 4a, 4b and the n ⁻ -type epi layer 2 on the surface portions of the p ⁻ -type base regions 3a, 3b. This n ^- type S
The iC layer 5 functions as a channel forming layer on the device surface during device operation. Hereinafter, n ⁻ -type SiC layer 5 is referred to as a surface channel layer.

Type base region 3a, n located on the top of 3b ^{- -} [0007] p of the surface channel layer 5 dopant concentration type layer 5a ^{is, 1 × 10 15 cm -3 ~1} × 10 17 cm -3 of about The concentration is low and is lower than the dopant concentration of the n ⁻ -type epi layer 2 and the p ⁻ -type base regions 3a and 3b. Thereby, low on-resistance is achieved.

Further, the p ^- type base regions 3a, 3b, n ⁺
Concave portions 6a and 6b are formed in the surface portions of the mold source regions 4a and 4b.

A gate insulating film (silicon oxide film) 7 is formed on the upper surface of the surface channel layer 5 and the upper surfaces of the n ⁺ type source regions 4a and 4b. Further, a gate electrode 8 is formed on the gate insulating film 7. Gate electrode 8 is covered with insulating film 9. LTO (L
(Operating Temperature Oxide) film. A source electrode 10 is formed thereon, and the source electrode 10 has n ⁺ type source regions 4a, 4b and p ⁻
It is in contact with the mold base regions 3a, 3b. Further, a drain electrode layer 11 is formed on the back surface 1b of the n ⁺ type substrate 1.

The on-resistance is reduced by operating in the storage mode configured as described above and improving the channel mobility.

[0011]

On the other hand, there is a demand for a higher breakdown voltage as a power device. For this reason,
In the off state, it is necessary to always maintain the off state even when a drain voltage is applied. In particular, when a drain voltage of several hundred volts or more is applied, the drain voltage becomes the reverse bias of the PN junction formed by the n ⁻ -type epi layer (drift region) 2 and the p ⁻ -type base regions 3a and 3b. It is held in the state. Therefore,
The above demands are made on the n ⁻ -type epi layer 2 and the p ⁻ -type base region 3.
a, 3b are provided thickly or the p ⁻ type base region 3
A and 3b are achieved by increasing the doping concentration instead of increasing the layer thickness.

Here, in order to increase the thickness of the p ^- type base regions 3a and 3b, the diffusion coefficient of the impurity in the SiC is set to S.
Since it is one to two orders of magnitude smaller than i and cannot utilize thermal diffusion of impurities such as Si, an ion implantation technique with high acceleration energy of about several MeV is required. FIGS. 9A to 9C show steps of forming the p ⁻ -type base regions 3 a and 3 b by this ion implantation technique.

After the ion implantation as shown in FIG. 9A, a heat treatment for recrystallization and activation of the implanted ion species is performed in the range of 1000 to 1800 ° C. in SiC. . Therefore, when the ion implantation region becomes thicker,
At the time of heat treatment for recrystallization and activation, as shown by arrows in FIG. 9B, the upper and lower portions of the ion-implanted layer inherit the crystal form of the adjacent layer, but at the center portion, as shown in FIG. As shown in (c), 3C—SiC having a stable structure is formed at 1000 to 1800 ° C., and it is difficult to form the entire ion-implanted region into a single crystal form. In particular,
When 6H, 4H-SiC is used for the substrate, the crystal form (Pol) of the substrate is near the boundary between the ion-implanted region and the substrate.
The crystal structure inherits y-type), but becomes 3C-SiC which is thermally stable at the center of the ion implantation region. As described above, when the 3C-SiC is formed, the band gap becomes narrow at the portion where the 3C-SiC is formed, and
There is a problem that the breakdown voltage of the FET is reduced. In addition, crystal defects may accumulate at the interface with a portion having a different crystal form, and the breakdown voltage of the MOSFET may be further reduced.

The present invention has been made in view of the above points, and provides a recrystallization and activation heat treatment technique for forming an ion-implanted region into a single crystal form in forming a high withstand voltage structure to reduce the withstand voltage of a silicon carbide semiconductor device. The purpose is to improve.

[0015]

To achieve the above object, according to the first aspect of the present invention, a base region (3) is provided.
a, 3b) In the forming step, the impurity of the second conductivity type is 1 MeV
The method is characterized by including a step of implanting with the above-described acceleration energy and a step of performing heat treatment with a laser to activate the implanted impurities and recrystallize the base regions (3a, 3b).

As described above, when the base region is deeply implanted, the heat treatment is performed by the laser, and the base region is recrystallized, so that the heat treatment can be performed directly by the laser. The formation of the same polymorph can be prevented by preventing the crystal form. Thereby, the breakdown voltage of the silicon carbide semiconductor device can be improved.

According to the second aspect of the present invention, in the laser heat treatment step, the base regions (3a, 3b) are sequentially arranged from the lower end to the upper end, or from the upper end to the lower end. It is characterized by performing laser irradiation.

Thus, the crystal form of the portion in contact with the base region from below or above the base region can be inherited, and the entire base region can be formed in that crystal form.

For example, in the laser heat treatment step, the heat treatment can be performed in such a manner that the heat treatment is performed at the condensing portion where the laser is condensed. Further, as described in claim 4, in the laser heat treatment step, laser irradiation may be performed so that a plurality of lasers cross each other, and heat treatment may be performed at a portion where the lasers cross.

More specifically, an excimer laser can be used as the laser. And when silicon carbide is interposed in the upper part of the base region,
As described in claim 6, the wavelength of the excimer laser is uniquely determined by λ = λ from the energy of the band gap of the silicon carbide.
Energy is absorbed in a region where heat treatment is desired by making the wavelength longer than the wavelength obtained from the expression of 1239.9 / Eg (eV) and by making the wavelength absorbed by the portion which is made amorphous by ion implantation. Can be done.
This is because the band gap becomes smaller than the band gap of a single crystal when it is made amorphous.

Further, as a laser, any one of a He-Cd laser, a He-Ne laser and an Ar + laser can be used as the laser. Since these lasers have a wavelength narrower than the band gap of 4H-SiC,
This is particularly effective when 4H—SiC is arranged on the base region. Further, in a case where an X-ray is used instead of a laser beam, the present invention is also applicable to the case where an X-ray is used.
The same can be said.

Further, any one of an electron beam, a neutron beam and a positron beam can be used in place of the laser.

In this case, since neutrons and the like are injected until they collide with the atoms, the neutrons collide with the amorphous base region, and the base region can be heat-treated.

According to the first to ninth aspects of the present invention, as described in the ninth aspect, the base regions (3a, 3b) have a thickness of 1 μm or more, and are all in contact with the semiconductor substrate (1). A silicon carbide semiconductor device having the same polymorphism is formed.

The reference numerals in parentheses of the above means indicate the correspondence with specific means described in the embodiments described later.

[0026]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 1 is a cross-sectional view of a normally-off n-channel planar MOSFET (vertical power MOSFET) according to the present embodiment. This device is
It is suitable when applied to a rectifier of an inverter or a vehicle alternator.

The structure of the vertical power MOSFET will be described with reference to FIG. However, the vertical power MOSFET in this embodiment is the same as the MOSFET shown in FIG.
Since it has a structure similar to that of T, only different parts will be described. Note that, in the vertical power MOSFET of the present embodiment, the same portions as those of the MOSFET shown in FIG. 8 are denoted by the same reference numerals.

In the MOSFET of this embodiment, p
^- type base region 3a, the acceleration energy 3b 1～8M
It is formed by ion implantation of eV. In contrast, in MOSFET shown in FIG. 8, p ^- type base region 3a, 3
Since b is formed at 1 MeV or less, the MOSFET according to the present embodiment is thicker than the MOSFET shown in FIG. Specifically, in the present embodiment,
When Al is used as the dopant, the layer thickness of the p ⁻ -type base regions 3a and 3b is about 4 μm, and when B (boron) is used, it is about 6 μm.

The MOSFET according to the present embodiment
In this case, all the p ⁻ -type base regions 3a and 3b have the same po
has a ly-type crystal form (for example, 4H),
It inherits the crystal form of n − -type epi layer 2 located below p ⁻ -type base regions 3a and 3b.

As described above, the p ⁻ -type base regions 3a and 3b are all formed in the same crystal form. When 3C-SiC having a different crystal form is formed at the center position of p ⁻ -type base regions 3a and 3b as in the related art, the band gap at that part becomes narrower, and the interface with a part having a different crystal form is formed. MOSF because crystal defects accumulate in
Although the withstand voltage of the ET decreases, such a problem can be eliminated in the present embodiment.

Next, the vertical power MOSFET shown in FIG.
Will be described with reference to FIGS.

[Step shown in FIG. 2A] First, n-type 4H
Alternatively, a 6H or 3C-SiC substrate, that is, an n ⁺ type substrate 1 is prepared. Here, the n ⁺ type substrate 1 has a thickness of 4
The main surface 1a is a (0001) Si plane or a (112-0) a plane. Main surface 1 of this substrate 1
A 5 μm-thick n ⁻ -type epi layer 2 is epitaxially grown on a. In this example, the n ⁻ -type epi layer 2 has the same crystal as that of the underlying substrate 1 and has n-type 4H or 6H or 3C-Si.
It becomes the C layer.

[Step shown in FIG. 2B] n ^- type epi layer 2
(Molybdenum) film 20 is arranged in a predetermined region above the
Using this as a mask, B ⁺ (or aluminum) ions are implanted to form p ⁻ -type base regions 3a and 3b. The ion implantation condition at this time is that the acceleration energy is 1
Up to 8 MeV, at a temperature of 700 ° C., and at a dose of 1 × 10 ¹⁶
cm ^-2 . For this reason, when Al is used as a dopant, the layer thickness of the p ⁻ -type base regions 3a and 3b is about 4 μm, and when B (boron) is used, it is about 6 μm.
μm.

Thereafter, recrystallization and activation heat treatment steps for p ⁻ -type base regions 3a and 3b are performed. The state of this step will be described with reference to FIG. First, at the time when the above-described ion implantation is performed, ions are implanted into the p ⁻ -type base regions 3a and 3b from the surface of the n ⁺ -type substrate 1 to a position at a predetermined depth, as shown in FIG. The ion-implanted portion is in an amorphous state (indicated by dots in the figure). This amorphous p ^- type base region 3
A heat treatment as shown in FIG.

In this heat treatment step, heat treatment is performed using a laser. An excimer laser whose laser wavelength can be adjusted is used as this laser. The wavelength of the excimer laser is set to be longer than the wavelength determined by the band gap of 4H-SiC. This is because if the laser wavelength is shorter than the band gap of 4H-SiC, the energy of the laser is absorbed by 4H-SiC interposed in the upper layer than the amorphous p ^- type base regions 3a and 3b. . Although FIG. 2B shows that the p ⁻ -type base regions 3a and 3b are formed from the surface of the n ⁺ -type substrate 1, actually, the p ⁻ -type base regions 3a and 3b have a predetermined depth from the surface. Since ions are implanted up to the position, 4H is formed above the p ⁻ -type base regions 3a and 3b.
-SiC will be interposed.

The laser beam 50 of this excimer laser is condensed by using a condensing lens 51, and only the condensing portion is arranged so as to be in an energy state suitable for heat treatment. As a result, the heat treatment proceeds only in the vicinity of the light collecting portion.

First, the condensing portion of the laser 50 is moved to the substrate side of the ion implantation region, that is, the p ^- type base regions 3a and 3a.
After being located at the lower side end of b, while scanning the laser beam 50, the condensing portion is scanned in the plane direction of the substrate so as to cover the entire ion implantation region. Thus, p of the ion implantation region ^- -type base region 3a, a heat treatment from a lower end of 3b to a predetermined height performed, p ^- type base region 3a,
3b, the poly-ty of the n ⁻ -type epi layer 2
Recrystallization is performed by inheriting the information of the crystal form (polymorphism) of pe (indicated by hatching in the figure).

[0039] At this time, p ^- type base region 3a, since the heat treatment is performed from the lower end of 3b, p ^- type base region 3a, the laser beam 50 in a portion positioned above than of 3b Although energy can be absorbed, the power of the laser beam 50 may be set in consideration of the energy absorption rate.

After that, the condensing portion is moved from the substrate side toward the inside (upper ends of the p ^- type base regions 3a and 3b), for example, to a position where it is not recrystallized. The light-collecting unit is scanned in the plane direction of the substrate so as to cover. Thereafter, by repeating such processing, the information of the crystal form of the n ⁻ -type epi layer 2 is inherited in order from the lower layer of the p ⁻ -type base regions 3a and 3b, and as shown in FIG. P ⁻ -type base regions 3a and 3b having the same poly-type crystal form are formed. In addition,
For reference, an arrow in FIG. 5B indicates a scanning path of the light collecting unit.

[Step shown in FIG. 2C] After the Mo film 20 is removed, N ⁺ ions are implanted from the upper surface of the
^- the surface layer portion of the type epi layer 2 and p ^- type base region 3a, 3b
The surface channel layer 5 composed of the n ⁻ -type layer 5a and the n ⁺ -type layer 5b is formed on the surface portion (surface layer portion). The ion implantation conditions at this time are as follows: a temperature of 700 ° C. and a dose of 1 × 10 ¹⁶ c.
m ^-2 . Thus, the surface channel layer 5 has p
^- is formed as a mold layer, n ^{- -} type base region 3a, the surface portion of the 3b impurity concentration is thin n of being compensated n-type impurity concentration of the n-type in the surface portion of the epitaxial layer 2 is thick n ⁺ -type layer Is formed as

In order to make the vertical power MOSFET normally-off type, the thickness (film thickness) of the surface channel layer 5 is set.
Is determined based on the following equation. Vertical power MO
In order for the SFET to be of the normally-off type, it is necessary that the depletion layer extending to the n ⁻ -type layer 5a has a sufficient barrier height so as to prevent electric conduction when no gate voltage is applied. is there. This condition is expressed by the following equation.

[0043]

[Formula 1] Where, Tepi is the height of the depletion layer extending to the n ⁻ -type layer, φms
Is the work function difference (electron energy difference) between metal and semiconductor,
Qs is a space charge in the gate insulating film (oxide film) 7, Qfc
Qi is a fixed charge at an interface between the gate oxide film (SiO ₂ ) and the n ⁻ -type layer 5a (hereinafter referred to as an SiO ₂ / SiC interface).
Is the mobile ion in the oxide film, Qss is the surface charge at the SiO ₂ / SiC interface, and Cox is the capacitance of the gate insulating film 7.

The first term on the right side of the equation 1 is the extension of the depletion layer due to the built-in voltage Vbuilt of the PN junction between the surface channel layer 5 and the p ^- type base regions 3a and 3b, that is, the p ^- type base region 3a, 3b to surface channel layer 5
The second term is the extension amount of the depletion layer due to the charge of the gate insulating film 7 and φms, that is, the extension amount of the depletion layer extending from the gate insulating film 7 to the surface channel layer 5. Therefore, if the sum of the extension of the depletion layer extending from the p ⁻ -type base regions 3 a and 3 b and the extension of the depletion layer extending from the gate insulating film 7 is equal to or greater than the thickness of the surface channel layer 5, the vertical power Since the MOSFET can be a normally-off type, the surface channel layer 5 is formed under ion implantation conditions satisfying this condition.

Such a normally-off type vertical power M
The OSFET can prevent a current from flowing even when a voltage cannot be applied to the gate electrode due to a failure or the like, so that safety can be ensured as compared with a normally-on type.

As shown in FIG. 1, the p ⁻ type base regions 3a and 3b are in contact with the source electrode 10 and are in a ground state. Therefore, the built-in voltage V of the PN junction between the surface channel layer 5 and the p ⁻ -type base regions 3a and 3b
Using built-in, the surface channel layer 5 can be pinched off. For example, when the p ⁻ type base regions 3a and 3b are not grounded and are in a floating state, it is impossible to extend the depletion layer from the p ⁻ type base regions 3a and 3b using the built-in voltage Vbuilt. Therefore, it can be said that bringing the p ⁻ -type base regions 3 a and 3 b into contact with the source electrode 10 is an effective structure for pinching off the surface channel layer 5.

A normally-off type vertical power MOS
In order to form an FET, it is necessary to set the thickness of the surface channel layer 5 so as to satisfy the condition of the above formula 2, but when silicon is used, the thickness of the surface channel layer 5 is reduced because Vbuilt is low. Considering that it is difficult to control the amount of diffusion of impurity ions, it can be said that manufacturing is extremely difficult. However, when SiC is used, Vbuilt is about three times as high as that of silicon and can be formed by increasing the thickness of the n ⁻ -type layer or increasing the impurity concentration. Therefore, it is possible to manufacture a normally-off type storage MOSFET. It can be said that it is easy.

[Step shown in FIG. 3 (a)] An LTO film 21 is disposed in a predetermined region on the surface channel layer 5, and N ⁺ ions are implanted using the LTO film 21 as a mask to form an n ⁺ type source region 4a,
4b is formed. The ion implantation condition at this time is 700
C. and the dose is 1 × 10 ¹⁵ cm ⁻² .

[Steps shown in FIG. 3 (b)]
After removing the film 21, the surface is etched using a photoresist method.
A Mo film 22 is disposed in a predetermined region on the channel layer 5,
P by RIE using ^-Mold base regions 3a, 3
b) Partially remove the surface channel layer 5 by etching.
You.

[Step shown in FIG. 3C] Further, B ⁺ ions are implanted using the Mo film 22 as a mask to form the deep base layers 30a and 30b. Thereby, a part of the base regions 3a and 3b becomes thicker. The deep base layers 30a and 30b are formed in the n ⁺ type source region 4
a, 4b, and is formed in a portion that does not overlap with the deep base layer 30a of the p ⁻ -type base regions 3a, 3b.
The thicker portion where the 30b is formed has a higher impurity concentration than the thinner portion where the deep base layer 30a is not formed.

[Step shown in FIG. 4A] After the Mo film 22 is removed, a gate insulating film (gate oxide film) 7 is formed on the substrate by wet oxidation. At this time, the ambient temperature is 1080 ° C.

Thereafter, a gate electrode 8 made of polysilicon is deposited on the gate insulating film 7 by LPCVD.
The film formation temperature at this time is 600 ° C.

[Step shown in FIG. 4B] Subsequently, after removing unnecessary portions of the gate insulating film 7, an insulating film 9 made of LTO is formed to cover the gate insulating film 7. More specifically,
The film formation temperature is 425 ° C., and annealing is performed at 1000 ° C. after the film formation.

[Step shown in FIG. 4C] Then, the source electrode 10 and the drain electrode 11 are arranged by metal sputtering at room temperature. After film formation, annealing at 1000 ° C. is performed.

Thus, the vertical power M shown in FIG.
The OSFET is completed.

Next, the operation (operation) of the vertical power MOSFET will be described.

This MOSFET operates in a normally-off type accumulation mode. When no voltage is applied to the gate electrode, carriers in the surface channel layer 5 are
The entire region is depleted by a potential caused by a difference in electrostatic potential between the p ⁻ type base regions 3 a and 3 b and the surface channel layer 5 and a difference in work function between the surface channel layer 5 and the gate electrode 8. . By applying a voltage to the gate electrode 8, a potential difference caused by the sum of a work function difference between the surface channel layer 5 and the gate electrode 8 and an externally applied voltage is changed. As a result, the state of the channel can be controlled.

In the off state, the depletion region is p
^-Made by mold base regions 3a, 3b and gate electrode 8
The electric field is formed in the surface channel layer 5.
From this state, a positive bias is supplied to the gate electrode 8.
Then, the gate insulating film (SiO_Two7) and surface channel layer
5 at the interface between⁺Type source regions 4a, 4b
N^-Channel region extending in the direction of the mold drift region 2
And switched on. At this time,
The child is n⁺From source regions 4a and 4b to surface channel layer
5 through the surface channel layer 5 to n^-Flow to the epilayer 2
You. And n ^-Reaches the epitaxial layer 2 (drift region)
And the electron is n⁺Mold substrate 1 (n⁺Flow vertically to the drain)
It is.

As described above, by applying a positive voltage to the gate electrode 8, a storage channel is induced in the surface channel layer 5, and carriers flow between the source electrode 10 and the drain electrode 11.

(Other Embodiments) In the above embodiment, the laser is focused, and energy is generated at the focused point to recrystallize the laser.

FIG. 6 shows the state of laser irradiation. As shown in this figure, using a plurality of lasers 60, 61,
A plurality of lasers can intersect each other, and the heat treatment can be performed in the intersecting region 62.

According to such a heat treatment, a large energy can be generated on a wide intersecting surface.
The heat treatment can be performed in a wider range than in the above embodiment. For this reason, the manufacture of the semiconductor device can be facilitated, and the production efficiency can be improved.

In the above embodiment, the p ⁻ -type base regions 3 a and 3 b are arranged from the substrate side to the surface side (the p ⁻ -type base regions 3 a and 3 b).
a, 3b are recrystallized in order from the lower end to the upper end), but as shown in FIG. 7, the recrystallization is sequentially performed from the front side toward the substrate side (from the upper end to the lower end). It can also be crystallized. In this case, the p ⁻ type base region 3
a and 3b inherit the information of the crystal form of 4H-SiC located on the surface side of the p ⁻ -type base regions 3a and 3b.

However, also in this case, a laser having a wavelength longer than the band gap of 4H-SiC is used so that the energy of the laser is not absorbed by 4H-SiC located above the p ^- type base regions 3a and 3b. There is a need. Therefore, in this case, adjust the wavelength of the excimer laser,
Heat treatment is performed so that the wavelength is longer than the band gap of 4H-SiC.

In the above embodiment, an excimer laser is used, but other lasers can be used. For example, He-Cd laser, He-Ne laser, A
An r ⁺ laser may be used. Also, instead of a laser, X
-Ray, an electron beam, a neutron beam, a positron beam, or the like may be used.

For example, in the case of a He-Cd laser, a He-Ne laser, an Ar ⁺ laser, and an X-ray, the wavelength is 4H-
Since it is longer than the band gap of SiC, 4
By transmitting H-SiC located under the 4H-SiC p ^- type base region 3a, even when irradiating the laser 3b, without energy in the upper layer of 4H-SiC is absorbed, p ^- -type base The regions 3a and 3b can be recrystallized.

In the case of a neutron beam, it collides with an atom.
Neutrons are injected until ^-Mold base area 3
of channeling of 4H-SiC located on the upper layer of a, 3b
Amorphous when neutron beam is incident along the direction
P^-Neutrons are generated at the mold base regions 3a and 3b.
Collide with the child and generate energy, p^-Mold base area 3
a, 3b can be recrystallized.

[Brief description of the drawings]

FIG. 1 is a vertical power MOS according to an embodiment of the present invention.
It is sectional drawing of FET.

FIG. 2 is a diagram showing a manufacturing process of the vertical power MOSFET shown in FIG.

FIG. 3 is a view illustrating a manufacturing process of the vertical power MOSFET following FIG. 2;

FIG. 4 is a view illustrating a manufacturing process of the vertical power MOSFET following FIG. 3;

FIG. 5 is a diagram showing a state of a heat treatment step using a laser.

FIG. 6 is a diagram illustrating a state of a heat treatment step using a laser according to another embodiment.

FIG. 7 is a view showing a state of a heat treatment step using a laser according to another embodiment.

FIG. 8 is a sectional view of a conventional vertical power MOSFET.

FIG. 9 is a diagram for explaining a state of recrystallization of a base region.

[Explanation of symbols]

1 ... n ⁺ type substrate, 2 ... n ^- type epitaxial layer, 3a,
3b ... p ^- type base region, 4a, 4b ... n ⁺ -type source region, 5 ... surface channel layer (n ^- -type SiC layer), 5a ... n
^- -type layer, 5b ... n ⁺ -type layer, 7 ... gate insulating film, 8 ... gate electrode, 9 ... insulating film, 10 ... Source electrode, 11 ... drain electrode, 50 ... laser light, 51 ... condenser lens.

Claims (10)

[Claims] 1. A step of forming a first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate (1) on a main surface of the first conductivity type semiconductor substrate (1). Forming a second conductivity type base region (3a, 3b) having a predetermined depth by ion implantation in a predetermined region of a surface layer portion of the semiconductor layer (2); Base area (3a, 3b)
Forming a surface channel layer on the upper surface of the base region;
Forming a first conductivity type source region (4a, 4b) in contact with the surface channel layer (5) and shallower than the depth of the base region (3a, 3b). The step of forming the base region (3a, 3b) includes a step of implanting an impurity of the second conductivity type with an acceleration energy of 1 MeV or more, and a step of performing a heat treatment by a laser to activate the implanted impurity and Recrystallizing the base regions (3a, 3b). A method for manufacturing a silicon carbide semiconductor device, comprising: 2. In the laser heat treatment step, laser irradiation is performed in order from a lower side end to an upper side end of the base region (3a, 3b) or from an upper side end to a lower side end. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein: 3. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the laser heat treatment step, the heat treatment is performed in a condensing portion that condenses the laser. 4. The laser heat treatment step, wherein laser irradiation is performed so that a plurality of lasers cross each other, and the heat treatment is performed at a portion where the lasers cross each other. 3. The method for manufacturing a silicon carbide semiconductor device according to item 1. 5. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein an excimer laser is used as said laser. 6. The wavelength of the excimer laser is 4H-Si.
6. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein the wavelength is longer than a wavelength determined from the band gap of C. 7. A He-Cd laser as the laser,
The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein one of a He—Ne laser and an Ar ⁺ laser is used. 8. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein an X-ray is used instead of said laser. 9. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein any one of an electron beam, a neutron beam, and a positron beam is used instead of the laser. 10. A semiconductor substrate (1) of a first conductivity type having a main surface and a back surface opposite to the main surface and made of silicon carbide, formed on a main surface of the semiconductor substrate (1), A first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate (1); and a second layer formed in a predetermined region of a surface portion of the semiconductor layer (2) and having a predetermined depth. Conductive base region (3a, 3b)
A first conductivity type source region (4a, 4b) formed in a predetermined region of a surface portion of the base region (3a, 3b) and shallower than a depth of the base region (3a, 3b); (3a, 3b) and the surface of the semiconductor layer (2), the source regions (4a, 4b).
b) and the semiconductor layer (2).
Surface channel layer of first conductivity type made of silicon carbide (5)
A gate insulating film (7) formed on the surface of the surface channel layer (5); and a gate electrode (8) formed on the gate insulating film.
And the base region (3a, 3b) and the source region (4
a, 4b), the source electrode (1
0), and a drain electrode (11) formed on the back surface of the semiconductor substrate (1), wherein the base regions (3a, 3b) have a thickness of 1 μm or more, and A silicon carbide semiconductor device having the same polymorphism as described above.