JPH05190849A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the diffusion of impurity more than necessity by the inhibit effect of C on impurity diffusion through introducing C into a region where the impurity diffusion is intended in a silicon substrate. CONSTITUTION:In the manufacture of a semiconductor device, the semiconductor device is formed in such manner that C ion is implanted beforehand in a source- drain region 15 (b) and then B ion is implanted in the implantation region of the C ion (c) and is covered by C and thereafter the semiconductor device is subjected to heat treatment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a heat treatment step in which impurities introduced into a semiconductor are prevented from diffusing more than necessary.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, “MOS LSI manufacturing technology” edited by Shiba Tokuyama, Tetsuichi Hashimoto P. Nikkei Tuna Hill Co. 30 were listed. The ion implantation method is widely used as a method for introducing impurities into a silicon semiconductor. However, since the implanted impurities are not electrically activated as they are, the heat treatment step for electrical activation must be performed after the ion implantation step. Need.

[0003]

However, in the above method, impurities are electrically activated and diffused at the same time during the heat treatment usually performed at about 1000 ° C., and the distribution of impurities becomes larger than necessary. There was a problem that it would end up. The present invention introduces C (carbon) into a region where impurity diffusion is planned and eliminates the impurity diffusion suppressing effect of the C in order to eliminate the above-mentioned problem that the impurity diffuses more than necessary during activation heat treatment. By
Provided is a method for manufacturing a semiconductor device capable of reducing unnecessary diffusion of impurities.

[0004]

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, in which C ions are preliminarily implanted into a portion of a silicon substrate where impurity diffusion is planned, An impurity is implanted into an ion implantation region, the impurity is formed so as to be covered with C, and a heat treatment process is performed thereafter.

[0005]

According to the present invention, as described above, in the ion implantation method which is an impurity introduction method into a silicon substrate, C is previously introduced into the impurity distribution region, and the impurity diffusion suppressing effect of the C causes the impurities to be heat treated. Sometimes try not to spread more than necessary. Therefore, even during the heat treatment associated with the ion implantation process, unnecessary diffusion of the implanted impurities is suppressed, and electrical activation becomes possible.

[0006]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view of a manufacturing process of a semiconductor device showing an embodiment of the present invention, and FIG. 2 is a characteristic diagram of the depth of a diffusion layer and B (boron) concentration of the semiconductor device showing an embodiment of the present invention. Here, the manufacturing process of the P-channel MOSFET is shown.

First, as shown in FIG. 1A, a field oxide film 12, a gate oxide film 13, and a low resistance polycrystalline silicon gate electrode 14 are formed on the surface of an N-type silicon substrate 11 by a normal process. Next, as shown in FIG. 1B, C ions are then implanted to form the source / drain portions 15 of the silicon substrate. In order to set the C concentration of the source / drain portion 15 to 1 × 10 ²⁰ cm ⁻³ , the C ion has an energy of 90 KeV and a dose amount of 2 × 1.
Inject at 0 ¹⁵ cm ^-2 . As a result, the C concentration is 1 × 10 ²⁰ cm ⁻³ from the surface of the substrate to a depth of 200 nm.

Next, as shown in FIG.
In order to form the P ⁺ layer 16 in the drain portion 15, B ions are implanted with an energy of 20 KeV and a dose amount of 2 × 1.
Perform at 0 ¹⁵ cm ^-2 . As a result, B has a depth of 100 nm
To be implanted at a concentration of 1 × 10 ²⁰ cm ^-3. Thereafter, as shown in FIG. 1D, B is electrically activated by heat treatment at 1000 ° C. for 75 s (seconds), but the diffusion of B is as shown in FIG. At a depth of 200 nm, it can be suppressed by 100 nm or more as compared with the case without C implantation.

As described above, the source / drain P ⁺ layer 1
6 is formed, then, as shown in FIG.
The interlayer insulating film 17 and the Al electrode 18 are formed by the OSLSI manufacturing process, and the manufacturing of the P-channel MOSFET is completed. In FIG. 2, the horizontal axis represents depth (nm), the vertical axis represents B concentration (cm ⁻³ ), the curve is before heat treatment, the curve has a C concentration of 1 × 10 ²⁰ cm ⁻³ , and the curve has a C concentration. Is 1 × 1
0 ¹⁸ cm ^-3 , the curve shows the case without C implantation. The heat treatment was performed at 1000 ° C. for 75 seconds.

The method of suppressing the diffusion of impurities by C implantation in the above embodiment is effective not only for B but also for other impurities. Especially Si
The diffusion in the same interstitially as B (in
It is clear that it is also effective in suppressing the diffusion of P and As, which are impurities of Group V, and the heavy metals Fe, Co, Ni, Cu, Au, etc., which are known to be based on the tertsity mechanism.

Therefore, the present invention is not only effective in forming the source / drain portions of the P-channel MOSFET described above, but also in the case of another forming method using ion implantation, for example, in the case of the P-channel MOSFET. Of course, it is also effective when forming the channel part, the channel part and the source / drain part of the n-channel MOSFET, and the collector / base / emitter part of the bipolar transistor.

Further, when heavy metal impurities different from desired ions are introduced during ion implantation, diffusion of these heavy metals can be suppressed, and therefore deterioration of device characteristics can be prevented. Is. It should be noted that the present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0013]

As described above in detail, according to the present invention, C is introduced into the impurity distribution region of the silicon substrate in advance, and the impurity diffusion suppressing effect of C diffuses impurities more than necessary during the heat treatment. Since this is not done, even during the heat treatment associated with the ion implantation step, unnecessary diffusion of the implanted impurities is suppressed, and electrical activation becomes possible.

Further, when heavy metal impurities different from desired ions are introduced at the time of ion implantation, diffusion of these heavy metals can be suppressed, so that deterioration of device characteristics can be prevented.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device manufacturing process showing an embodiment of the present invention.

FIG. 2 is a characteristic diagram of depth and B concentration of a diffusion layer of a semiconductor device showing an example of the present invention.

[Explanation of symbols]

11 N-type silicon substrate 12 Field oxide film 13 Gate oxide film 14 Low resistance polycrystalline silicon gate electrode 15 Source / drain portion 16 P ⁺ layer 17 Interlayer insulating film 18 Al electrode

Claims (2)

[Claims] 1. A step of: (a) implanting C ions in advance in a portion of a silicon substrate where impurity diffusion is planned; and (b) implanting impurities into the C ion implantation region and covering the impurities with C. And a heat treatment step (c) are subsequently performed. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the C concentration is 1 × 10 ¹⁸ cm ⁻³ or more.