JP2850813B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a semiconductor device used as a memory LSI or a logic device as a MOS LSI.

[0002]

2. Description of the Related Art In recent years, MOSFETs have been highly integrated and miniaturized.
The joining design conditions also need to be adjusted to this scaling. To comply with this scaling law, MO
Many proposals have been made, such as a technique for reducing the depth of a p / n junction of a diffusion layer such as a source and a drain of an S-type element, a technique for controlling a channel concentration, and a technique for returning impurities. In particular, 900 ° C. for B (boron) implantation for forming a p-type diffusion layer.
Since the diffusion of B in Si at the above-mentioned annealing temperature is large, it is difficult to form a shallow junction, and a technique for reducing this diffusion is required. For example, Japanese Patent Application Laid-Open No. 62-112321
The technique disclosed in Japanese Patent Laid-Open Publication No. H10-157, is a technique for applying a technique of forming a metal silicide layer on a diffusion layer in order to reduce the resistance of the diffusion layer, thereby achieving a shallow junction of a p-type diffusion layer.

The prior art will be described using the technique disclosed in Japanese Patent Application Laid-Open No. 62-112321. FIGS. 3A to 3F are schematic cross-sectional views illustrating a p-type diffusion layer forming technique disclosed in Japanese Patent Application Laid-Open No. Sho 62-112321.
Indicates each step. In the figure, reference numeral 31 denotes an n-type silicon substrate, 3
2 is an element isolation structure, 33 is a gate insulating film, 34 is a gate electrode, 35a is a p source, 35b is a p drain, 36 is a TiN film, 37 is a p diffusion layer distributed to both TiN and Si by heat treatment, and 38 is a junction. A shallow p-diffusion layer,
Reference numeral 39 denotes a passivation film, and reference numeral 40 denotes an aluminum wiring.

First, an element isolation structure 32 is formed on an n-type silicon substrate 31, and a gate electrode 34 is formed of phosphorus-doped polycrystalline silicon via a gate insulating film 33 (a). Next, B (boron) is implanted using the gate electrode as a mask, and heat treatment is performed at 900 ° C. or more to form p-type source 35a / drain 35b regions (b). Thereafter, a TiN film 36 is formed on the entire surface by, for example, a sputtering method (c). Next, by performing a heat treatment in a nitrogen atmosphere at 450 ° C., B distributed in Si becomes T
Diffusion into the iN film 36 forms a p-diffusion layer 37 distributed in both TiN and Si. B diffused T
When the iN layer 36 is removed by etching, a p-type diffusion layer 38 having a reduced junction depth is obtained, and a shallow junction between the p-type source and the drain can be achieved (e). Finally passivation film 3
9. The aluminum wiring 40 is formed to complete the MOS element (f).

[0005] However, in this conventional example, 900% is usually injected with B.
The junction depth of the p-type diffusion layer formed by heat treatment at
It is formed deeper than 00 nm. For this reason, it is very difficult to form a sufficiently small junction depth by diffusing B into the TiN film by a low-temperature heat treatment at 450 ° C.

On the other hand, Yasuhisa 0 mur
a et al. Extended Abstract of the 2
0th Conference on Solid State
Device and Materials, 1988, 93-9
6 pages (Extendedabstracts of
20th Conference on Sol-i
d State Devices and Mater
ials, 1988, pp. 93-96), studies are being made on formation of Ti silicide by ion implantation of Ti into a region serving as a source / drain or a gate polysilicon electrode. 0
Mura et al. implant phosphorus or boron into a region serving as a source / drain of a p-type or n-type silicon substrate and perform heat treatment for activation. Next, Ti was accelerated at an acceleration voltage of 30 Ke.
V, dose of 1 × 10 ¹⁷ cm ^-2 and heat treatment,
The source / drain regions are made into Ti silicide. For this reason, in the above method, since heat treatment is performed by injecting impurities serving as carriers before the Ti silicidation reaction, there is a problem that accelerated diffusion of, for example, boron cannot be suppressed.

Further, in order to suppress diffusion due to channeling, a technique has been proposed in which an amorphous layer is formed by ion implantation before impurity implantation to suppress impurity diffusion. This will be disclosed using the method of manufacturing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 4-158530. 4A to 4F are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 4-158530.
Indicates each step. Reference numeral 41 in the figure denotes an n-type silicon substrate, 4
2 is a gate insulating film, 43 is an inverted T-shaped gate electrode, 44 is an amorphous layer, 45 is an insulating film for a gate electrode spacer, 45a
Is a gate electrode spacer, 46 is an inverted T-shaped gate electrode, 4
7 denotes a P ⁺ diffusion layer, 48 denotes an interlayer insulating film, and 49 denotes an aluminum electrode.

After an element isolation structure is formed on an n-type silicon substrate 41, a gate insulating film 42 and a low-resistance polycrystalline silicon film for a gate electrode are formed, and an inverted T-shaped gate electrode 43 is formed by an etching method ( a). Thereafter, Si ions are implanted at 70 KeV and 2 × 10 ¹⁵ cm ⁻² , and amorphized to a depth of 100 nm from the surface of the source / drain portion to form an amorphous layer 44 (b). Next, a gate electrode spacer insulating film 45 is deposited (c) and etched back to form a gate electrode spacer 45 which is a sidewall of the gate electrode.
a is formed. At this time, portions of the inverted T-shaped electrode 43 and the gate insulating film 42 other than the portion surrounded by the gate electrode spacer 45a are removed (d). Using this as a mask, BF ₂ is 15K
Ion implantation is performed at eV and 2 × 10 ¹⁵ cm ⁻² . At this time, B
Is estimated to be 50 nm in simulation and 40 nm in lateral spread. Thereafter, heat treatment is performed at 950 ° C. for 15 seconds by lamp annealing to form a p-type diffusion layer 47 (e). Finally, a passivation film 39 and an aluminum wiring 40 are formed to complete a MOS element (f).

The depth of the p-type diffusion layer 47 manufactured under the above conditions is about 90 nm, and the lateral spread is 70 nm. However, the depth of the amorphous layer 44 formed by implanting Si ions before implanting BF ₂ is 100 nm, which is deeper than the finally formed p-type diffusion layer junction depth of 90 nm. Therefore, it is considered that the junction characteristics at the p / n junction boundary are not good. Although the above method certainly suppresses lateral diffusion at the time of implanting BF ₂ , it is difficult to suppress the enhanced diffusion of B by heat treatment at the time of impurity activation or recovery of an amorphous portion. It is difficult to control depth or lateral diffusion. Further, an implantation defect layer remains, which may adversely affect the bonding characteristics.

[0010]

The above-mentioned JP-A-62-1
In the conventional example disclosed in Japanese Patent No. 12321, B implanted into a Si substrate before forming a TiN film is diffused deeply by a heat treatment at 900 ° C. or more, and a TiN film of B is formed by a heat treatment after the deposition of the TiN film. By suction to the side, a sufficiently shallow junction is not formed.

In the method of Yasuhisa Omura et al., An impurity such as boron as a carrier is first implanted into the source / drain region and heat treatment is performed, then Ti ion implantation is performed, and a silicidation heat treatment is performed. Since the p-type diffusion layer has already been formed in a deep region, diffusion of boron to the Ti silicide film side is not sufficient.

In the conventional example disclosed in Japanese Patent Application Laid-Open No. 4-158530, an amorphous Si is formed by gate self-alignment.
Implantation is performed, and then a side wale is formed beside the gate electrode, BF ₂ is implanted using this as a mask, and heat treatment is performed to suppress lateral channeling and form a shallow junction.
There is a problem that it is not possible to control up to the accelerated diffusion of B, and that the amorphous boundary depth is set at a position slightly deeper than the junction boundary of the diffusion layer, and it is difficult to improve the junction characteristics.

An object of the present invention is to suppress the enhanced diffusion of impurities, form a shallow diffusion layer, and have good junction characteristics.
An object of the present invention is to provide a method of manufacturing a semiconductor device capable of miniaturizing a MOSFET element.

[0014]

According to a method of manufacturing a semiconductor device of the present invention, there is provided a method of manufacturing a semiconductor device having a channel insulated gate field effect transistor.
Forming a metal ion-implanted region that becomes an amorphous layer by injecting metal ions on the surface of the semiconductor substrate on which the gate insulating film, the gate electrode, and the electrode protecting sidewall are formed; and in the vicinity of the boundary between the implanted region and the semiconductor substrate, a step of introducing an impurity to be a p-type or n-type carrier, after impurity introduction, the silicidation reaction
Forming a metal silicide layer in the metal ion-implanted region by performing heat treatment at a first temperature at which the impurity atoms are hardly diffused ;
Performing a second heat treatment at a temperature higher than the temperature to diffuse the implanted impurities to form a p / n junction boundary of the diffusion layer at a position deeper than an interface between the metal silicide and the semiconductor substrate.

In a method of manufacturing a semiconductor device having a channel insulated gate field effect transistor, a metal film is formed on a surface of a semiconductor substrate on which an element isolation structure, a gate insulating film, a gate electrode and an electrode protection sidewall are formed. a step of, in the vicinity of the boundary between the formed metal film and a metal and a semiconductor substrate, a step of introducing an impurity to be a p-type or n-type carrier, after impurity introduction, silicidation reaction
A step of forming a metal silicide layer on the metal film by performing a heat treatment at a first temperature at which the impurity atoms are hardly diffused, and a step of removing the metal film other than the upper part of the diffusion layer forming part and the gate electrode; At a higher temperature than the first temperature
Performing a second heat treatment to diffuse the implanted impurities to form a p / n junction boundary of the diffusion layer at a position deeper than an interface between the metal silicide and the semiconductor substrate.

In the latter manufacturing method, the formation of the metal film may be performed by a sputtering method, a CVD method, or a vapor deposition method.

The metal used for forming the metal silicide layer may be Ti, Co, or W.

According to the method of manufacturing a semiconductor device of the present invention,
The enhanced diffusion of impurities during heat treatment due to the influence of the point defects occurring upon implantation of impurities into the semiconductor substrate by ion implantation, impurities are introduced in the vicinity or in the silicide / semiconductor substrate boundaries metal silicide formation regions, and silicide
Reaction proceeds but impurity atoms hardly diffuse.
Since the metal silicide reaction is caused at the temperature of 1, point defects contributing to the accelerated diffusion are consumed in the metal silicide reaction, and the point defects have a much lower concentration than in the prior art.

Therefore, in the subsequent heat treatment at a temperature higher than the first temperature for forming the diffusion layer , the accelerated diffusion of impurities is suppressed, and a shallow diffusion layer can be formed.

Further, since the bonding boundary layer is in direct contact, good bonding characteristics can be obtained.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings. FIGS. 1A to 1D are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. FIGS. Reference numeral 11 in the figure
Is a silicon single crystal substrate, 12 is an element isolation structure, 13 is a gate insulating film, 14 is a gate electrode, 15 is a nitride film sidewall, 16 is an oxide film sidewall, 17a is an amorphous layer, and 17b is BF ₂ implantation. 17c indicates a silicidation reaction layer, 18 indicates a p-type diffusion layer, 19a indicates Ti ion implantation, and 19b indicates BF ₂ ion implantation.

First, an element isolation structure 12 is formed on a silicon single crystal substrate 11, a gate insulating film 13 is formed to a thickness of 8 nm, and a polycrystalline silicon film for a gate electrode is formed by LP.
Deposit 150 nm thick by CVD. After doping the gate polycrystalline silicon film with impurities by phosphorus diffusion, the gate electrode 14 is formed by dry etching. Further, a nitride film having a thickness of 10 nm is deposited for protecting the gate electrode, and then etched back. Further, a CVD oxide film is deposited with a thickness of 50 nm, and etched back in the same manner as described above, and the nitride film sidewall 15 and the oxide film are formed only on the side surfaces of the gate electrode. Leave the sidewall 16. Next, the ion implantation 19a of Ti is performed at an acceleration voltage of 20 KeV and the dose is 5 × 10 ¹⁶ to 1 × 10 ¹⁷ cm.
By performing about ^-2 , an amorphous layer 17a having a thickness of about 30 nm is formed (a).

Subsequently, BF ₂ ion implantation 19b is performed at an acceleration voltage of 25 KeV and a dose of 1 × 10 ¹⁵ cm ⁻² to turn the amorphous layer 17a into the BF ₂ implanted amorphous layer 17b (b ).

Next, a heat treatment at 650 ° C. is performed. At this time, T
The i-silicidation reaction layer 17c is generated, and a large amount of point defects (interstitial silicon) generated by Ti or B implantation or the like are consumed by the silicidation reaction. (C).

Next, in order to diffuse impurities so that the junction boundary of the p-type diffusion layer 18 comes into contact with the silicide layer boundary at a carrier concentration higher than about 5 × 10 ¹⁹ cm ⁻³ , the lamp is annealed at 800 ° C. The heat treatment is performed for 20 seconds to form the p-type diffusion layer 18 (d). At this time, the point defects contributing to the accelerated diffusion of boron due to the first silicidation reaction are reduced near the silicide layer boundary.
The diffusion from the high-concentration region is suppressed, and a shallow junction can be formed.

Finally, a passivation film and an aluminum wiring are formed to complete a MOS device.

Next, FIG. 2 is a schematic sectional view for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
(A)-(d) show each process. In the figure, reference numeral 21 denotes a silicon single crystal substrate, 22 denotes an element isolation structure, 23 denotes a gate insulating film, 24 denotes a gate electrode, 25 denotes a nitride film sidewall,
26 is an oxide film sidewall, and 27a is a sputter Ti
Reference numeral 27b denotes a silicidation reaction layer of sputtered Ti reacted at a low temperature, 27c denotes a Ti silicidation reaction layer after excessive Ti etching, 28 denotes a p-type diffusion layer, and 29 denotes BF ₂ ion implantation.

First, an element isolation structure 22 is formed on a silicon single crystal substrate 21, a gate insulating film 23 is formed to a thickness of 8 nm, and a polycrystalline silicon film for a gate electrode is formed by LPC.
Deposit 150 nm thick by VD method. After doping the gate polycrystalline silicon film with impurities by phosphorus diffusion, the gate electrode 24 is formed by dry etching. Further, a nitride film having a thickness of 10 nm is deposited for protecting the gate electrode, and then etched back. Further, a CVD oxide film is deposited with a thickness of 50 nm, and etched back in the same manner as described above, and the nitride film sidewall 25 and the oxide film are formed only on the side surfaces of the gate electrode. Leave the sidewall 26. Next, a 20 nm-thick sputtered Ti film 27a is deposited by sputtering (a).

Subsequently, the projection range is changed to the sputtering Ti film /
The film is set slightly on the Ti film side from the silicon substrate interface, and BF ₂ ion implantation 29 is performed at an acceleration voltage of 20 KeV and a dose of 1 × 10
Perform at ¹⁵ cm ^-2 (b).

Next, a heat treatment at 650 ° C. is performed. At this time, T
The i-silicidation reaction layer 27b is generated, and a large amount of point defects (interstitial silicon) generated near the Ti silicide layer boundary due to BF ₂ implantation or the like are almost consumed by the silicide reaction and have a very low concentration. By this silicidation reaction at a low temperature, boron as an impurity serving as a carrier does not diffuse (c).

Thereafter, through an extra Ti etching step and the like,
The Ti silicidation reaction layer 27c is formed only on the diffusion layer and the gate electrode, and a lamp annealing method is used so that the p / n junction boundary of the p-type diffusion layer 28 is formed at a position deeper than the silicide layer. 870 ° C. for 10 seconds. As a result, although the impurity B serving as a carrier starts to diffuse, the point defects contributing to the accelerated diffusion are reduced, so that the accelerated diffusion of B is suppressed during the heat treatment at 700 ° C. or more and shallow. A bond can be formed (d).
Finally, passivation film and aluminum wiring are formed and MOS
Complete the mold element.

[0032]

According to the present invention, the enhanced diffusion of impurities during heat treatment due to the effect of point defects generated when introducing impurities into a semiconductor substrate by ion implantation is performed by using the impurities in the metal silicide formation region or the silicide. / Introduced near the semiconductor substrate boundary and the silicidation reaction proceeds, but
Since the metal atoms cause the metal silicide reaction at the first temperature at which the pure atoms hardly diffuse , the point defects contributing to the accelerated diffusion are consumed by the metal silicide reaction, and the point defects have a much lower concentration than in the prior art. For this reason, the first
In the heat treatment at a temperature higher than the temperature described above, the accelerated diffusion of the impurities is suppressed, a shallow diffusion layer can be formed, and the junction boundary layer is in direct contact and the junction characteristics are good.
The effect that the OSFET type element can be miniaturized is obtained.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. (A) shows a first step. (B) shows the second step. (C) shows a third step. (D) shows a fourth step.

FIG. 2 is a schematic sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. (A) shows a first step. (B) shows the second step. (C) shows a third step. (D) shows a fourth step.

FIG. 3 is a schematic cross-sectional view illustrating a p-type diffusion layer forming technique disclosed in Japanese Patent Application Laid-Open No. 62-112321.
(A) shows a first step. (B) shows the second step. (C) shows a third step. (D) shows a fourth step. (E) shows a fifth step. (F) shows a sixth step.

FIG. 4 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 4-158530 of a conventional example. (A) shows a first step. (B) shows the second step. (C) shows a third step. (D) shows a fourth step. (E) shows a fifth step. (F) shows a sixth step.

[Explanation of symbols]

11, 21 Silicon single crystal substrate 12, 22 Element isolation structure 13, 23 Gate insulating film 14, 24 Gate electrode 15, 25 Nitride film sidewall 16, 26 Oxide film sidewall 17a Amorphous layer 17b BF ₂ implanted Amorphous layer 17c Silicidation reaction layer 18, 28 P-type diffusion layer 19a Ti ion implantation 19b, 29 BF ₂ ion implantation 27a Ti sputtered film 27b Silicidation reaction layer of sputter Ti reacted at low temperature 27c Excess Ti etched Ti Silicidation reaction layer 31, 41 n-type silicon substrate 32 element isolation structure 33, 42 gate insulating film 34 gate electrode 35a p-type source 35b p-type drain 36 TiN film 37 p diffusion layer distributed to both TiN and Si by heat treatment 38 junction P-diffusion layer with shallow depth 39 Passivation film 0 aluminum wiring 43 inverted T-shaped gate electrode 44 source and drain layer 45 a gate electrode spacer insulating film 45a gate electrode spacers 46 inverted T-shaped gate electrode 47 P ⁺ diffusion layer 48 interlayer insulating film 49 aluminum electrode

Claims (9)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a channel insulated gate field effect transistor, comprising the steps of: depositing metal ions on a surface of a semiconductor substrate on which an element isolation structure, a gate insulating film, a gate electrode, and an electrode protection sidewall are formed; Forming a metal ion-implanted region to be an amorphous layer by implantation; and introducing a p-type or n-type carrier impurity into the vicinity of the metal ion-implanted region and a boundary between the implanted region and the semiconductor substrate. After the process and the introduction of impurities, the silicidation
Forming a metal silicide layer in the metal ion-implanted region by performing a heat treatment at a first temperature at which the element hardly diffuses ; and after forming the metal silicide layer, a temperature higher than the first temperature.
Performing a second heat treatment at a temperature to diffuse the implanted impurities and forming a p / n junction boundary of the diffusion layer at a position deeper than an interface between the metal silicide and the semiconductor substrate. A method for manufacturing a semiconductor device. 2. A method of manufacturing a semiconductor device having a channel insulated gate field effect transistor, comprising: forming a metal film on a surface of a semiconductor substrate on which an element isolation structure, a gate insulating film, a gate electrode and an electrode protection sidewall are formed. a step of, the metal film is formed and in the vicinity of the boundary between the metal and the semiconductor substrate, a step of introducing an impurity to be a p-type or n-type carrier, after impurity introduction, silicidation reaction proceeds but impurities original
Child forming a first metal silicide layer on the metal film by heat at a temperature of hardly diffused, and removing the diffusion layer forming section top and a metal film other than the gate electrode upper, first temperature Forming a p / n junction boundary of the diffusion layer at a position deeper than the interface between the metal silicide and the semiconductor substrate by performing a second heat treatment at a higher temperature to diffuse the implanted impurities. A method for manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the formation of the metal film is performed by a sputtering method. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the metal film is formed by a CVD method. 5. The method for manufacturing a semiconductor device according to claim 2, wherein the formation of the metal film is performed by a vapor deposition method. 6. The method according to claim 1, wherein the metal used for forming the metal silicide layer is T.
i. A method for manufacturing a semiconductor manufacturing apparatus, wherein i. 7. The method for manufacturing a semiconductor manufacturing device according to claim 1, wherein the metal used for forming the metal silicide layer is C.
o. A method of manufacturing a semiconductor manufacturing apparatus, wherein 8. The method for manufacturing a semiconductor device according to claim 1, wherein the metal used for forming the metal silicide layer is W.
A method for manufacturing a semiconductor manufacturing apparatus. 9. The semiconductor according to claim 1 or claim 2.
In the manufacturing method of the manufacturing apparatus, Wherein the first temperature is 700 ° C.
Manufacturing method of body manufacturing device.