JPH10125916A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a reduction in the depth of each impurity diffused layer along a scaling law and the like to a miniaturization of a MIS semiconductor device. SOLUTION: A gate insulating film 4, a gate electrode 5 and sidewalls 7 are formed on a P-type silicon substrate 1. Arsenic ions are implanted in the substrate 1 using the electrode 5 and the sidewalls 7 as masks and impurity diffused regions 10 for source and drain use are formed. Similarly, carbon ions are implanted to form carbon-doped regions Rcd to overlap with the regions 10. An activation of the impurities using a heat treatment is performed to form an N-type low-resistance gate electrode 5a and N-type source and drain regions 10a. At that time, as diffusion of the arsenic impurities is inhibited by the carbon impurities, the depth of the regions 10a is inhibited and a reduction in the depth along a scaling law becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention provides a semiconductor device capable of suppressing a short channel effect or the like in accordance with miniaturization and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, high-density semiconductor devices, so-called LS, have been developed.
In the development of I, miniaturization of semiconductor elements such as transistors, which are constituent elements, is increasingly required. Here, in order to advance the miniaturization of a semiconductor element, for example, a MOS transistor, the dimensions of each part such as the gate length in the MOS transistor in each generation are reduced in accordance with a scaling rule, which is formed by implanting impurity ions. It is difficult to reduce the depth of the impurity diffusion layers such as the source / drain regions in proportion to the gate length. Therefore, as the gate length is reduced, problems such as a so-called short channel effect such as a reduction in threshold voltage and occurrence of punch-through occur. Therefore, in order to suppress the short channel effect, for example, measures such as increasing the impurity concentration of the semiconductor substrate have been taken. However, if the depth of the impurity diffusion layer cannot be reduced, the short channel effect is basically eliminated. It is difficult.

Therefore, several proposals have conventionally been made on the structure of a MOS transistor and a method for manufacturing the same in order to make the depth of the source / drain region closer to the depth according to the scaling rule.

Hereinafter, a conventional MOS transistor will be described with reference to the drawings.
An example of a structure and a manufacturing method of a transistor will be described.

FIGS. 21A to 21C show examples of the structure of a conventional n-channel MOS transistor, respectively. For convenience, the transistor shown in FIG. The transistor shown in b)
The extension type transistor shown in FIG. 21C is called an extension type with a pocket.

As shown in FIG. 21A, a single drain type MOS transistor is a p-type silicon substrate (p type).
Mold well) 1, a gate insulating film 4 formed on the p-type silicon substrate 1, an n-type gate electrode 5a formed on the gate insulating film 4, and a p-type silicon substrate with the n-type gate electrode 5a interposed therebetween. N-type source / drain region 1 formed in
0a and a p-type channel region 16a formed in a region in the silicon substrate 1 located immediately below the n-type gate electrode 5a.
It is composed of When the MOS transistor is miniaturized and the gate length is reduced, the depth of the source / drain region 10a is reduced according to the scaling rule,
If the p-type impurity concentration of the silicon substrate 1 is increased, the short channel effect can be suppressed.

The extension type MOS transistor shown in FIG. 21B has the same structure as that of the transistor shown in FIG. 21A, but also includes n-type source / drain regions 10a and p-type channel regions 16a. An n-type low-concentration source / drain region (n-type extension) 12a formed by introducing a low-concentration n-type impurity therebetween. Thus, the n-type low concentration source / drain region 12a (n-type extension) shallower than the n-type source / drain region 10a
Is provided inside the n-type source / drain region 10a, there is an advantage that the short channel effect can be improved as compared with a single gate drain type MOS transistor.

[0008] In addition, ex with a pocket shown in FIG.
The tension type MOS transistor is shown in FIG.
In addition to the configuration of the extension type MOS transistor shown in FIG.
) A p-type pocket region 15a for suppressing punch-through formed by introducing a p-type impurity below 12a. By providing the p-type pocket region 15a under the n-type low-concentration source / drain region 12a (n-type extension), the extension of the depletion layer from the n-type source / drain region 10a can be suppressed. Becomes possible,
Since punch-through can be suppressed, it is possible to further suppress the short channel effect.

Furthermore, the silicon substrate on which these MOS transistors are formed often employs a well structure usually called a retrograde well. The retrograde well has an impurity concentration peak deep in the silicon substrate, and has a low impurity concentration on the surface of the silicon substrate, and is usually formed by high-energy ion implantation. By adopting the retrograde well structure, the sheet resistance of the well can be reduced without increasing the impurity concentration near the MOS transistor formation region, so that the latch-up resistance can be improved.

FIGS. 22 (a) to 22 (f) show an example of a conventional method for manufacturing an n-channel MOS transistor.
An example of a method for manufacturing an S transistor (see FIG. 21C) will be described.

As shown in FIG. 1A, boron ions are implanted into a p-type silicon substrate 1 to form well impurity diffusion regions 2 for wells. The injection condition is that the acceleration energy is 300
At −2000 keV, the injection amount is 1 × 10 ¹³ to 1 × 10 ¹⁴
cm ^-2 . When implanted in such an energy range, the well impurity diffusion region 2 becomes a so-called retrograde well as described above. Next, boron ions are implanted into a region near the surface in the well impurity diffusion region 2,
The channel impurity diffusion region 16 is formed. The implantation conditions at this time are an acceleration energy of 20-60 keV and an implantation amount of 4-6 × 10 ¹² cm ⁻² .

Next, as shown in FIG. 1B, the surface of the p-type silicon substrate 1 is oxidized to form a gate insulating film 4 having a thickness of 8 to 12 nm.

Next, as shown in FIG. 22C, after a polysilicon film of 200 to 300 nm is deposited on the entire surface of the substrate, a gate electrode 5 is formed through a normal photo and etching process.

Next, as shown in FIG. 22D, low concentration arsenic ions are implanted into regions located on both sides of the gate electrode 5 in the p-type well 2a using the gate electrode 5 as a mask. Low concentration source / drain impurity diffusion region 12
To form The injection condition is such that the acceleration energy is 10-30.
At keV, the dose is 1-5 × 10 ¹⁴ cm ⁻² . Similarly, using the gate electrode 5 as a mask, boron fluoride ions are implanted into a region below the low-concentration source / drain impurity diffusion region 12 to form the pocket impurity diffusion region 1.
5 is formed. The implantation conditions at this time are as follows: the acceleration energy is 80-120 keV, and the implantation amount is 1-4 × 10 ¹³ cm.
^-2 .

Next, as shown in FIG. 22E, sidewalls 7 are formed on both side surfaces of the gate electrode 5.

Next, as shown in FIG. 22 (f), using the gate electrode 5 and the side wall 7 as a mask, the gate electrode 5 and regions located on both sides of the gate electrode 5 in the p-type well 2a are formed. High concentration arsenic ions are implanted to form source / drain impurity diffusion regions (not shown). Next, a heat treatment is performed at 850 ° C. for 30 minutes in order to activate the impurities introduced in each of the above steps and recover crystal defects, thereby forming a low-resistance n-type gate electrode 5 a and forming the n-type gate electrode 5 a in the p-type silicon substrate 1. , P-type well 2a, n-type source / drain region 16a, n-type low concentration source / drain region 12a (n-type extension), p-type pocket region 15a, and p-type channel region 16a.
However, when a silicon oxide film is deposited by CVD at a high temperature when forming the sidewalls 7, the impurities introduced up to that time are activated. In this case, in the step shown in FIG. 22E, the p-type well 2a, the n-type low-concentration source / drain region 12a, and the p-type pocket region 15a
Is formed. Then, in the step shown in FIG.
Well 2a, n-type low concentration source / drain region 12
The impurities in the a and p-type pocket regions 15a diffuse again.

By the way, if the implantation of boron fluoride ions in FIG. 22D is omitted, the extensio shown in FIG.
If an n-type MOS transistor is obtained and the implantation of boron fluoride ions and the implantation of arsenic ions are omitted, FIG.
1 is obtained.

[0018]

However, the above-mentioned conventional MOS type semiconductor device has the following problems.

(1) To form source / drain regions, n-type impurity ions are implanted in the case of an n-channel MOS transistor, and p-type impurities are implanted in the case of a p-channel MOS transistor. Although heat treatment is performed to activate the impurities, the desired shallow junction cannot be obtained because the impurities are accelerated and diffused due to point defects (vacancies and interstitial silicon) generated during the implantation. In a device having a small gate length, the interstitial silicon generated at the time of implantation is diffused toward the gate oxide film to form a concentration gradient of the interstitial silicon. Advection causes a so-called reverse short channel effect, which changes the threshold voltage.

(2) For the same reason, a desired shallow junction cannot be obtained even in a low concentration source / drain region (extension). Similarly, in the pocket region, at the time of heat treatment after the implantation of the impurity ions, point defects generated during the ion implantation accelerate and diffuse the impurities, thereby expanding the distribution region thereof, thereby effectively suppressing punch-through. It is difficult. In particular, when forming a sidewall formed after forming a low concentration source / drain region or a pocket region, a silicon oxide film is deposited by a normal CVD method at a temperature of 700 ° C. to 850 ° C. for several hours. However, in this process, the distance over which the impurity is diffused at a high speed is large, and it is difficult to realize a desired transistor structure. As in the case of forming the source / drain regions, in a device having a small gate length, the interstitial silicon generated at the time of implantation diffuses toward the gate oxide film and a concentration gradient of the interstitial silicon is formed. Impurities on the surface of the substrate in the region flow toward the surface, causing a so-called reverse short channel effect and changing the threshold voltage.

(3) In order to form a channel region,
After implanting n-type or p-type impurity ions, a gate oxidation step and a heat treatment for activating the impurity are performed. Since the region is wide, it is difficult to obtain a steep profile in the depth direction. For this reason, it becomes difficult to accurately achieve a preset threshold voltage with the miniaturization of semiconductor devices. In particular, when a retrograde well structure is employed as a well, if ions are implanted with high energy to form a well, point defects (vacancies and interstitial silicon) are generated deep in the semiconductor substrate. Among these point defects, interstitial silicon diffuses toward the surface of the semiconductor substrate by a subsequent heat treatment to form a concentration gradient, so that impurities on the surface of the substrate in the channel region migrate toward the surface and the semiconductor substrate in the channel region The impurity concentration on the surface increases, and the threshold voltage changes.

The present invention has been made in view of such a problem, and an object of the present invention is to provide an accurate threshold voltage by adopting a means for suppressing the spread of an impurity diffusion layer such as a source / drain region in the depth direction. An object of the present invention is to provide a semiconductor device equipped with a miniaturized transistor having a voltage and a method of manufacturing the same.

[0023]

To achieve the above object, according to the present invention, there is provided a semiconductor device according to the present invention, and a method of manufacturing a semiconductor device according to the present invention. And take measures.

According to a first aspect of the present invention, there is provided a semiconductor device, a first conductivity type substrate region formed in the semiconductor substrate, and a semiconductor substrate formed on the semiconductor substrate. A gate insulating film, a gate electrode formed on the gate insulating film, a source / drain region of a second conductivity type formed in regions located on both sides of the gate electrode in the semiconductor substrate, A carbon doped region formed at least in a region overlapping the source / drain region in the semiconductor substrate.

Thus, in the region overlapping with the carbon-doped region in the source / drain region, the interstitial atoms of the semiconductor constituting the semiconductor substrate are trapped by carbon. Therefore, the concentration of interstitial atoms in the source / drain regions is reduced, and the diffusion of the second conductivity type impurity that is diffused by forming a pair with the interstitial atoms is suppressed. As a result, it is possible to reliably prevent a short channel effect that is likely to appear as the semiconductor device becomes finer. Further, the spread of the source / drain region in the depth direction is suppressed, and the miniaturization in the depth direction according to the scaling rule becomes possible according to the miniaturization of the gate length of the semiconductor device.

According to a second aspect of the present invention, in the first aspect, the carbon-doped region is preferably formed only inside the source / drain region.

Since no carbon is introduced into the pn junction between the source / drain region and the substrate region, an increase in junction leakage can be reliably prevented.

According to a second aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a first conductivity type substrate region formed in the semiconductor substrate; and a semiconductor substrate formed on the semiconductor substrate. A gate insulating film, a gate electrode formed on the gate insulating film, a source / drain region of a second conductivity type formed in regions located on both sides of the gate electrode in the semiconductor substrate, A second conductivity type low-concentration source / drain region formed in a region between the source / drain region and a region located immediately below the gate electrode in the substrate region; And a carbon-doped region formed in the overlapping region.

Thus, since carbon is introduced into the low-concentration source / drain regions, the spread of the low-concentration source / drain regions is suppressed by the above-described action, and the short channel effect which is likely to appear with miniaturization of a semiconductor device. Can be reliably prevented. Further, since the concentration gradient of excessive interstitial atoms in the source / drain region or the low-concentration source / drain region in the direction of the gate insulating film can be suppressed, the occurrence of the reverse short channel effect can be suppressed.

According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the first region is formed in a region below the low concentration source / drain region and in contact with the low concentration source / drain region.
The device may further include a conductivity type pocket region, wherein the carbon-doped region is formed over a part of the pocket region.

Thus, the spread of the impurity distribution in the pocket region can be suppressed. Therefore, in addition to the function and effect of the third aspect, it is possible to suppress the short channel effect due to the pocket region and suppress the increase in the diffusion capacitance.

According to a fifth aspect of the present invention, in the third aspect, it is preferable that the carbon-doped region is formed only inside the low-concentration source / drain region.

Thus, since no carbon is introduced into the pn junction between the low-concentration source / drain region and the substrate region, an increase in junction leakage can be reliably prevented.

According to a sixth aspect of the present invention, in the semiconductor device according to the fifth aspect, the first region is formed in a region below the low concentration source / drain region and in contact with the low concentration source / drain region.
A pocket region of a conductivity type may be further provided.

Thus, the same function and effect as the fourth aspect can be obtained.

According to a third aspect of the present invention, a semiconductor substrate, a first conductivity type substrate region formed in the semiconductor substrate, and a semiconductor substrate formed on the semiconductor substrate are provided. A gate insulating film, a gate electrode formed on the gate insulating film, a source / drain region of a second conductivity type formed in regions located on both sides of the gate electrode in the semiconductor substrate, A channel region including a threshold control level impurity formed in a region located immediately below the gate electrode in the semiconductor substrate; and a carbon doped region formed in a region overlapping at least the channel region. ing.

As a result, the spread of the impurity distribution in the direction of the gate insulating film in the channel region can be suppressed, so that a steep impurity distribution in the depth direction can be obtained. The value can be kept high. In addition, since the carbon introduced into the channel region suppresses the concentration gradient of excessive interstitial atoms in the source / drain region toward the gate insulating film, it is possible to prevent the impurity concentration near the substrate surface from becoming excessively high. It is possible to prevent the occurrence of the reverse short channel effect.

As described in claim 8, in claim 7, the carbon-doped region is preferably formed only inside the channel region.

Thus, since no carbon is introduced into the pn junction, an increase in junction leakage can be reliably prevented.

According to a ninth aspect, in the eighth aspect, it is preferable that the carbon-doped region is separated from the gate insulating film.

Thus, even when the gate insulating film is formed of an oxide film, there is no fear that carbon is taken into the oxide film. Therefore, the operation and effect of claim 8 can be obtained while reliably preventing the withstand voltage of the gate insulating film from deteriorating.

According to a fourth aspect of the present invention, there is provided a semiconductor device comprising:
A semiconductor substrate; a first conductivity type well region formed in the semiconductor substrate; a gate insulating film formed above the well region and on the semiconductor substrate; A gate electrode formed on an insulating film, a second conductivity type source / drain region formed to be in contact with a region located on both sides of the gate electrode in the semiconductor substrate at the lower end with the well region, A channel region which is formed to be in contact with the well region at the lower end thereof in a region located between the source and the drain in the semiconductor substrate and contains a threshold control level impurity, and a part of a depth in the well region. And a carbon-doped region formed in a region separated from the channel region and the source / drain region.

This suppresses the diffusion of interstitial atoms generated near the region where the impurity concentration in the well region becomes maximum to the substrate surface, thereby suppressing the inclination of the interstitial atom concentration near the channel region. Can be. Therefore, the impurity distribution in the channel region in the depth direction can be kept steep, and in a miniaturized semiconductor device, the occurrence of the inverse short channel effect and the decrease in the saturation current value can be suppressed.

As set forth in claim 11, claim 1
At 0, the peak position of the carbon concentration in the carbon-doped region is preferably shallower than the peak position of the impurity concentration of the first conductivity type in the well region.

Thus, the diffusion of interstitial atoms in the well region in the direction of the channel region can be more reliably suppressed.

The first method of manufacturing a semiconductor device according to the present invention
13. A first step of forming a substrate region of a first conductivity type in a semiconductor substrate, and forming a gate insulating film and a gate electrode above the substrate region and on the semiconductor substrate. A second step of introducing a second conductivity type impurity into the semiconductor substrate by using at least the gate electrode as a mask, the impurity being located above the substrate region and on both sides of the gate electrode in the semiconductor substrate. A third step of forming a source / drain impurity diffusion region in the region, and after or before the third step, carbon is introduced into the semiconductor substrate using at least the gate electrode as a mask; A fourth step of forming a carbon-doped region in a region overlapping with the impurity diffusion region for the drain, and performing a heat treatment on the semiconductor substrate to form at least the source-drain region; The second conductivity type impurity of use impurity diffusion region and a fifth step of activating.

According to this method, when activating the second conductivity type impurity in the source / drain impurity diffusion region in the fifth step, the diffusion of the second conductivity type impurity is caused by the above-mentioned action due to the presence of carbon. Is suppressed. That is,
Even in the case of forming a fine semiconductor device, it is possible to increase the impurity concentration of the source / drain regions to be formed and to reduce the depth thereof, so that the size can be reduced not only in the lateral direction but also in the depth direction, and A semiconductor device with a small short channel effect is formed.

As set forth in claim 13, claim 1
2, In the fourth step, it is preferable that the carbon-doped region is formed only inside the source / drain impurity diffusion region.

According to this method, a semiconductor device having a small junction leak can be reliably obtained.

As set forth in claim 14, claim 1
2, further comprising a step of forming sidewalls on both side surfaces of the gate electrode after the second step and before the third step, wherein in the third step, the gate electrode and the side electrode are formed. Introducing a second conductivity type impurity into the substrate region using the wall as a mask, and introducing carbon into the substrate region using the gate electrode and the sidewall as a mask in the fourth step. it can.

According to this method, the channel length can be appropriately adjusted according to the type of the semiconductor device.

As set forth in claim 15, claim 1
3, after the second step and before the third step, a low-concentration second conductivity type impurity is introduced into the substrate region using the gate electrode as a mask; Forming a low-concentration source / drain impurity diffusion region in regions located on both sides of the gate electrode; and, in the fourth step, introducing carbon into the substrate region using the gate electrode as a mask. can do.

According to this method, carbon is introduced into the low-concentration source / drain impurity diffusion regions and the low-concentration source / drain impurity diffusion regions, so that carbon is formed during the heat treatment for activation in the fifth step. Since the spread of the impurity distribution in the lateral and vertical directions of the source / drain region and the low-concentration source / drain region is suppressed, a semiconductor device with small short-channel effect and reverse short-channel effect can be obtained. Further, since the concentration gradient of excessive interstitial atoms in the direction of the gate insulating film is also suppressed, a semiconductor device with less occurrence of the inverse short channel effect can be obtained.

As described in claim 16, claim 1
5, after the second step and before the third step, a first conductivity type impurity is introduced into the substrate region using the gate electrode as a mask, and the low concentration source in the substrate region is introduced. The method may further include a step of forming a pocket region below the drain impurity diffusion region and in a region adjacent to the low-concentration source / drain region.

According to this method, a semiconductor device having a smaller short channel effect and a smaller diffusion capacitance is formed.

According to the second method of manufacturing a semiconductor device of the present invention,
A first step of forming a substrate region of the first conductivity type in the semiconductor substrate, and introducing a threshold control level impurity into the semiconductor substrate, A second step of forming a channel impurity diffusion region in a region near the surface, and after or before the second step, carbon is introduced into the semiconductor substrate to form the channel impurity diffusion region in the semiconductor substrate. A third step of forming a carbon-doped region in a region overlapping with the region, a fourth step of forming a gate insulating film and a gate electrode on the channel impurity diffusion region, and using at least the gate electrode as a mask A second conductivity type impurity is introduced into the semiconductor substrate to form source / drain impurity diffusion regions in regions located on both sides of the gate electrode in the semiconductor substrate. And step, a heat treatment of the semiconductor substrate, and a sixth step of activating the impurity introduced into the respective impurity diffusion regions.

According to this method, since carbon is introduced into the impurity diffusion region for the channel, at the time of the sixth step, the spread of the impurity distribution in the depth direction of the channel region to be formed is suppressed, and the sharp concentration is improved. A channel region having a distribution is formed. Therefore, even when a fine semiconductor device is formed, a semiconductor device having a large saturation current value and a small short-channel effect is formed.

As set forth in claim 18, claim 1
7, in the third step, it is preferable to implant carbon ions at an acceleration energy such that the carbon-doped region is formed apart from the surface of the semiconductor substrate.

According to this method, in the sixth step and the like,
There is no danger that carbon will enter the gate insulating film. Therefore, even in a semiconductor device having a gate insulating film formed of an oxide film, a semiconductor device having a high withstand voltage of the gate insulating film is formed.

The third method of manufacturing a semiconductor device according to the present invention
As set forth in claim 19, a first step of epitaxially growing a semiconductor single crystal containing carbon on a semiconductor substrate to form a carbon-doped epilayer, and epitaxially growing a semiconductor single crystal on the carbon-doped epilayer. A second step of forming a surface epi layer, and forming a channel impurity diffusion region by introducing a threshold control level of impurity ions into the surface epi layer and a region including at least a part of the carbon doped epi layer. A third step, a fourth step of forming a gate insulating film and a gate electrode on the channel impurity diffusion region, and forming at least the surface epi layer and the carbon doped epi layer using the gate electrode as a mask. A second conductivity type impurity is introduced and located on both sides of the gate electrode in the surface epi layer and the carbon doped epi layer. A fifth step of forming an impurity diffusion region for the source and drain to pass, a heat treatment of the semiconductor substrate, and a sixth step of activating the impurity introduced into the respective impurity diffusion regions.

According to this method, a surface epi layer into which carbon has not been introduced exists between the carbon-doped epi layer and the gate insulating film. Therefore, in the sixth step or the like, carbon is reliably prevented from entering the gate insulating film, and even when a fine semiconductor device is formed, the short channel effect and the reverse short channel effect are small and the saturation current value is large. In addition, a semiconductor device having a good gate insulating film withstand voltage can be reliably obtained.

The fourth method of manufacturing a semiconductor device according to the present invention
A first step of implanting a first conductivity type impurity ion into a semiconductor substrate to form an impurity diffusion region for a well, and forming an impurity at a threshold control level in the semiconductor substrate. Introducing a second step of forming a channel impurity diffusion region in a region near the surface of the semiconductor substrate, and after or before the second step, implanting carbon ions into the semiconductor substrate, A third step of forming a carbon-doped region in a region including a part of a depth of the well impurity diffusion region and separated from the channel impurity diffusion region; and a gate insulating film on the channel impurity diffusion region. And a fourth step of forming a gate electrode, and introducing a second conductivity-type impurity into the semiconductor substrate using at least the gate electrode as a mask, and forming both gate electrodes in the semiconductor substrate. A fifth step of forming a source / drain impurity diffusion region in a region located on the other side and a sixth step of performing a heat treatment on the semiconductor substrate to activate the impurities introduced into the impurity diffusion regions. Have.

According to this method, a carbon-doped region is formed in a part of the depth of the well impurity diffusion region.
In the step, excessive diffusion of interstitial atoms existing in the well region in the channel direction is suppressed. Therefore,
Even when a fine semiconductor device is formed, a semiconductor device having a large saturation current value and almost no reverse short-channel effect is formed.

As described in claim 21, claim 2
At 0, the position where the carbon concentration in the carbon-doped region is maximum is above the position where the first conductivity type impurity concentration in the well impurity diffusion region is maximum.

According to this method, the operation and effect of the twentieth aspect can be reliably obtained.

According to a fifth method of manufacturing a semiconductor device of the present invention,
23. A first step of epitaxially growing a carbon-doped semiconductor single crystal on a semiconductor substrate to form a carbon-doped epilayer, and epitaxially growing a semiconductor single crystal on the carbon-doped epilayer. A second step of forming a surface epilayer by implanting impurity ions of the first conductivity type into a region extending over the surface epilayer, the carbon-doped epilayer, and a part of the semiconductor substrate. A third step of forming a region, a fourth step of implanting impurity ions at a threshold control level above the surface epilayer to form a channel impurity diffusion region, and a step of forming the channel impurity diffusion region. A fifth step of forming a gate insulating film and a gate electrode thereon, and using a second conductive type impurity in the surface epi layer using at least the gate electrode as a mask. A sixth step of introducing and forming a source / drain impurity diffusion region in a region located on both sides of the gate electrode in the surface epi layer, and performing a heat treatment on the semiconductor substrate to form the impurity diffusion region in each of the impurity diffusion regions. A seventh step of activating the introduced impurities.

According to this method, it is possible to easily and accurately control the position in the depth direction of the region where carbon is introduced in the semiconductor substrate. Therefore, in the seventh step, the excessive interstitial atoms in the well region are surely suppressed from diffusing in the channel direction due to the presence of the carbon-doped epilayer. Even when a fine semiconductor device is formed, the saturation current value can be reduced. And a semiconductor device having little reverse short channel effect is formed.

[0068]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment relating to a field effect transistor will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 1 is a cross-sectional view of an n-channel MOS transistor having a carbon-doped region, and FIGS. 2A to 2D are cross-sectional views illustrating the manufacturing steps.

As shown in FIG. 1, on a p-type silicon substrate (or p-type well) 1, a gate insulating film 4 made of a silicon oxide film and a gate electrode 5 made of a polysilicon film are provided.
a are formed, and sidewalls 7 made of a silicon oxide film are formed on both side surfaces of the gate electrode 5a. Further, n-type source / drain regions 10a formed by introducing high-concentration n-type impurities are formed in regions located on both sides of the gate electrode 5a in the p-type silicon substrate 1.
Are formed. A feature of the present embodiment is that a carbon-doped region Rcd is formed in the source / drain region 10a and in the surrounding region.

Generally, carbon in a silicon substrate has a function of trapping interstitial silicon atoms, which are point defects generated in the silicon substrate. Is reduced. On the other hand, impurities such as phosphorus, arsenic, and boron diffuse in the silicon substrate by pairs with interstitial silicon atoms, so that diffusion of the impurities is suppressed in the carbon-doped region in the silicon substrate. Therefore, if the carbon-doped region Rcd exists inside and around the n-type source / drain region 10a as in the present embodiment,
Diffusion in the depth direction and the lateral direction of the n-type source / drain region 10a is effectively suppressed, and the short channel effect can be effectively suppressed by forming the shallow source / drain region 10a.

The carbon-doped region Rcd also suppresses the concentration gradient of excessive interstitial silicon generated in the n-type source / drain region 10a in the direction of the gate oxide film.
The occurrence of the reverse short channel effect can be suppressed.

Next, the n-channel type MO according to this embodiment will be described.
The manufacturing process of the S transistor will be described.

First, as shown in FIG. 2A, the surface of a p-type silicon substrate 1 is oxidized to form a gate insulating film 4 made of a silicon oxide film having a thickness of 8 to 12 nm. next,
After a polysilicon film having a thickness of 200 to 300 nm is deposited on the entire surface of the substrate, the gate electrode 5 is formed through a normal photo and etching process.

Next, as shown in FIG. 2B, sidewalls 7 are formed on both side surfaces of the gate electrode 5 by depositing a silicon oxide film and etching back the silicon oxide film by anisotropic etching.

Next, as shown in FIG. 2C, using the gate electrode 5 and its side wall 7 as a mask, the gate electrode 5 and regions located on both sides of the gate electrode in the silicon substrate are formed. Arsenic ions are implanted to form source / drain impurity diffusion regions 10. The implantation conditions are as follows: the acceleration energy is 30-40 keV, and the implantation amount is 5 × 10 ¹⁵
cm- ² .

Next, as shown in FIG. 2D, using the gate electrode 5 and the side wall 7 as a mask, the gate electrode 5 and regions located on both sides of the gate electrode 5 in the silicon substrate 1 are formed. To form a carbon-doped region Rcd. The injection condition is that the acceleration energy is 1
At 0-20 keV, the dose is about 1 × 10 ¹⁵ cm ⁻² (preferably in the range of 3 × 10 ¹⁴ −2 × 10 ¹⁵ cm ⁻² ). At this time, the carbon-doped region Rcd is the source / drain impurity diffusion region 10 doped with arsenic ions.
And an area surrounding the inside.

Next, in the state shown in FIG. 2D, at 850 ° C. and 30 ° C., in order to activate impurities and recover crystal defects.
Minute heat treatment to form a low-resistance n-type gate electrode 5a.
And an n-type source / drain region 10a. At this time, since the source / drain impurity diffusion region 10 into which arsenic ions are implanted and the carbon-doped region Rcd overlap, diffusion of arsenic during heat treatment is suppressed, and the n-type source / drain region 10a is made shallow. it can. That is, while increasing the impurity concentration in the n-type source / drain region 10a, the depth of the n-type source / drain region 10a is reduced to a size close to the size according to the scaling law in accordance with the reduction in the gate length. It becomes possible.

However, in this embodiment and each of the following embodiments, when a high-temperature treatment equivalent to the heat treatment for activation is performed before the heat treatment for activation is performed, the impurities introduced up to that time are not activated. May be done. For example, in forming the sidewall 7 in the step shown in FIG. 2B, if a silicon oxide film is deposited on the entire surface by a normal CVD method, it is exposed to a high temperature for a long time. In this case, CV
Step D also functions as a heat treatment for activation. However, when a silicon oxide film is deposited by a low-temperature CVD method, impurities are not activated. Therefore, the heat treatment referred to in each claim is a concept including a treatment by a high-temperature CVD method and the like.

(Second Embodiment) Next, a second embodiment will be described. FIG. 3 shows n in the second embodiment.
FIG. 3 is a cross-sectional view of a channel-channel MOS transistor.

As shown in the figure, in the n-channel MOS transistor according to the present embodiment, the carbon doped region Rcd of the transistor according to the first embodiment is formed only inside the n-type source / drain 10a. I have.

Generally, the interstitial silicon atoms trapped by carbon in the carbon-doped region Rcd form a cluster of carbon and silicon atoms. Therefore, such a cluster is formed in the vicinity of the pn junction (particularly, p with a low impurity concentration).
If the depletion layer is widened, the pn junction leakage may be increased when the depletion layer is spread. That is, as in the first embodiment, the p-type region between the n-type source / drain region 10a and the p-type silicon substrate 1 (substrate region) is removed.
If the n-junction is included in the carbon-doped region Rcd, it cannot be said that junction leakage does not increase depending on the type of transistor and operating conditions.

Therefore, since the carbon-doped region Rcd exists inside the source / drain impurity diffusion region 10 as in the present embodiment, the generation of clusters on the p-type silicon substrate 1 near the pn junction is prevented. Can be suppressed, p
Short channel characteristics can be improved while reliably suppressing n-junction leakage.

Although the description of the manufacturing process of the transistor according to the present embodiment is omitted, in the process shown in FIG. 2D, the acceleration energy at the time of implanting carbon ions is slightly weakened. Can be easily realized.

(Third Embodiment) Next, a third embodiment will be described. FIG. 4 is a sectional view of an n-channel MOS transistor according to the third embodiment.

The transistor according to this embodiment has a so-called LDD structure, unlike the transistor according to the first embodiment. That is, the n-type source / drain region 10a into which high concentration arsenic is introduced and the gate electrode 5a
An n-type low-concentration source / drain region (n-type extension) 12a formed by introducing a low-concentration n-type impurity is provided between the region and the region (channel region) located immediately below. The other basic configuration of the MOS transistor is the same as that of the first embodiment. The feature of this embodiment is that a carbon soap and a region Rcd are formed in a region including the n-type low concentration source / drain region 12a. The carbon-doped region Rcd is also formed inside the n-type source / drain region 10a doped with a high-concentration n-type impurity.

As described above, diffusion of impurities is suppressed in the carbon soap and the region Rcd. In the present embodiment, since the n-type low-concentration source / drain regions 12a are doped with carbon, diffusion of the n-type low-concentration source / drain regions 12a in the depth direction and the lateral direction is effectively suppressed. , Short channel characteristics are improved.

Further, since the carbon-doped region Rcd partially overlaps with the n-type source / drain regions 10a, diffusion of the n-type source / drain in the depth direction and the lateral direction is also suppressed, and the short channel characteristics are further improved. You.

In this embodiment, the carbon doped region R
The carbon in cd is the n-type low concentration source / drain region 12
The concentration gradient of excessive interstitial silicon in the a and n-type source / drain regions 10a in the direction of the gate oxide film is suppressed. Therefore, it is possible to effectively prevent the impurity concentration near the substrate surface in the channel region from being excessively increased by the interstitial silicon, and to suppress the occurrence of the reverse short channel effect such as an increase in the threshold voltage. it can.

Next, the n-channel type MO according to this embodiment
FIG. 5A shows the manufacturing process of the S transistor.
This will be described with reference to FIG.

First, as shown in FIG. 5A, the surface of the p-type silicon substrate 1 is oxidized to form a gate insulating film 4 made of a silicon oxide film having a thickness of 8 to 12 nm. next,
After a polysilicon film having a thickness of 200 to 300 nm is deposited on the entire surface of the substrate, the gate electrode 5 is formed through a normal photo and etching process.

Next, as shown in FIG. 5B, arsenic ions are implanted into the gate electrode 5 and regions located on both sides of the gate electrode 5 in the silicon substrate using the gate electrode 5 as a mask. Source / drain impurity diffusion region 10
To form The injection condition is such that the acceleration energy is 10-30.
At keV, the implantation amount is about 1-5 × 10 ¹⁴ cm ⁻² .

Next, as shown in FIG. 5C, using the gate electrode 5 as a mask, carbon ions are implanted into the gate electrode 5 and regions located on both sides of the gate electrode 5 in the silicon substrate 1. Implantation is performed to form a carbon-doped region Rcd.
The implantation conditions are as follows: the acceleration energy is 10-20 keV, and the implantation amount is about 1 × 10 ¹⁵ cm ⁻² (3 × 10 ¹⁴ −2 ×
A range of 10 ¹⁵ cm ^-2 is preferred). At this time, the carbon-doped region Rcd extends over the inside of the source / drain impurity diffusion region 10 doped with arsenic ions and a region surrounding the inside.

Next, as shown in FIG. 5D, sidewalls 7 are formed on both side surfaces of the gate electrode 5 by depositing a silicon oxide film and etching back the silicon oxide film by anisotropic etching. Further, in the state shown in FIG. 5D, a heat treatment at 850 ° C. for 30 minutes is performed to activate each impurity and recover crystal defects, thereby forming a low resistance n.
Gate electrode 5a and n-type source / drain region 10a
And n-type low concentration source / drain regions (n-type extension
) 12a. At this time, the source / drain impurity diffusion region 10 and the carbon-doped region Rcd overlap with each other. The spread in the lateral direction is suppressed. Therefore, the short channel effect and the inverse short channel effect can be reliably suppressed.

However, as described above, if the same high-temperature treatment is performed before the heat treatment for activation is performed, the impurities introduced up to that time are activated. In the step shown in FIG.
When a silicon oxide film is deposited on the entire surface by a normal CVD method during the formation of
00-850 ° C for several hours). When such high-temperature CVD is used, the n-type low-concentration source / drain regions 12a are formed at that time. However, in this embodiment, since the carbon-doped region Rcd is formed, the high-temperature Even if a trivial CVD process is performed, the spread of the impurity distribution in the n-type low concentration source / drain region 12a can be sufficiently suppressed.

(Fourth Embodiment) Next, a fourth embodiment will be described. FIG. 6 is a sectional view of an n-channel MOS transistor having an LDD structure according to the present embodiment.

As shown in the figure, the basic structure of the transistor according to the present embodiment is the same as the structure of the transistor according to the third embodiment. However, in the present embodiment, the carbon-doped region Rcd is formed over the inside of the n-type low-concentration source / drain region 12a and the inside of the n-type source / drain region 10a.

In the present embodiment, the carbon-doped region Rcd does not exist at the pn junction between the low-concentration source / drain region 12a and the substrate region as compared with the third embodiment, and therefore, the second embodiment The function similar to that of the embodiment makes it possible to suppress the generation of clusters on the p-type silicon substrate side near the pn junction. Therefore, short channel characteristics can be improved while suppressing pn junction leakage.

Although the description of the manufacturing process of the transistor according to this embodiment is omitted, the process shown in FIG.
It can be easily realized by slightly weakening the acceleration energy when implanting carbon ions.

(Fifth Embodiment) Next, a fifth embodiment will be described. FIG. 7 is a sectional view of the n-channel MOS transistor according to the present embodiment.

As shown in the figure, the transistor according to the present embodiment also has n-type low concentration source / drain regions (n-type exte
The structure of the transistor according to the third and fourth embodiments is the same as that of the transistor according to the third and fourth embodiments. However, in this embodiment, the sidewalls are eliminated in the final finished state, and low-resistance silicide layers 21a and 21b are formed on the gate electrode 5a and the n-type source / drain regions 10a, respectively. ing.
The carbon-doped region Rcd is formed in each silicide layer 21.
a, 21b are formed by implantation of carbon ions using the n-type low-concentration source / drain regions 12a as masks.
Is formed only in the region around it.

In the present embodiment, the resistance of the gate electrode and the n-type source / drain regions can be reduced in addition to the suppression of the short channel effect.

(Sixth Embodiment) Next, a sixth embodiment will be described. FIG. 8 is a sectional view of the n-channel MOS transistor according to the present embodiment.

As shown in the figure, the structure of the transistor according to the present embodiment is basically the same as the structure of the transistor according to the fifth embodiment. However, in the present embodiment, the carbon-doped region Rcd is formed only inside the n-type low-concentration source / drain region 12a, and between the n-type low-concentration source / drain region 12a and the silicon substrate 1 (substrate region). No carbon has been introduced into the pn junction of. Therefore, there is an advantage that an increase in junction leak can be avoided as compared with the fifth embodiment.

In particular, since no carbon-doped region Rcd is formed in the n-type source / drain region 10a, n
This structure is advantageous when it is desired to suppress only the diffusion of impurities in the n-type low concentration source / drain regions 12a without affecting the diffusion of impurities in the source / drain regions 10a.

Next, a method for manufacturing an n-channel MOS transistor according to this embodiment will be described with reference to FIGS.

First, as shown in FIG. 9A, the surface of the p-type silicon substrate 1 is oxidized to form a gate insulating film 4 made of a silicon oxide film having a thickness of 8 to 12 nm. next,
After a polysilicon film having a thickness of 200 to 300 nm is deposited on the entire surface of the substrate, the gate electrode 5 is formed through a normal photo and etching process. Next, sidewalls 7 are formed on both side surfaces of the gate electrode 5 by depositing a silicon oxide film and etching back the silicon oxide film by anisotropic etching.
To form

Next, arsenic ions are implanted into the gate electrode 5 and regions located on both sides of the gate electrode in the silicon substrate by using the gate electrode 5 and its side wall 7 as a mask, and the source / drain An impurity diffusion region 10 is formed. The injection condition is that the acceleration energy is 30-40k.
In eV, the implantation amount is about 5 × 10 ¹⁵ cm ⁻² .

Next, as shown in FIG. 9B, the side wall 7 is selectively over-etched to retreat the side wall 7.

Next, as shown in FIG. 9C, a refractory metal film (for example, a titanium film) is formed on the exposed surface of the silicon substrate 1 and on the gate electrode 5 and then silicidized. After reacting with the exposed silicon to form a silicide layer, the titanium film is removed, and a heat treatment is further performed to form a silicide layer 21 a on the gate electrode 5 and the source / drain impurity diffusion region 10. , 21b.

Next, as shown in FIG. 9D, after removing the sidewalls 7, the respective silicide layers 21a and 21b are removed.
Is used as a mask to implant low-concentration phosphorus ions into the substrate,
A low concentration source / drain impurity diffusion region is formed (not shown). The injection condition is such that the acceleration energy is 10-3.
At 0 keV, the injection amount is about 1-5 × 10 ¹⁴ cm ⁻² . Further, using the silicide layers 21a and 21b as a mask, carbon ions are implanted into the substrate to form carbon doped regions R.
forming a cd. The injection conditions are as follows:
At 20 keV, the dose is about 1 × 10 ¹⁵ cm ⁻² (preferably in the range of 3 × 10 ¹⁴ −2 × 10 ¹⁵ cm ⁻² ).
Thereafter, a heat treatment is performed at 850 ° C. for 30 minutes in order to activate each impurity and recover crystal defects, to thereby obtain a low-resistance n.
Gate electrode 5a and n-type source / drain region 10a
And n-type low concentration source / drain regions (n-type extension
) 12a.

Through the above steps, the n-type low concentration source
Only in the inside of the drain region 12a is the carbon doped region Rcd
Can be formed. When the carbon-doped region Rcd may extend over the n-type source / drain region 10a as in the fifth embodiment, it is not necessary to perform the sidewall retreating process shown in FIG. 9B.

In this embodiment, arsenic in the gate electrode 5 and the source / drain impurity diffusion region 10 is activated because the temperature is maintained at a high temperature when silicidation is performed.

(Seventh Embodiment) Next, a seventh embodiment will be described. FIG. 10 shows n according to the seventh embodiment.
It is sectional drawing of a channel type MOS transistor.

As shown in the figure, the transistor according to the present embodiment has an n-type low-concentration source / drain region (n-type extension) in addition to the structure of the transistor according to the third embodiment (see FIG. 4). P) formed below 12a
A mold pocket region 15a is provided. However, since the region where the carbon-doped region Rcd is formed is the same as that of the third embodiment, a part of the p-type pocket region 15a is also doped with carbon.

Therefore, in this embodiment, the same effect as that of the third embodiment can be obtained, and in addition, since the carbon-doped region Rcd overlaps a part of the p-type pocket region 15a, The spreading of the impurity distribution in the mold pocket region 15a can be suppressed. Therefore, it is possible to effectively suppress the short channel effect and also suppress an increase in the diffusion capacitance.

Although description of the manufacturing process in this embodiment is omitted, carbon ions are implanted in the process shown in FIG. 22D in the conventional manufacturing process (see FIGS. 22A to 22F). This can be easily realized.

(Eighth Embodiment) Next, an eighth embodiment will be described. FIG. 11 is a cross-sectional view of the n-channel MOS transistor according to the present embodiment.

As shown in FIG. 11, the p-type silicon substrate 1
(Or p-type well), the gate insulating film 4 and n
A gate electrode 5a is formed, and an n-type source / drain region 10a is formed in the silicon substrate 1. Further, a p-type impurity at a threshold control level is introduced into a region located immediately below the n-type gate electrode 5a in the silicon substrate 1 to form a channel p-type semiconductor region (hereinafter referred to as a p-type channel region) 16a. Is formed. And
The feature of this embodiment is that the n-type source / drain region 1
0a and a channel region 16a, and a carbon-doped region R in which carbon is introduced into a region including a substrate region below both.
cd is formed.

As described above, since carbon in the carbon-doped region Rcd suppresses diffusion of impurities, the carbon-doped region Rcd has the p-type channel region 16a and the n-type
If the n-type source / drain 10a is included, the p-type channel region 16a having a steep depth distribution is suppressed by suppressing the spread of the impurity distribution in the p-type channel region 16a, and at the same time, the n-type source / drain 10a is formed. Diffusion in the depth direction and the lateral direction of the drain region 10a is effectively suppressed. as a result,
It is possible to improve short channel characteristics while securing a high saturation current value.

Further, the carbon-doped region Rcd suppresses the concentration gradient of excessive interstitial silicon generated in the n-type source / drain region 10a toward the gate oxide film.
The effect of suppressing the occurrence of the inverse short channel effect can also be exhibited.

In the present embodiment, the p-type channel region is taken as an example of the channel region, but the same effect can be exerted in the case of the n-type channel region.

(Ninth Embodiment) Next, a ninth embodiment will be described. FIG. 12 is a sectional view of the n-channel MOS transistor according to the present embodiment.

As shown in the figure, the structure of the transistor according to the present embodiment is almost the same as the structure of the transistor according to the eighth embodiment. However, in the eighth embodiment shown in FIG. 11, the doped region Rcd is in contact with the surface of the p-type silicon substrate 1, but in the present embodiment, the carbon doped region Rcd is located near the surface of the p-type silicon substrate 1. It is formed so as not to include the region, that is, not to be in contact with the surface of the p-type silicon substrate 1.

Normally, the gate insulating film 4 is formed of a silicon oxide film formed by oxidizing the surface of the p-type silicon substrate 1. However, as in the eighth embodiment, the carbon doped region Rcd has a gate insulating film. When in contact with the film 4, carbon is taken into the oxide film, and the breakdown voltage of the gate oxide film may be deteriorated. Therefore, since the carbon-doped region Rcd is formed so as not to be in contact with the surface of the p-type silicon substrate 1 as in this embodiment, the same effect as in the eighth embodiment can be obtained without deteriorating the breakdown voltage of the gate oxide film. Can be demonstrated.

However, when the gate insulating film is made of a material other than the silicon oxide film, the carbon doped region R
Even if cd is in contact with the surface of the p-type silicon substrate 1, it does not cause deterioration of the breakdown voltage or the like.

Next, the manufacturing process of the n-channel MOS transistor according to the present embodiment will be described with reference to FIG.
This will be described with reference to (a) to (e).

As shown in FIG. 13A, boron ions having a concentration of a threshold control level are implanted into a region near the surface of the p-type silicon substrate 1 so that the channel impurity diffusion region
6 is formed. The injection condition is such that the acceleration energy is 20-6.
At 0 keV, the dose is 4-6 × 10 ¹² cm ⁻² .

Next, as shown in FIG. 13B, carbon ions are implanted into the p-type silicon substrate 1 to partially overlap the channel impurity diffusion region 16 into which the p-type impurity is introduced, and The carbon-doped region Rcd is formed so as not to contact the surface of the substrate 1. At this time, the implantation conditions of the carbon ions are such that the acceleration energy is about 30 keV and the implantation amount is about 1 × 10 ¹⁵ cm ⁻² (3 × 10 ¹⁴ to 2 × 10 ^15).
cm ^-2 is preferred).

Next, as shown in FIG. 13C, the surface of the p-type silicon substrate 1 is oxidized to form a gate insulating film 4 having a thickness of 8 to 12 nm.

Next, as shown in FIG. 13D, after a polysilicon film having a thickness of 200 to 300 nm is deposited on the entire surface, the gate electrode 5 is subjected to ordinary photo and etching steps.
To form Next, sidewalls 7 are formed on both side surfaces of the gate electrode 5.

Next, as shown in FIG. 13E, using the gate electrode 5 and the side wall 7 as a mask, the gate electrode 5 and regions located on both sides of the gate electrode 5 in the p-type silicon substrate 1 are formed. And then implant high concentration arsenic ions,
The source / drain impurity diffusion region 10 is formed. At this time, the source / drain impurity diffusion region 10 into which arsenic ions are introduced is shallower than the carbon-doped region Rcd.
The implantation conditions are such that the acceleration energy is 30 to 40 keV and the implantation amount is about 5 × 10 ¹⁵ cm ⁻² . Next, at 850 ° C. to activate the introduced impurities and recover crystal defects.
By performing a heat treatment for 30 minutes, the gate electrode 5 is turned into a low-resistance n-type gate electrode 5a.
p-type channel region 16a and n-type source / drain region 1
0a.

However, when a silicon oxide film is deposited by a normal CVD method in the step shown in FIG. 13D, boron in the channel impurity diffusion region 16 is activated and diffused at that time. However, even in that case, the presence of the carbon-doped region Rcd can exert the above-described effects. The same applies to the below-described tenth to thirteenth embodiments.

(Tenth Embodiment) Next, a tenth embodiment will be described. FIG. 14 is a diagram illustrating n according to the present embodiment.
It is sectional drawing of a channel type MOS transistor.

As shown in the figure, a p-type well 2 a is formed in a p-type silicon substrate 1.
a, a carbon-doped epitaxial region Rc formed by doping carbon simultaneously with the epitaxial growth of a silicon single crystal.
de is provided. Then, a surface epilayer 31 made of a silicon single crystal containing no carbon is formed on the carbon-doped epiregion Rcde. Further, the p-type channel region 16a and the n-type source / drain region 10 extend over the surface epi layer 31 and the carbon-doped epi region Rcde.
a are formed. Other configurations are the same as those in the ninth embodiment.

The transistor according to the present embodiment has essentially the same structure as the transistor according to the ninth embodiment in that the carbon-doped epi region Rcde is not in contact with the substrate surface. Therefore, the same effects as those of the ninth embodiment can be exerted.

Next, the n-channel type MO according to this embodiment will be described.
FIG. 15A shows the manufacturing process of the S transistor.
This will be described with reference to FIG.

First, as shown in FIG. 15 (a), a silicon single crystal is epitaxially grown on a p-type silicon substrate 1 while doping carbon to form a carbon-doped epi region Rcde.

Next, as shown in FIG. 15B, a silicon single crystal is epitaxially grown on the carbon-doped epi-region Rcde without doping with carbon to form a surface epi-layer 31.

Next, as shown in FIG. 15C, boron ions are implanted into the surface epilayer 31, the carbon-doped epiregion Rcde and the lower p-type silicon substrate 1 to form the well impurity diffusion region 2. . At this time, the implantation conditions are that the acceleration energy is 300-2000 keV and the implantation amount is 1
× 10 ¹³ -1 × 10 ¹⁴ cm ^-2 . When boron ions are implanted in such an energy range, the impurity diffusion region for well 2 has a low impurity concentration near the surface of the p-type silicon substrate 1 and a peak of the impurity concentration deep in the p-type silicon substrate 1. Has a certain impurity concentration profile, and becomes a so-called retrograde well. Next, boron ions having a threshold control level concentration are implanted into a region extending over the entire surface epi layer 31 and a part of the carbon-doped epi region Rcde to form the channel impurity diffusion region 16. The injection condition is such that the acceleration energy is 20-60 keV.
And the injection amount is 4-6 × 10 ¹² cm ⁻² .

Next, as shown in FIG. 15D, the surface of the substrate is oxidized to form a gate insulating film 4 having a thickness of 8 to 12 nm.
To form

Next, as shown in FIG. 15E, after a polysilicon film having a thickness of 200 to 300 nm is deposited on the entire surface, the gate electrode 5 is subjected to ordinary photo and etching steps.
To form Next, sidewalls 7 are formed on both side surfaces of the gate electrode 5.

Next, as shown in FIG. 15F, using the gate electrode 5 and the side wall 7 as a mask, the gate electrode 5, the surface epilayer 31 and the carbon-doped epiregion Rc are formed.
High-concentration arsenic ions are implanted into a region located on both sides of the gate electrode 5 within a region extending over de to form a source / drain impurity diffusion region 10. At this time, the source / drain impurity diffusion region 10 into which the arsenic ions are introduced.
Is above the lower end of the carbon-doped region Rcd. The injection condition is such that the acceleration energy is 30 to 40 keV.
And the injection amount is about 5 × 10 ¹⁵ cm ⁻² . Next, 85% is used to activate the introduced impurities and recover crystal defects.
A heat treatment is performed at 0 ° C. for 30 minutes to make the gate electrode 5 a low-resistance n-type gate electrode 5 a and the silicon substrate 1.
In the p-type well 2a, the p-type channel region 16a and n
Form source / drain regions 10a.

According to the manufacturing method of the present embodiment, the ninth embodiment
There is an advantage that the carbon-doped epi region Rcde can be easily and reliably formed away from the substrate surface as compared with the embodiment.

(Eleventh Embodiment) Next, an eleventh embodiment will be described. FIG. 16 shows n according to the present embodiment.
FIG. 3 is a cross-sectional view of a channel-channel MOS transistor.

As shown in the figure, the structure of the transistor according to the present embodiment is very similar to the structure of the transistor according to the eighth embodiment (see FIG. 11). However, in this embodiment, the n-type channel region 17a is formed instead of the p-type channel region, and the carbon-doped region Rc
d is formed shallower than n-type channel region 17a.

According to the present embodiment, the following effects can be obtained. As described above, since the diffusion of impurities is suppressed by the presence of carbon, if the carbon-doped region Rcd is formed shallower than the n-type channel region 16a as in the present embodiment, the impurity in the n-type channel region 17a is reduced. At the same time that the n-type channel region 17a having a steep depth direction distribution is formed by suppressing the spread of the distribution, the n-type source / drain 10
The diffusion of “a” in the depth direction and the lateral direction is effectively suppressed. As a result, the short channel effect can be suppressed while increasing the saturation current value.

Further, the carbon-doped region Rcd suppresses the concentration gradient of excessive interstitial silicon generated in the n-type source / drain region 10a in the direction of the gate oxide film.
It is also possible to suppress the occurrence of the inverse short channel effect.

The interstitial silicon atoms trapped by carbon in the carbon-doped region Rcd form clusters with the carbon atoms. Therefore, if such a cluster exists near the pn junction (especially on the substrate region side where the impurity concentration is low), the pn junction leak may increase when the depletion layer spreads. On the other hand, as in the present embodiment, the carbon-doped region Rcd is different from the n-type channel region 17a.
It is provided shallower and is not introduced into the pn junction, thereby preventing an increase in pn junction leakage,
Short channel effects can be suppressed.

In particular, when the channel region 16a and the source / drain region 10a are of the same conductivity type as in the present embodiment, the carbon does not exist in the pn junction, so that the junction leakage is suppressed as described above. There are potential benefits.

Although illustration of the manufacturing process of the present embodiment is omitted, the carbon ion implantation step (the step shown in FIG. 13B) in the ninth embodiment described above It goes without saying that a shallow carbon-doped region Rcd can be easily formed by weakening the acceleration energy. Other steps are the same as the steps shown in FIGS.

Although not shown, the carbon-doped region may be formed only in the channel region not only in the depth direction but also in the lateral direction. For example, FIG.
A gate oxide film is formed before the step shown in FIG.
By implanting carbon ions using a resist film having a pattern obtained by expanding the inversion pattern of the gate electrode as a mask, a carbon-doped region that does not protrude from the channel region in both the depth direction and the lateral direction can be formed. it can.

(Twelfth Embodiment) Next, a twelfth embodiment will be described. FIG. 17 shows n according to the present embodiment.
It is sectional drawing of a channel type MOS transistor.

As shown in the figure, a p-type well 2a is formed in a p-type silicon substrate 1, and a p-type channel region 16a and an n-type source / drain region 10a in the p-type well 2a. A carbon-doped region Rcd is formed in a deep region. That is, in the present embodiment, the carbon-doped region Rcd is the p-type channel region 16a.
And do not overlap with the n-type source / drain regions 10a. Other configurations are the same as those in the tenth embodiment.

Next, an impurity concentration profile of the transistor according to the present embodiment will be described with reference to FIG. As shown in the figure, the p-type well 2a of the transistor according to the present embodiment has a low impurity concentration near the surface of the p-type silicon substrate 1 and an impurity concentration having a peak of the impurity concentration deep in the silicon substrate 1. It has a profile and is a so-called retro grade well. The carbon-doped region Rcd does not overlap with the p-type channel region 16a and the n-type source / drain regions 10a, and the carbon concentration peak position is shallower than the impurity concentration peak position of the p-type well 2a. Have a profile.

By adopting the structure as in the present embodiment, it is possible to suppress the diffusion of interstitial silicon to the substrate surface near the peak position of the impurity concentration in the p-type well 2a. A steep interstitial silicon concentration gradient in the vicinity of the mold channel region 16a can be suppressed. Therefore, p-type channel region 16a
The distribution of impurities in the inside can be kept sharp, and a decrease in the saturation current value can be suppressed.

Next, the n-channel type MO according to this embodiment will be described.
FIG. 19A shows the manufacturing process of the S transistor.
This will be described with reference to FIG.

First, as shown in FIG. 19A, boron ions are implanted into a p-type silicon substrate 1 to form a well impurity diffusion region 2 for wells. The implantation conditions at this time are as follows: the acceleration energy is 300-2000 keV, and the implantation amount is 1 ×
It is 10 < ¹³ > -1 * 10 ^{< 14} > cm ^<-2> . When boron ions are implanted in such an energy range, the impurity diffusion region for well 2 has a low impurity concentration near the surface of the p-type silicon substrate 1 and a peak of the impurity concentration deep in the p-type silicon substrate 1. Has a certain impurity concentration profile, and becomes a so-called retrograde well.

Next, as shown in FIG. 19B, carbon ions are implanted into the well impurity diffusion region 2 to form a carbon-doped region Rcd. At this time, the implantation conditions are that the acceleration energy is 80 keV and the implantation amount is 1 × 10 ¹⁵ cm ^−2.
(Preferably in the range of 3 × 10 ¹⁴ to 2 × 10 ¹⁵ cm ⁻² ).

Next, as shown in FIG. 19C, a boron ion having a threshold control level is implanted into a region near the surface of the p-type silicon substrate 1 to form a channel impurity diffusion region 16. I do. The injection condition is that the acceleration energy is 2
At 0-30 keV, the implantation dose is 4-6 × 10 ¹² cm ⁻² .

Next, as shown in FIG. 19D, the surface of the p-type silicon substrate 1 is oxidized to form a gate insulating film 4 having a thickness of 8 to 12 nm.

Next, as shown in FIG. 19E, after a polysilicon film having a thickness of 200 to 300 nm is deposited on the entire surface, the gate electrode 5 is subjected to ordinary photo and etching steps.
To form Next, sidewalls 7 are formed on both side surfaces of the gate electrode 5.

Next, as shown in FIG. 19F, using the gate electrode 5 and the side wall 7 as a mask, the gate electrode 5 and a region located on both sides of the gate electrode 5 in the p-type silicon substrate 1 are formed. At this time, high concentration arsenic ions are implanted to form source / drain impurity diffusion regions (not shown). At this time, the source
The drain impurity diffusion region is shallower than the carbon-doped region Rcd. The injection condition is such that the acceleration energy is 30 to 40 ke.
In V, the implantation amount is about 5 × 10 ¹⁵ cm ⁻² . Next, in order to activate the introduced impurities and recover crystal defects, 8
The gate electrode 5 is turned into a low-resistance n-type gate electrode 5a by performing a heat treatment at 50 ° C. for 30 minutes, and a p-type well 2a and a p-type channel region 16a are formed in the silicon substrate 1.
And an n-type source / drain region 10a.

(Thirteenth Embodiment) Next, a thirteenth embodiment will be described. Although the structure of the n-channel MOS transistor according to the present embodiment is essentially the same as the structure of the transistor according to the twelfth embodiment, in the present embodiment, a carbon-doped region is formed simultaneously with epitaxial growth. Are different.

Hereinafter, the n-channel type MO according to this embodiment will be described.
FIG. 20A shows the manufacturing process of the S transistor.
This will be described with reference to FIG.

First, as shown in FIG. 20A, a carbon-doped epi region RRcde is formed on a p-type silicon substrate 1 by epitaxially growing a silicon single crystal while doping carbon.

Next, as shown in FIG. 20B, a silicon single crystal is epitaxially grown on the carbon-doped epi region Rcde without doping with carbon to form a surface epilayer 32.

Next, as shown in FIG. 20C, boron ions are implanted into the surface epilayer 32, the carbon-doped epiregion Rcde and the lower p-type silicon substrate 1 to form the well impurity diffusion region 2. . At this time, the implantation conditions are that the acceleration energy is 300-2000 keV and the implantation amount is 1
× 10 ¹³ -1 × 10 ¹⁴ cm ^-2 . When boron ions are implanted in such an energy range, the impurity diffusion region for well 2 has a low impurity concentration near the surface of the p-type silicon substrate 1 and a peak of the impurity concentration deep in the p-type silicon substrate 1. Has a certain impurity concentration profile, and becomes a so-called retrograde well. Next, boron ions having a threshold control level concentration are implanted into a region near the surface of the surface epilayer 32 to form the channel impurity diffusion region 16. The injection conditions are as follows:
At -60 keV, the dose is 4-6 × 10 ¹² cm ⁻² .

Next, as shown in FIG. 20D, the surface of the substrate is oxidized to form a gate insulating film 4 having a thickness of 8 to 12 nm.
To form

Next, as shown in FIG. 20E, a polysilicon film having a thickness of 200 to 300 nm is deposited on the entire surface, and the gate electrode 5 is subjected to ordinary photo and etching steps.
To form Next, sidewalls 7 are formed on both side surfaces of the gate electrode 5.

Next, as shown in FIG. 20F, using the gate electrode 5 and the side wall 7 as a mask, the gate electrode 5 and the regions located on both sides of the gate electrode 5 in the surface epilayer 32 are formed. High concentration arsenic ions are implanted to form source / drain impurity diffusion regions (not shown).
At this time, the source / drain impurity diffusion region into which arsenic ions are introduced is shallower than the carbon-doped region Rcd. The implantation conditions are such that the acceleration energy is 30 to 40 keV and the implantation amount is about 5 × 10 ¹⁵ cm ⁻² . Next, at 850 ° C. to activate the introduced impurities and recover crystal defects,
By performing a heat treatment for 0 minutes, the gate electrode 5 is turned into a low-resistance n-type gate electrode 5a, and a p-type
Form a well 2a, a p-type channel region 16a, and an n-type source / drain region 10a.

According to the manufacturing method of this embodiment, the first
As compared with the second embodiment, there is an advantage that the peak position of the carbon concentration in the carbon-doped epi region Rcde can be easily and reliably formed to be shallower than the peak position of the impurity concentration in the p-type well 2a.

(Other Embodiments) In each of the above embodiments, an n-channel MOS is used as a semiconductor device.
Although the transistor has been described, the present invention is not limited to such an embodiment, and can be similarly applied to a p-channel MOS transistor. Therefore, it is needless to say that the present invention can be applied to a CMOS semiconductor device equipped with an n-channel MOS transistor and a p-channel MOS transistor.

The present invention can be applied not only to MOS type semiconductor devices but also to general MIS type semiconductor devices having a gate insulating film formed of an oxynitride film or the like.

Further, the method of forming the carbon-doped region is not necessarily limited to the ion implantation method or the CVD method (epitaxial growth method) as in the above embodiments, but may be a diffusion method from a gas, an introduction method using plasma, or the like. May also be used.

Similarly, an n-type source / drain region, a channel region, a low concentration source / drain region (extension)
), The pocket injection region, etc., can also use the diffusion method from gas or the introduction method from plasma. However, it is needless to say that carbon must be introduced in advance when diffusion of impurities is to be suppressed by using the diffusion method.

Further, in each of the above embodiments, the semiconductor substrate is constituted by a silicon substrate. However, the present invention is not limited to such an embodiment, and can be similarly applied to other types of semiconductor substrates. It is.

[0177]

According to the present invention, the carbon-doped region is formed so as to overlap with the source / drain region of the semiconductor device. It is possible to make the depth shallower in accordance with the reduction in the gate length, so that the short channel effect in a miniaturized semiconductor device can be suppressed.

According to claim 3-6, in a semiconductor device having a low-concentration source / drain region provided between a source / drain region and a region immediately below a gate, carbon is provided so as to overlap with the low-concentration source / drain region. Since a doped region is formed or a carbon doped region is formed over a pocket region added to this structure, in a miniaturized semiconductor device, in addition to the suppression of the short channel effect, the suppression of the reverse short channel effect And the diffusion capacity can be reduced.

According to the ninth aspect, the channel region is formed so as to overlap the channel region of the semiconductor device. Therefore, in a miniaturized semiconductor device, the short channel effect and the inverse short channel effect can be reduced. In addition to restraint,
A high saturation current value can be maintained.

According to the tenth aspect, the carbon-doped region is formed so as to be away from the channel region in the depth of the well region of the semiconductor device. Therefore, in a miniaturized semiconductor device, the inverse short channel effect can be reduced. It is possible to suppress and maintain a high saturation current value.

According to claim 12-22, claim 1-1
Manufacturing of the semiconductor device having the first configuration can be facilitated.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an n-channel MOS transistor according to a first embodiment.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the n-channel MOS transistor according to the first embodiment.

FIG. 3 is a cross-sectional view of an n-channel MOS transistor according to a second embodiment.

FIG. 4 is a cross-sectional view of an n-channel MOS transistor according to a third embodiment.

FIG. 5 is a cross-sectional view showing a process of manufacturing an n-channel MOS transistor according to a third embodiment.

FIG. 6 is a cross-sectional view of an n-channel MOS transistor according to a fourth embodiment.

FIG. 7 is a cross-sectional view of an n-channel MOS transistor according to a fifth embodiment.

FIG. 8 is a sectional view of an n-channel MOS transistor according to a sixth embodiment.

FIG. 9 is a cross-sectional view showing a manufacturing step of an n-channel MOS transistor according to a sixth embodiment.

FIG. 10 is a sectional view of an n-channel MOS transistor according to a seventh embodiment.

FIG. 11 is a sectional view of an n-channel MOS transistor according to an eighth embodiment.

FIG. 12 is a sectional view of an n-channel MOS transistor according to a ninth embodiment.

FIG. 13 is a cross-sectional view showing a manufacturing step of the n-channel MOS transistor according to the ninth embodiment.

FIG. 14 is an n-channel MOS according to a tenth embodiment.
FIG. 3 is a cross-sectional view of a transistor.

FIG. 15 shows an n-channel MOS according to a tenth embodiment.
FIG. 4 is a cross-sectional view illustrating a manufacturing process of the transistor.

FIG. 16 shows an n-channel MOS according to an eleventh embodiment.
FIG. 3 is a cross-sectional view of a transistor.

FIG. 17 shows an n-channel MOS according to a twelfth embodiment.
FIG. 3 is a cross-sectional view of a transistor.

FIG. 18 shows an n-channel MOS according to a twelfth embodiment.
FIG. 4 is a diagram illustrating a relationship between an impurity concentration in each region of a transistor and a carbon concentration in a carbon-doped region.

FIG. 19 shows an n-channel MOS according to a twelfth embodiment.
FIG. 4 is a cross-sectional view illustrating a manufacturing process of the transistor.

FIG. 20 is an n-channel MOS according to a thirteenth embodiment;
FIG. 4 is a cross-sectional view illustrating a manufacturing process of the transistor.

FIG. 21 is a sectional view showing the structure of each of various conventional n-channel MOS transistors.

FIG. 22 is a cross-sectional view showing a manufacturing step of a conventional n-channel MOS transistor having an LDD structure and a pocket injection region.

[Explanation of symbols]

 Reference Signs List 1 p-type silicon substrate (substrate region) 2 impurity diffusion region for well 2 a p-type well (substrate region) 4 gate insulating film 5 gate electrode 5 a n-type gate electrode 7 sidewall 10 impurity diffusion region for source / drain 10 a n-type source Drain region 12 Low-concentration source / drain impurity diffusion region 12a n-type low-concentration source / drain region 15a p-type pocket region 16 channel impurity diffusion region 16a p-type channel region 17a n-type channel region 21a, 21b silicide layer 31, 32 Surface epi layer Rcd Carbon doped region Rcde Carbon doped epi region

Claims (22)

[Claims] A semiconductor substrate; a first conductivity type substrate region formed in the semiconductor substrate; a gate insulating film formed on the semiconductor substrate; and a gate electrode formed on the gate insulating film. And a second conductivity type source / drain region formed in a region located on both sides of the gate electrode in the semiconductor substrate; and a carbon doped region formed in at least a region overlapping the source / drain region. A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein said carbon-doped region is formed only inside said source / drain region. 3. A semiconductor substrate, a first conductivity type substrate region formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a gate electrode formed on the gate insulating film. A source / drain region of a second conductivity type formed in a region located on both sides of the gate electrode in the semiconductor substrate; a region located immediately below the gate electrode in the substrate region; and the source / drain A low-concentration source / drain region of the second conductivity type formed in a region between the first and second regions, and a carbon-doped region formed in a region overlapping at least the low-concentration source / drain region in the semiconductor substrate. A semiconductor device, comprising: 4. The semiconductor device according to claim 3, further comprising: a first conductivity type pocket region formed in a region below said low concentration source / drain region and in contact with said low concentration source / drain region; A semiconductor device, wherein the doped region is formed over a part of the pocket region. 5. The semiconductor device according to claim 3, wherein said carbon-doped region is formed only inside said low-concentration source / drain region. 6. The semiconductor device according to claim 5, further comprising a first conductivity type pocket region formed in a region below said lightly doped source / drain region and in contact with said lightly doped source / drain region. A semiconductor device characterized by the above-mentioned. 7. A semiconductor substrate, a first conductivity type substrate region formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a gate electrode formed on the gate insulating film A source / drain region of the second conductivity type formed in a region located on both sides of the gate electrode in the semiconductor substrate; and a region formed immediately below the gate electrode in the semiconductor substrate. A semiconductor device, comprising: a channel region containing a threshold control level impurity; and a carbon doped region formed at least in a region overlapping with the channel region. 8. The semiconductor device according to claim 7, wherein the carbon-doped region is formed only inside the channel region. 9. The semiconductor device according to claim 8, wherein the carbon-doped region is separated from the gate insulating film. 10. A semiconductor substrate, a first conductivity type well region formed in the semiconductor substrate, a gate insulating film formed above the well region and on the semiconductor substrate, and the gate insulating film. A gate electrode formed thereon; a second conductivity type source / drain region formed in a region located on both sides of the gate electrode in the semiconductor substrate so as to be in contact with the well region at a lower end; A region located between the source and the drain in the substrate is formed to be in contact with the well region at a lower end;
A channel region containing an impurity of a threshold control level; and a carbon doped region including a part of the well inside the well region and formed apart from the channel region and the source / drain region. A semiconductor device characterized by the above-mentioned. 11. The semiconductor device according to claim 10, wherein a peak position of the carbon concentration in the carbon-doped region is shallower than a peak position of the first conductivity type impurity concentration in the well region. 12. A first step of forming a first conductivity type substrate region in a semiconductor substrate, and a second step of forming a gate insulating film and a gate electrode above the substrate region and on the semiconductor substrate. And introducing a second conductivity type impurity into the semiconductor substrate using at least the gate electrode as a mask, and forming a source / drain in a region located above the substrate region and on both sides of the gate electrode in the semiconductor substrate. A third step of forming a source / drain impurity diffusion region, and after or before the third step, carbon is introduced into the semiconductor substrate using at least the gate electrode as a mask, and the source / drain impurity diffusion is performed. Performing a fourth step of forming a carbon-doped region in a region overlapping with the region, and performing a heat treatment on the semiconductor substrate to at least expand the impurity for the source / drain. The method of manufacturing a semiconductor device characterized by and a fifth step of activating a second conductivity type impurity in the region. 13. The semiconductor device manufacturing method according to claim 12, wherein in the fourth step, the carbon doped region is formed only inside the source / drain impurity diffusion region. Manufacturing method. 14. The method of manufacturing a semiconductor device according to claim 12, further comprising a step of forming sidewalls on both side surfaces of said gate electrode after said second step and before said third step. In the third step, a second conductivity type impurity is introduced into the substrate region using the gate electrode and the sidewall as a mask, and in the fourth step, the gate electrode and the sidewall are masked. A method of manufacturing a semiconductor device, wherein carbon is introduced into the substrate region. 15. The method of manufacturing a semiconductor device according to claim 13, wherein after the second step and before the third step, a low-concentration first semiconductor layer is formed in the substrate region using the gate electrode as a mask. A step of introducing a two-conductivity-type impurity to form low-concentration source / drain impurity diffusion regions in regions located on both sides of the gate electrode in the semiconductor substrate; A method for manufacturing a semiconductor device, comprising introducing carbon into the substrate region using an electrode as a mask. 16. The method for manufacturing a semiconductor device according to claim 15, wherein after the second step and before the third step, the first conductivity type is formed in the substrate region using the gate electrode as a mask. Impurities are introduced and the low-concentration source
A method for manufacturing a semiconductor device, further comprising a step of forming a pocket region below a drain impurity diffusion region and in a region adjacent to the low-concentration source / drain region. 17. A first step of forming a first conductivity type substrate region in a semiconductor substrate, and introducing a threshold control level impurity into the semiconductor substrate to form a region near a surface in the semiconductor substrate. A second step of forming a channel impurity diffusion region, and after or before the second step, carbon is introduced into the semiconductor substrate to overlap the channel impurity diffusion region in the semiconductor substrate. A third step of forming a carbon-doped region in the region, a fourth step of forming a gate insulating film and a gate electrode on the channel impurity diffusion region, and the semiconductor substrate using at least the gate electrode as a mask. A fifth step of introducing a second conductivity type impurity into the semiconductor substrate and forming source / drain impurity diffusion regions in regions located on both sides of the gate electrode in the semiconductor substrate; Serial subjected to a heat treatment of the semiconductor substrate, a method of manufacturing a semiconductor device characterized by and a sixth step of activating the impurity introduced into the respective impurity diffusion regions. 18. The method of manufacturing a semiconductor device according to claim 17, wherein in the third step, carbon ions are implanted at an acceleration energy such that the carbon-doped region is formed apart from a surface of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: 19. A first step in which a semiconductor single crystal containing carbon is epitaxially grown on a semiconductor substrate to form a carbon-doped epilayer, and a semiconductor single crystal is epitaxially grown on the carbon-doped epilayer to form a surface epilayer. A second step of forming a channel impurity diffusion region by introducing a threshold control level of impurity ions into the surface epi layer and a region including at least a part of the carbon doped epi layer. A fourth step of forming a gate insulating film and a gate electrode on the impurity diffusion region for a channel, and a second conductivity type impurity in the surface epilayer and the carbon doped epilayer using at least the gate electrode as a mask. Is introduced into the surface epilayer and the carbon-doped epilayer in regions located on both sides of the gate electrode.
A fifth step of forming an impurity diffusion region for a drain; and a sixth step of performing a heat treatment on the semiconductor substrate to activate an impurity introduced into each of the impurity diffusion regions. A method for manufacturing a semiconductor device. 20. A first step of forming a well impurity diffusion region by implanting a first conductivity type impurity ion into a semiconductor substrate; and introducing a threshold control level impurity into the semiconductor substrate, A second step of forming a channel impurity diffusion region in a region near the surface of the substrate; and carbon ions are implanted into the semiconductor substrate after or before the second step to form the impurity diffusion region for the well. A third step of forming a carbon-doped region in a region including a part of the back of the region and away from the channel impurity diffusion region; and forming a gate insulating film and a gate electrode on the channel impurity diffusion region. A fourth step of introducing a second conductivity type impurity into the semiconductor substrate by using at least the gate electrode as a mask, and positioning the impurity on both sides of the gate electrode in the semiconductor substrate. A fifth step of forming a source / drain impurity diffusion region in the region; and a sixth step of performing a heat treatment on the semiconductor substrate to activate the impurities introduced into each of the impurity diffusion regions. A method for manufacturing a semiconductor device, comprising: 21. The method of manufacturing a semiconductor device according to claim 20, wherein the position where the carbon concentration in the carbon-doped region is maximum is:
A method of manufacturing a semiconductor device, wherein the semiconductor device is located above a position where the first conductivity type impurity concentration in the well impurity diffusion region is maximum. 22. A first step of epitaxially growing a carbon-doped semiconductor single crystal on a semiconductor substrate to form a carbon-doped epilayer, and a step of epitaxially growing a semiconductor single crystal on the carbon-doped epilayer to form a surface epilayer. Forming a well impurity diffusion region by implanting a first conductivity type impurity ion into a region extending over the surface epi layer, the carbon doped epi layer, and a part of the semiconductor substrate. A third step of implanting impurity ions at a threshold control level above the surface epi layer to form a channel impurity diffusion region; and a gate insulating film on the channel impurity diffusion region. And a fifth step of forming a gate electrode, and introducing a second conductivity type impurity into the surface epilayer using at least the gate electrode as a mask. A sixth step of forming source / drain impurity diffusion regions in regions located on both sides of the gate electrode in the surface epi layer, and performing a heat treatment on the semiconductor substrate to thereby introduce impurities introduced into the impurity diffusion regions. And a seventh step of activating the semiconductor device.