TWI476923B - Double diffused drain metal oxide semiconductor device and manufacturing method thereof - Google Patents

Description

Double-diffused drain metal oxide semiconductor device and method of manufacturing same

The present invention relates to a double diffused drain metal oxide semiconductor (DDDMOS) device and a method of fabricating the same, and more particularly to improving a breakdown voltage and improving band gap tunneling (band) -to-band tunneling) DDDMOS device and its manufacturing method.

1A-1C are cross-sectional, perspective, and top views, respectively, of a prior art double diffused drain metal oxide semiconductor (DDDMOS) device 100. As shown in FIGS. 1A and 1B, the field oxide layer 12 is formed in the P-type substrate 11, and the field oxide layer 12 is, for example, a shallow trench isolation (STI) structure or a region oxide (local) as shown in the figure. Oxidation of silicon, LOCOS) structure. The DDDMOS device 100 includes a gate 13, a drift region 14, a source 15, and a drain 16. The drift region 14, the source 15 and the drain 16 are defined by lithography techniques, and the N-type impurities are implanted into the defined regions in the form of accelerated ions by ion implantation techniques, respectively. The source 15 and the drain 16 are respectively located below the two sides of the gate 13 , and the drift region 14 is located on the side of the drain 16 and partially below the gate 13 . Fig. 1C shows a top view of the DDDMOS device 100, showing the positional relationship of the conductive plug 18 and the first metal layer 19 in the DDDMOS device 100 in addition to the relative positional relationship of the respective regions. As shown in FIG. 1C, in the prior art DDDMOS device 100, in order to reduce the antenna effect, the conductive plug 18 and the first metal layer 19 are arranged to be defined by the field oxide layer 12 surrounding the DDDMOS device 100. The element area 12a (illustrated by the thick black line in the figure) is outside.

However, the DDDMOS device is a high voltage component, that is, it is designed to be supplied for a higher operating voltage, but when the DDDMOS component needs to be integrated on the same substrate as a component of a generally lower operating voltage, it is compatible with a lower operating voltage. In the component process, the DDDMOS component and the low voltage component need to be fabricated with the same ion implantation parameters, so that the ion implantation parameters of the DDDMOS component are limited, especially the collapse protection voltage of the P-type substrate 11 and the N-type drift region 14 side junction. Lower. In addition, when the DDDMOS device is operated in a high electric field, the electron hole is generated to cause the band to be twisted, so that the carrier has sufficient energy, and the carrier is directly priced when the conduction band/valence band of the junction depletion zone is close. The effect of the electrical band crossing the bandgap band to the conduction band is the band gap tunneling effect. When the component size is getting smaller and smaller, this effect will obviously cause leakage current, which is also considered. Therefore, under the limitation of the processing conditions, the application range of the component is further limited. If the DDDMOS component collapse protection voltage is not sacrificed or the tunneling effect needs to be improved, the process step must be added, and the DDDMOS component is separately manufactured in different process steps, but As a result, the manufacturing cost will be increased to achieve the desired collapse protection voltage. 2A and 2B are diagrams showing a simulation diagram of a component equipotential line and a current-voltage characteristic of a DDDMOS device of the prior art when operating in a reverse bias voltage. Taking a 6V DDDMOS device as an example, the breakdown protection voltage is about 18.7V, and In the reverse bias voltage of 16.5V or more, a significant band gap tunneling effect is exhibited. A comparison thereof with components of the same specifications to which the present invention is applied will be described in detail later.

In view of the above, the present invention is directed to the above-mentioned deficiencies of the prior art, and provides a high-voltage component and a manufacturing method thereof, which can improve the breakdown protection voltage of the component operation and improve the tunneling effect without increasing the process steps, thereby increasing the component. The scope of application can be integrated into the process of low voltage components.

It is an object of the present invention to provide a double diffused drain metal oxide semiconductor (DDDMOS) device and a method of fabricating the same.

In order to achieve the above object, the present invention provides a DDDMOS device formed in a first conductive type substrate having an upper surface, the DDDMOS device comprising: a drift region formed under the upper surface, having a The second conductivity type includes a first region and a second region; a gate is formed above the upper surface, and the first region of the drift region is located under the gate; a source and a drain have a second conductivity Forming, respectively, under the upper surface on both sides of the gate, and the drain is located in the second region of the drift region, viewed from a top view, between the drain and the gate, by the second region of the drift region Separating a portion; a dielectric layer formed over the gate and the second region of the drift region; and a conductive layer formed over the dielectric layer, wherein the conductive layer is viewed from a top view Between the gate and the drain, at least a portion of the second region of the drift region overlaps.

In another aspect, the present invention also provides a method of fabricating a DDDMOS device, comprising: providing a first conductive type substrate having an upper surface; forming a drift region below the upper surface, having a second conductivity type, including a first region and a second region; forming a gate above the upper surface, and the first region of the drift region is located below the gate; respectively forming a source and a drain under the upper surface on both sides of the gate Having a second conductivity type, and the drain is located in the second region of the drift region, as viewed from a top view, the drain and the gate are separated by a portion of the second region of the drift region; The dielectric material forms a dielectric layer over the gate and the second region of the drift region; and a conductive layer is formed over the dielectric layer by a conductive material, and the conductive layer is at the gate from a top view Between the drain and at least a portion of the second region of the drift region.

In a preferred embodiment, in the DDDMOS device, the conductive layer is electrically connected to the gate.

In the above DDDMOS device, the conductive layer is viewed from a top view, and can completely span an element region of the DDDMOS device in a width direction of the DDDMOS device, wherein the device region is defined by a field oxide layer surrounding the DDDMOS device. .

In the above DDDMOS device, the conductive layer is viewed from a top view and preferably overlaps at least a portion of the gate.

In another preferred embodiment, in the DDDMOS device, the conductive layer is preferably formed of a metal material, and preferably, a first metal layer is formed by the same process as the DDDMOS device.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.

Referring to Figures 3A-3F, a first embodiment of the present invention is shown. This embodiment shows a perspective view of a manufacturing method of the DDDMOS device 200. It should be noted that in order to show the focus of the invention, in FIG. 3B, the gate 23 is separately displayed from the gate dielectric layer 23a and the substrate 21 for easy understanding. First, as shown in FIG. 3A, in the substrate 21, a field oxide layer 22 is formed to define an element region (surrounded by the field oxide layer 22, not shown), wherein the substrate 21 is, for example, a P type but is not limited to a P type. (Alternate to N-type); the field oxide layer 22 is, for example, an STI structure or a regional oxide LOCOS structure as shown. As shown in FIG. 3A, a gate dielectric layer 23a is formed on the upper surface 211 of the substrate 21, such as but not limited to, on the upper surface 211 of the substrate 21 by an oxidation technique. Next, as shown in FIG. 3B, a gate electrode 23 is formed on the upper surface 211 of the substrate; in the element region, a drift region 24, a source electrode 25, and a drain electrode 26 are formed. The N-type drift region 24, the N-type source 25, and the N-type drain 26 are formed under the upper surface 211, and are covered by lithography and/or partially or entirely by the gate 23 and the field oxide layer 22. The hood is used to define the regions and is formed by implanting N-type impurities in the form of accelerated ions into the defined regions by ion implantation techniques, respectively. The source 25 and the drain 26 are respectively located below the two sides of the gate 23 . The drain 26 is located in the second region 24b of the drift region 24, and the drain 26 and the gate 23 are separated by the second region 24b of the drift region 24, and the first region 24a of the drift region 24 is located below the gate 23. .

Next, as shown in FIG. 3C, the dielectric layer 27 is formed, for example, but not limited to, by a deposition technique. The dielectric layer 27 is formed of a dielectric material over the upper surface 211 and over the gate 23, and the dielectric layer 27 substantially covers all regions of the DDDMOS device, including the gate 23 and the second region 24b. As shown in FIG. 3D, conductive plugs 28 are formed, for example, but not limited to, using lithography techniques, etching techniques, deposition techniques, chemical mechanical polishing techniques, and the like. It should be noted that, for ease of understanding, FIG. 3D shows a single conductive plug 38. The conductive plugs are, for example but not limited to, directly connected to the gate 23 and may be arranged outside the component area. 3E and 3F show a perspective view and a top view, respectively, of the DDDMOS device 200 of the present invention. As shown in FIG. 3E, a conductive layer 29 is formed over the dielectric layer 27 with a conductive material using, for example, but not limited to, lithography, deposition techniques, and etching techniques. The conductive material is, for example but not limited to, a metal such as aluminum copper, and the conductive layer 29 can be formed, for example, by the same process as the first metal layer (not shown) in the DDDMOS device 200. It should be noted that, as shown in the upper view of FIG. 3F, the conductive layer 29 overlaps between the gate 23 and the drain 26 and at least a portion of the second region 24b of the drift region 24.

Unlike the prior art, in the present embodiment, the DDDMOS device 200 has a conductive layer 29 overlapping the second region 24b of at least a portion of the drift region 24, as viewed from above, above the dielectric layer 27. This embodiment shows that the present invention is superior to the prior art in that a conductive layer 29 overlapping at least a portion of the second region 24b is separated by a dielectric layer 27, and the conductive layer 29 is preferably electrically connected to the gate 23. In this way, whether the DDDMOS device 200 is operated in conduction or non-conduction, the conductive layer 29 generates an electric field, which penetrates the dielectric layer 27 and affects the electric field of the channel of the DDDMOS device 200, so that the gate is triggered when the operation is turned on. Gate induced drain leakage (GIDL); and improves the band gap tunneling effect when the DDDMOS device 200 operates in a non-conducting state; moreover, the DDDMOS device 200 collapse protection voltage can be further improved.

Comparing the prior art 2A and 2B, when the DDDMOS device is operated in reverse bias, the component isotope line simulation diagram and the current-voltage characteristic simulation diagram, and the DDDMOS component which is the same as the application of the present invention, operates in the reverse bias voltage. The component isotope line simulation diagram and current-voltage characteristic simulation diagrams 4A and 4B. By applying the invention, the density of the equipotential lines can be reduced, the electric field can be lowered, the collapse protection voltage can be increased, and the band gap tunneling effect can be improved. Comparing FIGS. 2B and 4B, the collapse protection voltage of the prior art DDDMOS device is about 18.7 V, and the reverse bias voltage is 16.5 V or more, exhibiting a significant band gap tunneling effect; and the DDDMOS to which the present invention is applied. The component's breakdown protection voltage is approximately 19.4V, which significantly improves component performance for DDDMOS devices operating at 6V, and does not exhibit significant band gap tunneling effects before component collapse. In addition, the conductive layer 29 of the present invention can be completed simultaneously with the first metal layer by the process of the first metal layer. The advantage of this arrangement can be, but is not limited to, utilizing the same process steps as the first metal layer in the process, without the need to additionally add a mask or process step, thereby reducing manufacturing costs.

5A-5C are top views showing different embodiments of several conductive layers in the DDDMOS device 200 of the present invention. Figure 5A shows the element region 22a (shown by the thick black line in the figure) defined by the field oxide layer 22 (not shown, see Figure 3E) surrounding the DDDMOS device 200, having a width w, and this implementation In the example, the conductive layer 29a completely spans the element region 22a of the DDDMOS device in a width direction of the DDDMOS device. Fig. 5B shows that the conductive layer 29b can partially overlap the gate 23. 5C shows that the conductive layer 29c can have any shape as long as it is partially overlapped with the second region 24b as viewed from above, and within the range allowed by the antenna effect, with most of the gate 23, the drift region 24, and The bungee poles 26 are viewed from the top view and can overlap.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as deep well areas, may be added without affecting the main characteristics of the components; for example, lithography is not limited to reticle technology, and may include electron beam lithography; In all the embodiments, the drift region, the source, the drain, and the like are not limited to the N-type, and the substrate or the like is not limited to the P-type, but may be interchanged as long as the other doped regions are adjusted accordingly; for example, the conductive plug It is not limited to being formed outside the component area, and may be arranged within the component area. The above and other equivalent variations are intended to be covered by the scope of the invention.

11,21. . . Substrate

12,22. . . Field oxide layer

13,23. . . Gate

14,24. . . Drift zone

15,25. . . Source

16,26. . . Bungee

18,28. . . Conductive plug

19, 29, 29a, 29b, 29c. . . Conductive layer

23a. . . Gate dielectric layer

24a. . . First area

24b. . . Second area

27. . . Dielectric layer

100,200. . . DDDMOS component

211. . . Upper surface

w . . . width

1A-1C are cross-sectional, perspective, and top views, respectively, of a prior art DDDMOS device 100.

Figures 2A and 2B show a simulation of the component equipotential line and current-voltage characteristics of the prior art DDDMOS device operating in reverse bias.

Figures 3A-3F show a first embodiment of the invention.

4A and 4B are diagrams showing a simulation diagram of the equipotential lines and a current-voltage characteristic of the device when the DDDMOS device of the present invention is operated in the reverse bias voltage.

5A-5C are top views showing different embodiments of several conductive layers in the DDDMOS device 200 of the present invention.

21‧‧‧Substrate

22‧‧‧Field oxide layer

23‧‧‧ gate

24‧‧‧ drift zone

25‧‧‧ source

26‧‧‧汲polar

27‧‧‧Dielectric layer

28‧‧‧ Conductive plug

29‧‧‧ Conductive layer

200‧‧‧DDDMOS components

Claims (10)

A double diffused drain metal oxide semiconductor (DDDMOS) device is formed in a first conductive type substrate having an upper surface, the DDDMOS device comprising: a drift region formed on the Below the upper surface, having a second conductivity type, including a first region and a second region; a gate formed over the upper surface, and the first region of the drift region is located below the gate; a source and a drain The poles each have a second conductivity type, respectively formed under the upper surface on both sides of the gate, and the drain is located in the second region of the drift region, viewed from a top view, between the drain and the gate Separated by a portion of the second region of the drift region; a dielectric layer formed over the gate and the second region of the drift region; and a conductive layer formed over the dielectric layer and viewed from above The conductive layer overlaps at least a portion of the second region of the drift region between the gate and the drain. The DDDMOS device of claim 1, wherein the conductive layer is electrically connected to the gate. The DDDMOS device of claim 2, wherein the conductive layer is viewed from a top view, in a width direction of the DDDMOS device, completely spanning an element region of the DDDMOS device, wherein the component region is separated by a field An oxide layer is defined around the DDDMOS device. The DDDMOS device of claim 2, wherein the conductive layer is viewed from a top view and overlaps at least a portion of the gate. The DDDMOS device of claim 1, wherein the conductive layer is formed of a metal material, and a first metal of the DDDMOS device The layers are formed using the same process. A method for fabricating a double diffused drain metal oxide semiconductor (DDDMOS) device, comprising: providing a first conductive type substrate having an upper surface; forming a drift region below the upper surface, The second conductivity type includes a first region and a second region; a gate is formed above the upper surface, and the first region of the drift region is located below the gate; forming a source and a drain at the gate respectively Below the upper surface of both sides, there is a second conductivity type, and the drain is located in the second region of the drift region, viewed from a top view, between the drain and the gate, by the second region of the drift region Separating a portion; forming a dielectric layer over the gate and the second region of the drift region by a dielectric material; and forming a conductive layer over the dielectric layer from the conductive material, and viewed from a top view, The conductive layer overlaps at least a portion of the second region of the drift region between the gate and the drain. The method of fabricating a DDDMOS device according to claim 6, wherein the conductive layer is electrically connected to the gate. The method for fabricating a DDDMOS device according to claim 7, wherein the conductive layer is viewed from a top view, and spans an element region of the DDDMOS device in a width direction of the DDDMOS device, wherein the device region It is defined by a layer of oxide surrounding the DDDMOS device. The method of fabricating a DDDMOS device according to claim 7, wherein the conductive layer is viewed from a top view and overlaps at least a portion of the gate. The method for manufacturing a DDDMOS device according to claim 7 of the patent application scope, Wherein the conductive layer is formed of a metal material, and a first metal layer is formed by the same process as the DDDMOS device.