TWI476925B - Double diffused drain metal oxide semiconductor device and manufacturing method thereof - Google Patents

Description

Double-diffused drain metal oxide semiconductor device and method of manufacturing same

The present invention relates to a double diffused drain metal oxide semiconductor (DDDMOS) device and a method of fabricating the same, and more particularly to a DDDMOS device formed by a low voltage device process step and a method of fabricating the same.

1A-1B are cross-sectional and top views, respectively, of a prior art double diffused drain metal oxide semiconductor (DDDMOS) device 100. As shown in FIGS. 1A and 1B, a field oxide region 12 is formed in the P-type substrate 11 to define an element region of the P-type DDDMOS device 100. The field oxide region 12 is, for example, a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure as shown. The DDDMOS device 100 includes a gate 13, a drift region 14, a source 15, a drain 16, and a well region 17. The drift region 14, the source 15 and the drain 16 are defined by lithography techniques, and are formed by implanting a P-type impurity into a defined region in the form of an accelerated ion by ion implantation. The source 15 and the drain 16 are respectively located below the two sides of the gate 13 , and the drift region 14 is located near the drain 16 side and partially below the gate 13 . The well region 17 and the well region contact 17a are defined by lithography technology, and are respectively formed by ion implantation technology to implant N-type impurities in the form of accelerated ions into the defined region. Figure 1B shows a top view of the DDDMOS device 100 to show the relative positional relationship of the various regions.

However, the DDDMOS device 100 is a high voltage component, that is, it is designed to be supplied for higher operating voltages. The so-called high-voltage components, in general, the highest The operating voltage (for example, the N-type high-voltage component, usually refers to the voltage coupled to the drain), the voltage drop is higher than 5V relative to its lowest operating voltage. In contrast, the component operates at a voltage drop of less than or equal to 5V, referred to as a low voltage component. Under the limitation of process conditions, when the high-voltage DDDMOS component needs to be integrated on the same substrate as the general low-voltage component, if the DDDMOS component collapse protection voltage or on-resistance is not sacrificed, the process steps must be added, and the DDDMOS component must be fabricated in different process steps. However, this will increase the manufacturing cost to achieve the desired breakdown protection voltage and on-resistance.

In view of the above, the present invention is directed to the above-mentioned deficiencies of the prior art, and proposes a DDDMOS device and a manufacturing method thereof, which can form a high-voltage DDDMOS device by using a process step of a low-voltage component without increasing or slightly increasing a process step to reduce manufacturing. Cost and increase the range of applications of components.

It is an object of the present invention to provide a double diffused first drained metal oxide semiconductor (DDDMOS) device and a method of fabricating the same.

In order to achieve the above object, the present invention provides a DDDMOS device formed in a P-type substrate, and another low-voltage component is formed in the substrate, the DDDMOS device includes: a first well region having a second conductivity type, And a second well region of the low voltage component is formed in the substrate by using the same process step; a first gate is formed on the substrate, and the first gate has a first one in the channel direction a side and a second side, wherein a portion of the first well region is located below the first gate relatively close to the first side; a diffusion region having a first conductivity type, lightly doped with one of the low voltage components a dopant region, formed in the substrate by the same process step, wherein at least a portion of the diffusion region is located on the second side And the first source and the first drain have a first conductivity type, respectively formed in the substrate outside the first side and the second side, as viewed from a top view, The first drain and the first gate are separated by a portion of the diffusion region, and the first source is located in the first well region.

In another aspect, the present invention also provides a method for fabricating a DDDMOS device, comprising: providing a P-type substrate, and another low voltage component is formed in the substrate; providing a first conductive type substrate for forming the DDDMOS device Forming a second conductivity type first well region in the substrate, and forming a first well region and one of the low voltage components in the second well region by using the same process step; forming a first gate Extremely on the substrate, the first gate has a first side and a second side opposite to each other in the channel direction, wherein a portion of the first well region is located at the first gate relatively close to the first side Forming a first conductive type diffusion region in the substrate relatively close to the second side, wherein at least a portion of the diffusion region is located in the substrate outside the second side, and the diffusion region is in the low voltage component a lightly doped drain region formed by the same process step; and forming a first conductivity type first source and a first conductivity type first drain on the first gate first side and the second Side of the substrate, by the top view Optionally, the first drain and the first gate are separated by a portion of the diffusion region, and the first source is located in the first well region.

In one embodiment, the substrate may include a non-elevation substrate, and the DDDMOS device further includes a first deep well region of the second conductivity type, and the second deep well region of the low voltage component, using the same process step Formed in the substrate, and the first well region, the diffusion region, the first source and the first drain are located in the first deep well region.

In another embodiment, the DDDMOS device may further include an epitaxial layer formed on the substrate, and the first well region, the diffusion region, and the first source Preferably, the first gate is located in the epitaxial layer, and the first gate is preferably located on the epitaxial layer.

Preferably, the DDDMOS device further includes a second conductivity type buried layer formed in the substrate under the epitaxial layer.

In still another embodiment, the low voltage component further includes a second gate, a second source, and a second drain, and the first gate, the first source, and the first It is preferable to form the same process steps as the second gate, the second source, and the second drain, respectively.

In still another embodiment, the DDDMOS device can further include at least one field of oxidation formed on the substrate to define an element region, and using an identical process step of forming the first well region to form an isolation region relatively close to the Below the field oxidation zone on the first drain side.

In another embodiment, the first conductivity type is preferably P-type or N-type, and the second conductivity type corresponds to the first conductivity type being N-type or P-type.

In another embodiment, the first well region and the diffusion region preferably do not overlap each other.

In another embodiment, the diffusion region can include a plurality of sub-diffusion regions.

In the above embodiment, the plurality of sub-diffusion regions are viewed from the top view and preferably have a matrix pattern arrangement.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.

Referring to Figures 2A-2F, a first embodiment of the present invention is shown. 2A-2E is a schematic cross-sectional view showing the manufacturing method of the DDDMOS device 200 of the present embodiment, and illustrates how the high voltage device of the present invention can be completed by the low voltage device manufacturing process formed in the substrate 21. For convenience of description, in FIG. 2A-2E, two different elements which are separated by a horizontal dotted line from left to right but formed on the substrate 21; respectively, a low voltage PMOS element 300 (FIG. 2E is a low voltage NMOS element 400), and an application thereof The high voltage DDDMOS device 200 of the present invention. As shown in FIG. 2A, a P-type substrate 21 is first provided, such as, but not limited to, a non-epilation substrate. Next, in the P-type substrate 21, for example, but not limited to, respectively, the N-type deep well region 38 and the field oxide region 32 are formed in the low voltage PMOS device 300 by using the same process steps; the N-type deep well region 28 and the field oxide are formed in the DDDMOS device 200. District 22.

Next, as shown in FIG. 2B, in the P-type substrate 21, an N-type well region 37 is formed in the low-voltage PMOS device 300 by the same process step, and an N-type well region 27 is formed in the DDDMOS device 200. Wherein, the well region 37 and the well region 27 define, for example, but not limited to, the photoresist 27b formed by the lithography technique, and the ion implantation technique, the N-type impurity, in the form of an accelerated ion (as indicated by the dotted arrow in the figure) ), formed within the defined area of the implant.

Next, as shown in FIG. 2C, for example, but not limited to, respectively, using the same process steps, a gate 33 and a P-type lightly doped drain (LDD) region 34 are formed in the low voltage PMOS device 300; and the DDDMOS device is used. A gate 23 and a P-type diffusion region 24 are formed in 200. Wherein, the LDD region 34 and the diffusion region 24 are, for example but not limited to, defined by the lithography technique to form the photoresist 24a, and the ion implantation technique is used to accelerate the P-type impurity in the form of an accelerated ion (as indicated by the dotted arrow in the figure). ), formed within the defined area of the implant. The gate 23 has a first side 23a and a second side opposite to each other in the direction of the channel (as indicated by the solid arrow in the figure) 23b, and the component channel is located in the substrate 21 between the first side 23a and the second side 23b, wherein a portion of the well region 27 is located below the gate 23 of the first side 23a, and at least a portion of the diffusion region 24 is located at the second In the substrate 11 outside the side 23b. In addition, the LDD region 34 serves to mitigate the hot carrier effect of the low voltage PMOS device 300 during operation.

Next, as shown in FIG. 2D, the source 35 and the drain 36 are formed in the low voltage PMOS device 300, for example, but not limited to, using the same process steps, respectively, and the source 25 and the drain 26 are formed in the DDDMOS device 200. Wherein, the sources 35 and 25, and the drains 36 and 26, for example, but not limited to, the regions defined by the photoresist 26a formed by the lithography technique, and the ion implantation technique, the P-type impurity, in the form of accelerated ions (as shown in the figure) The dotted arrow indicates that it is formed within the defined area. The source 25 and the drain 26 are respectively formed in the substrate 21 outside the first side 23a and the second side 23b, and are separated from the gate 23 by the partial diffusion region 24, as viewed from the top view 2F. And the source 25 is located in the well region 27.

Next, as shown in FIG. 2E, for example, but not limited to, using the same process steps, a source 45 and a drain 46 are formed in the low voltage NMOS device 400 also formed in the substrate 21; a well is formed in the DDDMOS device 200. Area junction 27a. Wherein, the source 45, the drain 46 and the contact 27a are, for example but not limited to, the regions defined by the photoresist 27b formed by lithography, and the ion implantation technique is used to accelerate the ions in the form of an N-type impurity (as shown in the figure). The dotted arrow indicates that it is formed within the defined area of the implant. Further, a source 45 and a drain 46 are formed in the P-type well region 47.

Referring to Figures 3A-3G, a second embodiment of the present invention is shown. 3A-3F is a schematic cross-sectional view showing the manufacturing method of the DDDMOS device 500 of the present embodiment, and illustrates how the high voltage device of the present invention can be completed by the low voltage device manufacturing process formed in the substrate 51. For convenience of explanation, Figure 5A-5F The two different elements, which are separated from the left and right by a horizontal dashed line but formed on the substrate 51; respectively, are a low voltage PMOS element 600 (Fig. 3F is a low voltage NMOS element 700), and a high voltage DDDMOS element 500 to which the present invention is applied. As shown in FIG. 3A, first, for example, but not limited to, a P-type substrate 51 is provided. Next, in the P-type substrate 51, for example, but not limited to, respectively, using the same process steps, the N-type impurity is implanted into the defined region by the ion implantation technique in the form of accelerated ions (illustrated by the dotted arrow in the figure). The N-type buried layer 69 is formed in the low voltage PMOS device 600, or the N-type buried layer 59 is formed in the DDDMOS device 500.

Next, as shown in FIG. 3B, on the P-type substrate 21, for example, but not limited to, the epitaxial layer 61a is formed in the low voltage PMOS device 600 by the same epitaxial process step, respectively; and the epitaxial layer 51a is formed in the DDDMOS device 500. Field oxide region 62 is then formed in low voltage PMOS device 600, such as but not limited to, using the same process steps; field oxide region 52 is formed in DDDMOS device 500.

Next, as shown in FIG. 3C, in the epitaxial layers 61a and 51a, an N-type well region 67 is formed in the low-voltage PMOS device 600 by the same process step, and an N-type well region 57 and an N-type are formed in the DDDMOS device 500. The isolation region 57b, wherein the isolation region 57b is formed below the field oxide region 52 on the side closer to the drain 56 (refer to FIG. 3F). Wherein, the well regions 67 and 57 are, for example but not limited to, defined by the lithography technique to form regions of the photoresist 57c, and by ion implantation techniques, the N-type impurities are in the form of accelerated ions (as indicated by the dashed arrows in the figure). Formed within the defined area of the implant.

Next, as shown in FIG. 3D, for example, but not limited to, respectively, a gate 63 is formed on the epitaxial layer 61a by using the same process step, and a P-type LDD region 64 is formed in the epitaxial layer 61a; on the epitaxial layer 51a. A gate 53 is formed and a P-type diffusion region 54 is formed in the epitaxial layer 51a. Wherein the LDD region 64 and the diffusion region 54 are, for example However, it is not limited to forming the regions defined by the photoresist 54a by the lithography technique, and the P-type impurities are implanted into the defined regions by the ion implantation technique in the form of accelerated ions (illustrated by the dotted arrows in the figure). .

Next, as shown in FIG. 3E, the source 65 and the drain 66 are formed in the low voltage PMOS device 600 also formed in the substrate 51, for example, but not limited to, using the same process step; the source is formed in the DDDMOS device 500. 55 and bungee 56. Wherein, the sources 65 and 55, and the drains 66 and 56, for example, but not limited to, the regions defined by the lithography forming photoresist 56a, and the ion implantation technique, the P-type impurities, in the form of accelerated ions (as shown in the figure) The dotted arrow indicates that it is formed within the defined area. Viewed from the third view of the top view, the drain 56 and the gate 53 are separated by a partial diffusion region 54 and the source 55 is located in the well region 57.

Next, as shown in FIG. 3F, for example, but not limited to, the source 75 and the drain 76 are formed in the low voltage NMOS device 700 using the same process steps; the well contact 57a is formed in the DDDMOS device 500. Wherein, the source 75, the drain 76 and the contact 57a are, for example but not limited to, the regions defined by the lithography forming photoresist 57d, and the ion implantation technique is used to accelerate the ions in the form of an N-type impurity (as shown in the figure). The dotted arrow indicates that it is formed within the defined area of the implant. Further, a source 75 and a drain 76 are formed in the P-type well region 77.

Figure 4 is a cross-sectional view showing a third embodiment of the present invention, which is a DDDMOS device 800 to which the present invention is applied. As shown in the figure, an N-type DDDMOS device 800 is formed on a P-type substrate 81, and includes a P-type epitaxial layer 81a formed on the substrate 81, a P-type well region 87 formed in the epitaxial layer 81a, and a P-type contact. 87a, a P-type isolation region 87b, a field oxide region 82, an N-type diffusion region 84, an N-type source 85, a drain 86, and a gate 83 formed on the epitaxial layer 81a. This embodiment is also formed by the same process steps of the low voltage elements formed in the substrate 81. Real The examples are intended to illustrate that the invention can also be applied to N-type DDDMOS devices having an epitaxial layer.

Figures 5A-5C show a characteristic curve of a P-type DDDMOS device using the present invention. Referring to FIG. 5A, there is shown a characteristic curve of the drain current to the drain voltage when the DDDMOS device of the present invention is operated in a non-conducting state. According to the characteristic curve, the non-conduction collapse protection using the DDDMOS device of the present invention can be known. The voltage is approximately -30.5V. Referring to FIG. 5B, the characteristic curve of the gate voltage of the DDDMOS device (right vertical axis) and the conductance (left vertical axis) of the DDDMOS device of the present invention is shown. According to the characteristic curve, the DDDMOS using the present invention can be known. The threshold voltage of the component is also approximately -1.2V. Next, please refer to FIG. 5C, which shows the characteristic curve of the drain current to the drain voltage when the DDDMOS device of the present invention is operated in the on state. According to the characteristic curve, the conduction collapse protection of the DDDMOS device using the present invention can be known. The voltage is approximately -25V. 5A-5C are intended to illustrate that, in accordance with the present invention, a DDDMOS device operating in a high voltage environment can be formed using the same process steps as the low voltage component.

Fig. 6 is a top plan view showing a fourth embodiment of the present invention for applying the DDDMOS device 900 of the present invention. As shown, the N-type DDDMOS device 900 is formed on a P-type substrate (not shown), including a P-type epitaxial layer (not shown) formed on the substrate, a field oxide region 92 formed in the epitaxial layer, A P-type well region 97, a P-type contact 97a, a complex N-type sub-diffusion region 94a, an N-type source 95, a drain 96, and a gate 93 formed on the epitaxial layer are formed in the epitaxial layer. This embodiment is also formed using the same process steps of the low voltage components formed in the same substrate. This embodiment is intended to illustrate the N-type diffusion region of the present invention, and may also be formed by a plurality of sub-diffusion regions 94a having a matrix pattern as viewed from above.

It should be noted that, in the above embodiments, the preferred embodiment of the well region and the diffusion region is that the well region and the diffusion region do not overlap each other.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as a threshold voltage adjustment region, may be added without affecting the main characteristics of the component; for example, the lithography technology is not limited to the reticle technology, and may also include electron beam lithography; In all the above embodiments, the conductivity type of each region is not limited to P type (or N type), and may be N type (or P type), as long as other doping regions are adjusted accordingly. The above and other equivalent variations are intended to be covered by the scope of the invention.

11,21,51,81‧‧‧substrate

12,22,32,52,62,82,92‧‧‧Ozone oxidation zone

13,23,33,53,63,83,93‧‧‧ gate

14‧‧‧Drift area

15,25,35,45,55,65,75,85,95‧‧‧Source

16,26,36,46,56,66,76,86,96‧‧‧bungee

17,27,37,47,57,67,77,87,97‧‧

17a, 27a, 57a, 87a, 97a‧‧‧ Well junction

28,38‧‧‧Shenjing District

24,54,84‧‧‧Diffusion zone

24a, 26a, 27b, 54a, 56a, 57b, 57c, 57d‧‧‧ photoresist

34,64‧‧‧LDD area

57b, 87b‧‧ ‧ isolation zone

94a‧‧‧Sub-diffusion zone

100,200,500,600,700,800,900‧‧‧DDDMOS components

300,600‧‧‧ low voltage PMOS components

400,700‧‧‧Low-voltage NMOS components

1A-1B are cross-sectional and top views, respectively, of a prior art DDDMOS device 100.

Fig. 2A-2F shows a first embodiment of the present invention.

Figures 3A-3G show a second embodiment of the invention.

Figure 4 shows a third embodiment of the invention.

Figures 5A-5C show the characteristic curves of the DDDMOS device to which the present invention is applied.

Fig. 6 shows a fourth embodiment of the present invention.

21‧‧‧Substrate

22‧‧‧Field Oxidation Zone

23‧‧‧ gate

24‧‧‧Diffusion zone

25,45‧‧‧ source

26,46‧‧‧汲polar

27,47‧‧‧ Well Area

27a‧‧‧ Well junction

28‧‧‧Shenjing District

200‧‧‧DDDMOS components

400‧‧‧Low-voltage NMOS components

Claims (18)

A double diffused drain metal oxide semiconductor (DDDMOS) device is formed in a P-type substrate, and another low voltage component is formed in the substrate, the DDDMOS device includes: a first well region Having a second conductivity type, and a second well region of the low voltage component is formed in the substrate by the same process step; a first gate is formed on the substrate, and the first gate has a channel a first side and a second side opposite to each other, wherein a portion of the first well region is located below the first gate relatively close to the first side; a diffusion region having a first conductivity type, and a lightly doped drain region of the low voltage component formed in the substrate by the same process step, wherein at least a portion of the diffusion region is located in the substrate outside the second side; and a first source and a first a drain having a first conductivity type formed in the substrate outside the first side and the second side, viewed from a top view, between the first drain and the first gate The diffusion zone is separated, and the first The pole is located in the first well region; wherein the substrate comprises a non-elevation substrate, and the DDDMOS device further comprises a first deep well region of the second conductivity type, and the second deep well region of the low voltage component utilizes the same process The step is formed in the substrate, and the first well region, the diffusion region, the first source and the first drain are located in the first deep well region. A double diffused drain metal oxide semiconductor (DDDMOS) device is formed in a P-type substrate, and another low voltage component is formed in the substrate. The DDDMOS device includes: a first well region having a second conductivity type, and a second well region of the low voltage component, formed in the substrate by the same process step; a first gate formed on the substrate, the first The gate has a first side and a second side opposite to each other in the channel direction, wherein a portion of the first well region is located below the first gate relatively close to the first side; a diffusion region has a first a conductive type, and a lightly doped drain region of the low voltage component, formed in the substrate by the same process step, wherein at least a portion of the diffusion region is located in the substrate outside the second side; a first source The poles and the first drains each have a first conductivity type formed in the substrate outside the first side and the second side, and the first drain and the first gate are viewed from a top view Interposed by a portion of the diffusion region, and the first source is located in the first well region; and an epitaxial layer is formed on the substrate, and the first well region, the diffusion region, the first The source and the first drain are located in the epitaxial layer, and the first gate is located on the epitaxial layer. The DDDMOS device of claim 2, further comprising a second conductivity type buried layer formed in the substrate under the epitaxial layer. The DDDMOS device of claim 1 or 2, wherein the low voltage component further includes a second gate, a second source, and a second drain, and the first gate, the first The source and the first drain are respectively formed by the same process steps as the second gate, the second source, and the second drain. The DDDMOS device according to claim 1 or 2, further comprising at least one oxidation zone formed on the substrate to define an element region, and forming an isolation region by using the same process step of forming the first well region Relatively Near the field oxide region of the first drain side. A method of manufacturing a double diffused drain metal oxide semiconductor (DDDMOS) device, comprising: providing a P-type substrate for forming the DDDMOS device and another low voltage component; forming a second conductivity type a first well region is in the substrate, and the first well region and one of the second well regions of the low voltage component are formed by the same process step; forming a first gate on the substrate, the first gate having a first side and a second side opposite to each other in the channel direction, wherein a portion of the first well region is located below the first gate relatively close to the first side; forming a first conductive type diffusion region In the substrate closer to the second side, wherein at least a portion of the diffusion region is located in the substrate outside the second side, and the diffusion region and one of the low voltage components are lightly doped with a drain region, using the same process Forming; forming a first conductivity type first source and a first conductivity type first drain in the substrate on the first side of the first gate and the second side, respectively, viewed from a top view , the first bungee and the a gate is separated by a portion of the diffusion region, and the first source is located in the first well region; wherein the substrate comprises a non-epilation substrate, and the DDDMOS device manufacturing method further comprises forming a second conductive a first deep well zone in the substrate, the second conductivity type first deep well zone adopting the same process step as forming a second deep well zone of the low voltage component, and the first well zone, the diffusion zone, the first A source and the first drain are located in the first deep well region. A method for manufacturing a double diffused drain metal oxide semiconductor (DDDMOS) device, comprising: Providing a P-type substrate for forming the DDDMOS device and another low voltage component; forming a second conductivity type first well region in the substrate, and the first well region and one of the low voltage components a region formed by the same process step; forming a first gate on the substrate, the first gate having a first side and a second side opposite to each other in a channel direction, wherein a portion of the first well region is located Being relatively close to the first gate of the first side; forming a first conductivity type diffusion region in the substrate relatively close to the second side, wherein at least a portion of the diffusion region is located outside the second side In the substrate, the diffusion region and one of the low-voltage components are lightly doped with a drain region, and are formed by the same process step; respectively forming a first conductivity type first source and a first conductivity type first drain The first gate and the second side of the substrate are viewed from a top view, and the first drain and the first gate are separated by a portion of the diffusion region, and the first a source is located in the first well region; and an epitaxial layer is formed on the substrate, and The first well region, the diffusion region, the first source and the first drain are located in the epitaxial layer, and the first gate is located on the epitaxial layer. The method for fabricating a DDDMOS device according to claim 7, further comprising forming a second conductivity type buried layer in the substrate under the epitaxial layer. The method for manufacturing a DDDMOS device according to claim 6 or 7, further comprising forming at least one oxidation zone on the substrate to define an element region, and forming a component by using the same process step of forming the first well region. The isolation region is below the field oxidation region relatively close to the first drain side. Manufacturer of DDDMOS components as described in claim 6 or 7 The low voltage component further includes a second gate, a second source, and a second drain, and the first gate, the first source, and the first drain respectively utilize The second gate, the second source, and the second drain are formed in the same process step. The DDDMOS device of claim 1 or 2, wherein the first conductivity type is P-type or N-type, and the second conductivity type corresponds to the first conductivity type being N-type or P-type. The DDDMOS device of claim 1 or 2, wherein the first well region and the diffusion region do not overlap each other. The DDDMOS device of claim 1 or 2, wherein the diffusion region comprises a plurality of sub-diffusion regions. The DDDMOS device of claim 13, wherein the plurality of sub-diffusion regions are viewed from a top view and have a matrix pattern arrangement. The method for fabricating a DDDMOS device according to claim 6 or 7, wherein the first conductivity type is P-type or N-type, and the second conductivity type corresponds to the first conductivity type being N-type or P-type. The DDDMOS device manufacturing method according to claim 6 or 7, wherein the first well region and the diffusion region do not overlap each other. The method of fabricating a DDDMOS device according to Item 6 or 7, wherein the diffusion region comprises a plurality of sub-diffusion regions. The method for fabricating a DDDMOS device according to Item 17, wherein the plurality of sub-diffusion regions are viewed from a top view and have a matrix pattern arrangement.