TWI512984B - Lateral double diffused metal oxide semiconductor device and manufacturing method thereof - Google Patents

Lateral double diffused metal oxide semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
TWI512984B
TWI512984B TW101119457A TW101119457A TWI512984B TW I512984 B TWI512984 B TW I512984B TW 101119457 A TW101119457 A TW 101119457A TW 101119457 A TW101119457 A TW 101119457A TW I512984 B TWI512984 B TW I512984B
Authority
TW
Taiwan
Prior art keywords
region
upper surface
field oxide
gate
field
Prior art date
Application number
TW101119457A
Other languages
Chinese (zh)
Other versions
TW201349499A (en
Inventor
Tsung Yi Huang
Original Assignee
Richtek Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Richtek Technology Corp filed Critical Richtek Technology Corp
Priority to TW101119457A priority Critical patent/TWI512984B/en
Publication of TW201349499A publication Critical patent/TW201349499A/en
Application granted granted Critical
Publication of TWI512984B publication Critical patent/TWI512984B/en

Links

Description

Lateral double-diffused metal oxide semiconductor device and method of manufacturing same

The present invention relates to a lateral double diffused metal oxide semiconductor (LDMOS) device and a method of fabricating the same, and more particularly to an LDMOS device having a high breakdown protection voltage and a method of fabricating the same.

1A-1C are cross-sectional, perspective, and top views, respectively, of a prior art lateral double diffused metal oxide semiconductor (LDMOS) device 100. As shown in FIGS. 1A-1C, the P-type substrate 11 has an isolation region 12 surrounding a closed region (as indicated by the thick black border of the isolation region 12 in FIG. 1C) to define the function of the LDMOS device 100. The region 12, the isolation region 12 and the field oxide region 12a are, for example, a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure as shown. The LDMOS device 100 includes an N-type well region 14, a gate 13, a drain 15, a source 16, a body region 17, a body electrode 17a, and a field oxide region 12a. Wherein, the N-type well region 14, the drain 15 and the source 16 are formed by lithography to form a photoresist or/and a part or all of the gate 13 is used as a mask to define regions and respectively adopt ion implantation technology. The N-type impurity is implanted into the defined region in the form of accelerated ions. Wherein, the drain 15 and the source 16 are respectively located below the two sides of the gate 13; the body region 17 and the body pole 17a are formed by photoresist by lithography or/and some or all of the gate 13 is used as a mask to define Each region, and ion implantation technique, respectively, implants P-type impurities into the defined region in the form of accelerated ions. Further, in the LDMOS device, a part of the gate 13 is located on the field oxide region 12a. LDMOS element The components are high voltage components, ie they are designed to supply higher operating voltages. The higher the breakdown protection voltage of the LDMOS device, the lower the conduction resistance value, and the wider the application range. In general, the breakdown protection voltage and the on-resistance cannot be balanced. To reduce the on-resistance of the LDMOS device, the ion implantation parameters must be changed, thus sacrificing the breakdown protection voltage; or increasing the ion implantation step in a specific region. Additional lithography and implantation steps are required, which will increase manufacturing costs to achieve the desired conduction resistance and breakdown protection voltage.

In view of the above, the present invention is directed to the deficiencies of the prior art described above, and proposes an LDMOS device and a manufacturing method thereof, which can improve the collapse protection voltage and increase the application of the component without increasing the process steps and without sacrificing the conduction resistance value of the component operation. range. In addition, the ion implantation parameters of the LDMOS device of the present invention can be shared with the low voltage device, that is, integrated into the process of the low voltage device to simultaneously manufacture the high voltage component and the low voltage component on the same wafer.

It is an object of the present invention to provide a lateral double diffused metal oxide semiconductor (LDMOS) device and a method of fabricating the same.

In order to achieve the above object, the present invention provides an LDMOS device formed in a first conductive type substrate having an upper surface, the LDMOS device comprising: a second conductive type high voltage well region formed on the upper surface a first field oxide region formed on the upper surface, the first field oxidation region being located in the high voltage well region; and a gate formed on the upper surface The gate includes a first portion located on the first field oxide region; a second conductivity type source and a second conductivity type drain are respectively formed under the upper surface on both sides of the gate; a conductive body region formed on the upper a surface of the substrate, the source is located on the same side of the gate, and the source is located in the body region; and at least a second field oxide region is formed on the upper surface, as viewed from a top view, A second field oxide zone is located between the first field oxide zone and the drain.

In another aspect, the present invention also provides a method for fabricating a lateral double diffused metal oxide semiconductor (LDMOS) device, comprising: providing a first conductive type substrate having an upper surface; forming a first field oxide region and at least a second field oxide region on the upper surface; forming a second conductivity type high voltage well region in the substrate under the upper surface, viewed from a top view, the second conductivity type The high-voltage well region includes the first field oxide region and the at least one second field oxide region; forming a gate on the upper surface, and the gate portion includes a first portion located on the first field oxide region; And forming a second conductive type source and a second conductive type drain under the upper surface of the gate, and forming a first conductive type body region in the substrate below the upper surface, and the source a pole is located on the same side of the gate, and the source is located in the body region, wherein the drain is located outside the second field oxidation region farthest from the gate; wherein the high voltage well region is formed in the first field Oxidation zone and the second After the oxidation region is formed, so that the distribution of the second conductivity type impurity concentration of the well region of high pressure, related to the position of the second field oxide region.

In a preferred embodiment, between the first field oxide region and the at least one second field oxide region, at least one open region is defined, and the second conductive type impurity concentration of the open region below the upper surface is A concentration of the second conductivity type impurity higher than the first field oxide region and the second field oxide region.

In the above preferred embodiment, the gate further includes a second portion on the upper surface above the open area, and the second portion has a dielectric layer connected to the upper surface.

In the foregoing embodiment, the gate may further include a third portion located above the second field oxide region.

In a preferred embodiment, the LDMOS device preferably includes a plurality of second field oxide regions between the first field oxide region and the adjacent second field oxide region and the adjacent second field oxide region. And defining a plurality of open regions, wherein the second conductive type impurity concentration of the open region below the upper surface is higher than the second conductive type impurity concentration of the first field oxide region and the second field oxide region.

In the above preferred embodiment, from the top view, the area of the open area relatively close to the drain is larger than the area of the open area relatively close to the first field oxide.

In still another embodiment, the body region and the substrate may be separated by the high voltage well region such that the body region is not directly connected to the substrate; or at least a portion of the body region may be connected to the substrate, or The substrate is connected via a first conductivity type connection well region to electrically connect the body region to the substrate.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.

Referring to Figures 2A-2D, there is shown a first embodiment of the present invention. This embodiment shows a schematic diagram of a method of fabricating an LDMOS device 200 to which the present invention is applied. 2A-2B is a schematic perspective view, FIG. 2C is a schematic cross-sectional view, and FIG. 2D is a top view. First, as shown in FIG. 2A, a substrate 21 having an upper surface 21a and a conductive type of the substrate 21 is, for example, a P type but not It is limited to P type (it may be N type in other embodiments); and the substrate 21 may be, for example, a non-excipherated germanium substrate or an epitaxial substrate. Next, please continue to refer to FIG. 2A. The same, but not limited to, the same process steps can be used to form the isolation region 22 and the field oxide regions 22a and 22b on the upper surface 21a, as viewed from above (see FIG. 2D). The field oxide regions 22a and 22b are located in the high voltage well region 24 formed by subsequent processing steps; wherein the isolation region 22 and the field oxide regions 22a and 22b are, for example, STI structures or regions oxidized LOCOS structures as shown. Next, an ion implantation technique is used to implant, for example, but not limited to, an N-type impurity, in the form of an accelerated ion, into a defined region, and an N-type high voltage well region 24 is formed in the substrate 21 under the upper surface 21a. It is to be noted that since the field oxide regions 22a and 22b have a masking effect on the above-mentioned accelerated ions; therefore, the high-pressure well region 24 is formed after the field oxide regions 22a and 22b are formed, and the N-type impurity concentration in the high-pressure well region 24 is formed. The distribution is related to the position of the field oxide region 22b; in the present embodiment, between the field oxide regions 22a and 22b, the defined opening region 221 (see FIGS. 2C and 2D) is below the upper surface 21a. The N-type impurity concentration is higher than the N-type impurity concentration under the field oxide regions 22a and 22b. Next, referring to FIGS. 2B, 2C, and 2D, a gate 23, a drain 25, a source 26, a body region 27, and a body electrode 27a are formed. Here, as shown, the gate 23 is formed on the upper surface 21a, and a portion of the gate 23 is located on the field oxide region 22a. The drain 25 and the source 26 are, for example, N-type but not limited to N-type, respectively located under the upper surface 21a of both sides of the gate 23, and viewed from the top view 2D, the drain 25 and the source 26 are gated. 23 is spaced apart from the field oxide regions 22a and 22b; wherein the body region 27 is formed in the upper high voltage well region 24 of the upper surface 21a, both the source 26 and the source 26 are located on the same side of the gate 23, and the source 26 is located in the body region 27, The drain 25 is located outside the field oxide region 22b farthest from the gate 23; the drain 25 is formed in the high voltage well region 24 on the other side of the gate 23. Among them, N-type source 26 and N The type drain 25 is formed under the upper surface 21a by a lithography technique and/or with some or all of the gate 23 and the field oxide regions 22a and 22b as masks to define regions and respectively adopt ion implantation technology. An N-type impurity is formed in the form of an accelerated ion implanted in a defined region. The P-type body region 27 and the P-type body electrode 27a are formed under the upper surface 21a, and are defined by lithography and/or with some or all of the gate 23 and the isolation region 22 as a mask, and the region is defined and ion-implanted. The technique is to form P-type impurities in the form of accelerated ions implanted into defined areas. The source 26 and the drain 25 can be completed by the same or different lithography process steps and ion implantation steps, and the order of the process steps formed by the source 26, the drain 25 and the body region 27 and the body electrode 27a can be changed. .

In the aforementioned prior art LDMOS device 100, the drift region between the body region 17 and the drain 15 is completely covered by the gate 13 and the field oxide region 12a. Unlike the prior art, in the present embodiment, the drift region in the LDMOS device 200 is not completely covered by the gate 23 and the field oxide regions 22a and 22b, and the open region 221 between the field oxide regions 22a and 22b. Part of the upper surface 21a of the high-pressure well region 24 is exposed, so that an ion implantation process step of forming the high-voltage well region 24 is performed, and at the opening region 221, more impurities are implanted into the substrate so that the open region 221 is above Below the surface 21a, the N-type impurity concentration is high. The advantages of this arrangement include: in terms of component specifications, compared with the prior art, the application of the present invention can improve the collapse protection voltage of the LDMOS component, especially to mitigate the Kirk effect, and more obvious, to make the conduction collapse protection. The voltage can be greatly increased; in the process, the field oxide region 22b can be formed by the same process steps as the field oxide region 22a and the isolation region 22, without requiring additional process steps, thereby reducing manufacturing costs.

Figure 3 is a cross-sectional view showing a second embodiment of the present invention for applying the LDMOS device 300 of the present invention. As shown in the figure, this embodiment The LDMOS device 300 has a functional region defined by the isolation region 32; the LDMOS device 300 includes field oxide regions 32a and 32b, a gate 33, a high voltage well region 34, a drain 35, a source 36, a body region 37, and a body electrode 37a. . The difference from the first embodiment is that in the present embodiment, the gate 33 includes a first portion 33a located above the field oxide region 32a, and a second portion 33b on the upper surface 31a above the opening region 321, A third portion 33c is located above the field oxidation zone 32b. It should be noted that the second portion 33b preferably has a dielectric layer (that is, the gate 33 includes a gate electrode and a gate dielectric layer), and the dielectric layer is connected to the upper surface 31a to avoid the gate 33 and the high voltage well region. 34 direct electrical connection. Further, the third portion 33c may not be present, and is also included in the scope of the present invention.

Figure 4 is a cross-sectional view showing a third embodiment of the present invention for applying the LDMOS device 400 of the present invention. As shown, the LDMOS device 400 of the present embodiment has a functional area defined by the isolation region 42; the LDMOS device 400 includes field oxide regions 42a, 42b and 42c, a gate 43, a high voltage well region 44, a drain 45, and a source. The pole 46, the body region 47, and the body pole 47a. The difference from the first embodiment is that in the present embodiment, the field oxide regions 42b and 42c between the field oxide region 42a and the drain 45 are plural, and the field oxide region 42a and the adjacent field oxide region 42b. Between and between adjacent field oxide regions 42b and 42c, a plurality of open regions are defined, as shown in the open regions 421 and 422, and the N-type impurity concentrations of the open regions 421 and 422 below the upper surface 41a are high. The N-type impurity concentration under the field oxide region 42a and the field oxide regions 42b and 42c.

Fig. 5 is a cross-sectional view showing a fourth embodiment of the present invention for applying the LDMOS device 500 of the present invention. As shown, the LDMOS device 500 of the present embodiment has a functional area defined by the isolation region 52; the LDMOS device 500 includes field oxide regions 52a, 52b and 52c, a gate 53, a high voltage well region 54, a drain 55, and a source. The pole 56, the body region 57, and the body pole 57a. With the third The embodiment differs in that, in this embodiment, similar to the second embodiment, the gate 53 covers the field oxide regions 52a, 52b, and 52c and the plurality of open regions therebetween. Of course, it is necessary to pay attention to the opening region. A portion of the gate 53 preferably has a dielectric layer (i.e., the gate 53 includes a gate electrode and a gate dielectric layer) that is coupled to the upper surface 51a such that the gate 53 is not directly electrically coupled to the high voltage well region 54.

Figure 6 is a cross-sectional view showing a fifth embodiment of the present invention for applying the LDMOS device 600 of the present invention. As shown, the LDMOS device 600 of the present embodiment has a functional area defined by an isolation region 62; the LDMOS device 600 includes field oxide regions 62a, 62b, 62c and 62d, a gate 63, a high voltage well region 64, and a drain 65. The source 66, the body region 67, and the body pole 67a. This embodiment is intended to illustrate the open area defined between the plurality of field oxide regions 62a, 62b, 62c and 62d in the LDMOS device 600 of the present invention, and the size of the field oxide regions 62a, 62b, 62c and 62d can be used to control the N-type. The amount of impurities implanted in the high pressure well region 64 is optimized to optimize the performance of the present invention. For example, the open region relatively close to the drain 65 can be designed to be larger, and the open region relatively closer to the field oxide region 62a is smaller. To optimize the turn-on protection voltage of the LDMOS device 600.

Figure 7 is a top plan view showing the LDMOS high voltage component 700 of the present invention showing a sixth embodiment of the present invention. As shown, the LDMOS device 700 of the present embodiment has a functional region defined by an isolation region 72; the LDMOS device 700 includes field oxide regions 72a and 72b, a gate 73, a high voltage well region 74, a drain 75, and a source 76. The body region 77 and the body pole 77a. This embodiment is intended to illustrate that in the LDMOS device 700 to which the present invention is applied, in the field oxide region 72b, different numbers of open regions can be formed at different positions according to requirements to increase the collapse protection voltage of the LDMOS device. The arrangement of 72b is also within the scope of the invention.

Figure 8 is a top plan view showing the LDMOS device 800 of the present invention showing a seventh embodiment of the present invention. As shown, the LDMOS device 800 of the present embodiment has a functional area defined by an isolation region 82; the LDMOS device 800 includes field oxide regions 82a, 82b, 82c and 82d, a gate 83, a high voltage well region 84, and a drain. 85. A source 86, a body region 87, and a body pole 87a. This embodiment is intended to illustrate the position of the complex field oxide regions 82a, 82b, 82c, and 82d in the LDMOS device 800 to which the present invention is applied. From the top view, the width of the open region is adjusted according to electrical requirements.

Fig. 9 is a cross-sectional view showing the eighth embodiment of the present invention for applying the LDMOS device 900 of the present invention. As shown, the LDMOS device 900 of the present embodiment has a functional area defined by an isolation region 92; the LDMOS device 900 includes field oxide regions 92a and 92b, a gate 93, a high voltage well region 94, a drain 95, and a source 96. The body region 97 and the body electrode 97a. Different from the first embodiment, in the first embodiment, the body region 27 and the substrate 21 are separated by the high voltage well region 24, so that the body region 27 is electrically disconnected from the substrate 21, so that the LDMOS device 200 can be As a high side component in the power supply circuit. Differently, as shown in the figure, in the LDMOS device 900 of the present embodiment, a portion of the body region 97 is connected to the substrate 91 to electrically connect the body region 97 with the substrate 91, which enables the LDMOS device 900 to function as a power supply circuit. Lower side component.

Fig. 10 is a perspective view showing the ninth embodiment of the present invention, which is an application of the LDMOS device 1000 of the present invention. As shown, the LDMOS device 1000 of the present embodiment has a functional area defined by the isolation region 102; the LDMOS device 1000 includes field oxide regions 102a and 102b, a gate 103, a high voltage well region 104, a drain 105, and a source 106. The body region 107 and the body electrode 107a. The difference from the eighth embodiment is that in the embodiment, a part of the body region 107 Between the substrate 101 and the substrate 101, via the P-type connection well region 108, the body region 107 is electrically connected to the substrate 101. This allows the LDMOS device 1000 to function as a low side component in the power supply circuit.

Figure 11 is a top plan view showing the LDMOS high voltage component 1100 of the present invention showing the tenth embodiment of the present invention. As shown, the LDMOS device 1100 of the present embodiment has a functional region defined by the isolation region 112; the LDMOS device 1100 includes field oxide regions 112a and 112b, a gate 113, a high voltage well region 114, a drain 115, and a source 116. The body region 117 and the body pole 117a. This embodiment is intended to illustrate that in the LDMOS device 1100 to which the present invention is applied, in the field oxide region 112b, the shape of the opening region can be viewed from the top view according to the requirements, and is not limited to the rectangular shape in the foregoing embodiments. It may also be of any shape, and the arrangement of such field oxide zone 112b is also within the scope of the invention.

Figures 12A-12C show a characteristic curve of a prior art LDMOS device. Please refer to FIG. 12A, which shows the characteristic curve of the drain current to the drain voltage when the prior art LDMOS device operates in a non-conducting state. According to the characteristic curve, the non-conduction collapse protection voltage of the prior art LDMOS device can be known. It is 76V. Next, please refer to FIG. 12B, which shows the characteristic curve of the gate voltage of the prior art LDMOS device, the drain current (left vertical axis) and the conductance (right vertical axis). According to the characteristic curve, the prior art LDMOS device can be known. The threshold voltage is approximately 1V. Next, please refer to FIG. 12C, which shows the characteristic curve of the drain current to the drain voltage when the prior art LDMOS device operates in the on state. According to the characteristic curve, the conduction breakdown voltage of the prior art LDMOS device can be known. It is 54V.

On the other hand, Figs. 13A-13C show a characteristic curve using the LDMOS device of the present invention, the basic operating voltage of which is the same as that of the prior art LDMOS device shown in the aforementioned 12A-12C. Please refer to Figure 13A to show this When the LDMOS device of the present invention is operated in a non-conducting state, the characteristic curve of the drain current to the drain voltage, according to the characteristic curve, it can be known that the non-conduction collapse protection voltage of the LDMOS device using the present invention is about 100V. Referring to FIG. 13B, the characteristic curve of the gate voltage of the LDMOS device using the LDMOS device of the present invention (left vertical axis) and conductance (right vertical axis) is shown. According to the characteristic curve, the LDMOS using the present invention can be known. The threshold voltage of the device is also about 1V, and its on-resistance is comparable to the prior art LDMOS device shown in Figures 12A-12C above. Referring to FIG. 13C, the characteristic curve of the drain current to the drain voltage when the LDMOS device of the present invention is operated in the on state is shown. According to the characteristic curve, the conduction breakdown protection of the LDMOS device using the present invention can be known. The voltage is approximately 75V.

Comparing the characteristic curve of the prior art LDMOS device shown in FIG. 12A-12C with the characteristic curve of the LDMOS device shown in FIG. 13A-13C, it can be known that the application of the present invention can greatly improve the collapse protection voltage of the LDMOS device without sacrificing. On resistance.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as a threshold voltage adjustment region, may be added without affecting the main characteristics of the component; for example, the lithography technology is not limited to the reticle technology, and may also include electron beam lithography; As seen from the top view, the LDMOS device to which the present invention is applied is not limited to being rectangular, but may be circular or serpentine or the like. The above and other equivalent variations are intended to be covered by the scope of the invention.

11,21,31,41,51,61,91‧‧‧substrate

12,22,32,42,52,62,72,82,92,102,112‧‧ ‧Isolation area

12a, 22a, 22b, 32a, 32b, 42a, 42b, 42c, 52a, 52b, 52c, 62a, 62b, 62c, 62d, 72a, 72b, 82a, 82b, 82c, 82d, 92a, 92b, 102a, 102b, 112a, 112b‧‧‧ field oxidation zone

13,23,33,43,53,63,73,83,93,103,113‧‧ ‧ gate

14,24,34,44,54,64,74,84,94,104,114‧‧‧High-pressure well area

15,25,35,45,55,65,75,85,95,105,115‧‧‧bungee

16,26,36,46,56,66,76,86,96,106,116‧‧‧Source

17,27,37,47,57,67,77,87,97,107,117‧‧‧ body area

17a, 27a, 37a, 47a, 57a, 67a, 77a, 87a, 97a, 107a, 117a‧‧ ‧ body

21a, 31a, 41a, 51a, 61a, 91a, 101a‧‧‧ upper surface

108‧‧‧Connected well area

100,200,300,400,600,700,800,900,1000,1100‧‧‧LDMOS components

221,321,421,422‧‧‧open area

1A-1C are cross-sectional, perspective, and top views, respectively, of a prior art LDMOS device 100.

2A-2D shows a first embodiment of the present invention.

Figure 3 shows a second embodiment of the invention.

Fig. 4 shows a third embodiment of the present invention.

Fig. 5 shows a fourth embodiment of the present invention.

Fig. 6 shows a fifth embodiment showing the present invention.

Fig. 7 shows a sixth embodiment showing the present invention.

Fig. 8 shows a seventh embodiment showing the present invention.

Fig. 9 shows an eighth embodiment showing the present invention.

Fig. 10 shows a ninth embodiment showing the present invention.

Fig. 11 shows a tenth embodiment showing the present invention.

Figures 12A-12C show a characteristic curve of a prior art LDMOS device.

Figures 13A-13C show a characteristic curve using the LDMOS device of the present invention.

21‧‧‧Substrate

22‧‧‧Insert Area

22a, 22b‧‧‧ field oxidation zone

23‧‧‧ gate

24‧‧‧High-pressure well area

25‧‧‧汲polar

26‧‧‧ source

27‧‧‧ Body area

27a‧‧‧ body pole

100‧‧‧LDMOS components

221‧‧‧Open area

Claims (10)

  1. A lateral double diffused metal oxide semiconductor (LDMOS) device is formed in a first conductive type substrate having an upper surface, comprising: a second conductive type high voltage well region formed on a first field oxidation region formed on the upper surface, the first field oxidation region being located in the high voltage well region; a gate formed on the upper surface On the surface, the gate includes a first portion on the first field oxide region; a second conductivity type source and a second conductivity type drain are respectively formed under the upper surface on both sides of the gate a first conductive type body region formed in the substrate under the upper surface, the source is located on the same side of the gate, and the source is located in the body region; and at least a second field oxide region is formed On the upper surface, viewed from a top view, the second field oxide region is located between the first field oxide region and the drain; wherein the first field oxide region and the at least one second field oxide region are between Defining at least one open area, the opening The concentration of the second conductivity type impurity under the upper surface is higher than the concentration of the second conductivity type impurity below the first field oxide region and the second field oxide region; wherein the gate further comprises a second portion located at the The upper surface above the open area and the second portion has a dielectric layer coupled to the upper surface.
  2. The LDMOS device of claim 1, wherein the gate further comprises a third portion above the second field oxide region.
  3. A lateral double diffused metal oxide semiconductor (LDMOS) device formed in a first conductivity type In the substrate, the substrate has an upper surface, comprising: a second conductive type high voltage well region formed in the substrate under the upper surface; a first field oxidation region formed on the upper surface, viewed from above The first field oxide region is located in the high voltage well region; a gate is formed on the upper surface, and the gate electrode includes a first portion located on the first field oxide region; and a second conductivity type source a pole and a second conductive type drain are respectively formed under the upper surface of the gate; a first conductive type body region is formed in the substrate below the upper surface, and the source is located at the gate On the same side, and the source is located in the body region; and at least a second field oxidation region is formed on the upper surface, the second field oxidation region is located in the first field oxidation region and Between the drains; wherein the LDMOS device includes a plurality of second field oxide regions, and between the first field oxide region and the adjacent second field oxide region, and between the adjacent second field oxide regions, defining a plurality An open area, the second conductive type impurity under the upper surface is thick , Higher than the first field oxide region and the second field of the second conductivity type impurity concentration of the bottom oxidation zone.
  4. The LDMOS device of claim 3, wherein the area of the open area relatively close to the drain is larger than the area of the open area relatively close to the first field oxide area, as viewed from above.
  5. The LDMOS device of claim 1 or 3, wherein the body region and the substrate are separated by the high voltage well region such that the body region is not directly connected to the substrate; or at least part of the body The substrate is connected to the substrate or connected to the substrate via a first conductive type connection well region to electrically connect the body region to the substrate.
  6. A method for fabricating a lateral double diffused metal oxide semiconductor (LDMOS) device, comprising: providing a first conductive type substrate having an upper surface; forming a first field oxide region and at least one a second field oxide region is formed on the upper surface; a second conductivity type high voltage well region is formed in the substrate under the upper surface, as viewed from a top view, the second conductive type high voltage well region includes the first field An oxidation region and the at least one second field oxidation region; forming a gate on the upper surface, and the gate includes a first portion on the first field oxide region; and forming a second conductivity type source and a second conductive type drain is formed below the upper surface of the gate and forms a first conductive type body region in the substrate below the upper surface, and the source is located on the same side of the gate, and the a source is located in the body region, wherein the drain is located outside the second field oxidation region farthest from the gate; wherein the high voltage well region is formed in the first field oxide region and the second field oxide region After that, so that a distribution of a second conductivity type impurity concentration in the well region, related to a position of the second field oxidation region; wherein at least one open region is defined between the first field oxidation region and the at least one second field oxidation region The concentration of the second conductivity type impurity under the upper surface of the open region is higher than the concentration of the second conductivity type impurity below the first field oxide region and the second field oxide region; wherein the gate further comprises a second portion Located on the upper surface above the open area, and the second portion has a dielectric layer connected to the upper surface.
  7. The method of fabricating an LDMOS device according to claim 6, wherein the gate further comprises a third portion located above the second field oxide region.
  8. A method for fabricating a lateral double diffused metal oxide semiconductor (LDMOS) device, comprising: providing a first conductive type substrate having an upper surface; forming a first field oxide region and at least one a second field oxide region is formed on the upper surface; a second conductivity type high voltage well region is formed in the substrate under the upper surface, as viewed from a top view, the second conductive type high voltage well region includes the first field An oxidation region and the at least one second field oxidation region; forming a gate on the upper surface, and the gate includes a first portion on the first field oxide region; and forming a second conductivity type source and a second conductive type drain is formed below the upper surface of the gate and forms a first conductive type body region in the substrate below the upper surface, and the source is located on the same side of the gate, and the a source is located in the body region, wherein the drain is located outside the second field oxidation region farthest from the gate; wherein the high voltage well region is formed in the first field oxide region and the second field oxide region After that, so that a distribution of a second conductivity type impurity concentration in the well region, related to a position of the second field oxidation region; wherein the LDMOS device includes a plurality of second field oxidation regions, and in the first field oxidation region and adjacent second Between the field oxidation regions and between the adjacent second field oxidation regions, defining a plurality of open regions, the second conductivity type impurity concentration of the open regions below the upper surface, higher than the first field oxidation region and the first The concentration of the second conductivity type impurity below the two field oxidation regions.
  9. The method of fabricating an LDMOS device according to claim 8, wherein the area of the open area relatively close to the drain is larger than the area of the open area relatively close to the first field oxide area.
  10. LDMOS component manufacturer as described in claim 6 or 8 The method, wherein the body region and the substrate are separated by the high voltage well region such that the body region is not directly connected to the substrate; or at least a portion of the body region is connected to the substrate, or via a first conductivity type The connection well region is connected to the substrate to electrically connect the body region to the substrate.
TW101119457A 2012-05-31 2012-05-31 Lateral double diffused metal oxide semiconductor device and manufacturing method thereof TWI512984B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW101119457A TWI512984B (en) 2012-05-31 2012-05-31 Lateral double diffused metal oxide semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW101119457A TWI512984B (en) 2012-05-31 2012-05-31 Lateral double diffused metal oxide semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
TW201349499A TW201349499A (en) 2013-12-01
TWI512984B true TWI512984B (en) 2015-12-11

Family

ID=50157546

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101119457A TWI512984B (en) 2012-05-31 2012-05-31 Lateral double diffused metal oxide semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
TW (1) TWI512984B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI562374B (en) * 2014-03-04 2016-12-11 Vanguard Int Semiconduct Corp Semiconductor device and method of manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050073007A1 (en) * 2003-10-01 2005-04-07 Fu-Hsin Chen Ldmos device with isolation guard rings
US20070267693A1 (en) * 2006-05-22 2007-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Suppression of hot-carrier effects using double well for thin gate oxide ldmos embedded in hv process
US20120104492A1 (en) * 2010-10-29 2012-05-03 Macronix International Co., Ltd. Low on-resistance resurf mos transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050073007A1 (en) * 2003-10-01 2005-04-07 Fu-Hsin Chen Ldmos device with isolation guard rings
US20070267693A1 (en) * 2006-05-22 2007-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Suppression of hot-carrier effects using double well for thin gate oxide ldmos embedded in hv process
US20120104492A1 (en) * 2010-10-29 2012-05-03 Macronix International Co., Ltd. Low on-resistance resurf mos transistor

Also Published As

Publication number Publication date
TW201349499A (en) 2013-12-01

Similar Documents

Publication Publication Date Title
KR100867574B1 (en) Power device and method for manufacturing the same
US7678656B2 (en) Method of fabricating an enhanced resurf HVPMOS device
US7345341B2 (en) High voltage semiconductor devices and methods for fabricating the same
KR100781213B1 (en) Lateral Double-diffused Field Effect Transistor and Integrated Circuit Having Same
US20080160706A1 (en) Method for fabricating semiconductor device
US6946705B2 (en) Lateral short-channel DMOS, method of manufacturing the same, and semiconductor device
US8188542B2 (en) Field effect transistors including variable width channels and methods of forming the same
US20080093641A1 (en) Method of manufacturing a multi-path lateral high-voltage field effect transistor
US20080237703A1 (en) High voltage semiconductor devices and methods for fabricating the same
US7208397B2 (en) Transistor having an asymmetric source/drain and halo implantation region and a method of forming the same
US7851857B2 (en) Dual current path LDMOSFET with graded PBL for ultra high voltage smart power applications
TWI438898B (en) Self-aligned complementary ldmos
EP1779416A2 (en) Asymmetric hetero-doped high-voltage mosfet (ah2mos)
CN101111942A (en) Drain extended pmos transistors and methods for making the same
US7109562B2 (en) High voltage laterally double-diffused metal oxide semiconductor
US20050006701A1 (en) High voltage metal-oxide semiconductor device
US6888210B2 (en) Lateral DMOS transistor having reduced surface field
US8120105B2 (en) Lateral DMOS field effect transistor with reduced threshold voltage and self-aligned drift region
US5891782A (en) Method for fabricating an asymmetric channel doped MOS structure
DE102011088638B3 (en) Method for manufacturing high voltage component e.g. N-channel metal oxide semiconductor transistor, in mobile telephone, involves forming connection to field structure, and coupling connection with potential distributing field in substrate
TWI384629B (en) Semiconductor structure and method of forming the same
JP2006510206A (en) Integrated circuit structure
US8304830B2 (en) LDPMOS structure for enhancing breakdown voltage and specific on resistance in biCMOS-DMOS process
CN100413089C (en) High-voltage mos device
US8853780B2 (en) Semiconductor device with drain-end drift diminution