TWI489617B - Semiconductor device and manufacturing method and operating method for the same - Google Patents

Description

Semiconductor device, manufacturing method and operating method thereof

The present invention relates to a semiconductor device, a method of fabricating the same, and a method of fabricating the same, and more particularly to a depletion metal oxide semiconductor (depletion MOS) device, a method of fabricating the same, and a method of operation.

A depletion metal oxide semiconductor has a characteristic that a current can be generated in a channel when the gate voltage is zero. However, this output current is a fixed value and cannot be applied to different circuits.

The invention provides a semiconductor device, a manufacturing method thereof and an operating method thereof, wherein the output current can be adjusted according to requirements.

According to the present invention, there is provided a semiconductor device comprising a substrate, a deep well, a first well, a first doped electrode region, a second doped electrode region, and a high cutoff voltage channel region. The substrate has a first conductivity type. The deep well is located within the substrate and has a second conductivity type opposite to the first conductivity type. The first well is located in the deep well and has at least one of a first conductivity type or a second conductivity type. The first doped electrode region has a first conductivity type and is located within the first well. The second doped electrode region has a second conductivity type located in the first well adjacent to the first doped electrode region. The high cut-off voltage channel region has a second conductivity type extending downward from the surface of the substrate in the first well and covering a portion of the surface of the second doped electrode region. The surface of the high cut-off voltage channel region has a first side, a second side, and a third side And the fourth side, the first side is opposite to the second side, the third side is opposite to the fourth side, and the first side and the second side are adjacent to the third side and the fourth side.

According to the present invention, there is provided a method of fabricating a semiconductor device comprising: providing a substrate having a first conductivity type; forming a deep well in the substrate, the deep well extending downward from the surface of the substrate and having a second conductivity type opposite to the first conductivity type; Forming the first well in the deep well, the first well extends downward from the surface of the substrate and has at least one of the first conductivity type or the second conductivity type; forming a high cutoff voltage channel region in the first well, the high cutoff voltage channel The region is extended downward from the surface of the substrate and has a second conductivity type; the first doped electrode region is formed at a position in the first well that does not have a high cutoff voltage channel region, and the first doped electrode region has a first conductivity type; The second doped electrode region is adjacent to the first doped electrode region, the second doped region has a second conductivity type, and a portion of the second doped electrode region is covered by the high cutoff voltage channel region; by adjusting the high cutoff voltage channel region The ratio of the second doped electrode region is covered to determine the output current of the semiconductor device.

According to the present invention, there is provided a method of operating a semiconductor device, wherein the semiconductor device comprises a substrate, a deep well, a first well, a first doped electrode region, a second doped electrode region, a third doped electrode region, and a high cutoff voltage channel region . The substrate has a first conductivity type; the deep well is located in the substrate and has a second conductivity type opposite to the first conductivity type; the first well is located in the deep well and has at least one of the first conductivity type or the second conductivity type; a doped electrode region is located in the first well and has a first conductivity type; the second doped electrode region has a second conductivity type, located in the first well adjacent to the first doped electrode region; and the third doped electrode region has The second conductivity type is located in the deep well and is oriented by the surface of the substrate Expanding downwardly and spaced apart from the second doped electrode region; the high cutoff voltage channel region is located in the first well and has a second conductivity type, extending downward from the surface of the substrate and covering a portion of the second doped electrode region a surface, wherein a surface of the high cut-off voltage channel region has a first side, a second side, a third side, and a fourth side, the first side being opposite to the second side, the third side and the fourth side The first side and the second side are adjacent to the third side and the fourth side. The operating method of the semiconductor device includes applying a bias voltage to the high cutoff voltage channel region; coupling the first doped electrode region to the first electrode, the first electrode being one of the cathode and the anode; and coupling the third doped electrode region In the second electrode, the second electrode is the other of the cathode and the anode.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments, together with the accompanying drawings,

Referring to FIGS. 1A and 1B, FIG. 1A is a top view of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a partial enlarged view of FIG. 1A. The semiconductor device 10 has a first well 13 in a deep well (not shown) of a substrate (not shown), and the first well 13 includes adjacent first doped electrode regions 14 and second doped electrode regions 15. A high cut-off voltage channel region 132 has a first side 132a, a second side 132b, a third side 132c and a fourth side 132d, wherein the first side 132a is opposite the second side 132b, and the third side 132c is opposite to the fourth side 132d. The first side 132a and the second side 132b are adjacent to the third side 132c and the fourth side 132d to form a closed section. High cutoff voltage channel region 132 covers a portion of the second doping The impurity electrode region 15. In this example, the semiconductor device in which the electrode is circularly surrounding the substrate is taken as an example, but in other embodiments, the semiconductor device may have other configurations, such as a semiconductor device in which the electrodes are arranged in a straight line.

In this example, the substrate 11 and the first doped electrode region 14 have a first conductivity type, for example, a P type. The deep well 12, the second doped electrode region 15 and the high cut-off voltage channel region 132 have a second conductivity type opposite to the first conductivity type, for example, an N-type. The first well 13 may have at least one of a first conductivity type or a second conductivity type. In other embodiments, the first conductivity type may be an N type and the second conductivity type is a P type.

Please refer to both Figure 2 and Figure 3. 2 is a cross-sectional view of the semiconductor device of FIG. 1B taken along section line A-A', and FIG. 3 is a cross-sectional view of the semiconductor device of FIG. 1B taken along section line B-B', the difference between the two is whether High cutoff voltage channel region 132.

In detail, the first doped electrode region 14 and the second doped electrode region 15 of the semiconductor device 10 are located in the first well 13 and disposed adjacent to each other. In the structure of FIG. 2, the high-cut voltage channel region 132 is extended downward from the surface of the substrate 11 and covers the surface of the second doped electrode region 15; in addition, a field layer 131 having a first conductivity type is also used from the substrate. The surface of 11 is expanded downward to cover the first doped electrode region 14. On the contrary, in the structure of FIG. 3, there is no high off-voltage channel region, but the field layer 131 covers both the first doping electrode region 14 and the second doping electrode region 15. In other words, the high cutoff voltage channel region 132 covers a portion of the second doped electrode region 15, and the field layer 131 covers all of the first doped electrode region 14 and the remaining second doped electrode region 15.

As shown in FIGS. 2 and 3, the semiconductor device 10 includes a third doped electrode region 16, a top doped region 19, a dielectric structure 18, and a gate structure. 17, wherein the top doped region 19 has a first conductivity type and the third doped electrode region 16 has a second conductivity type. The third doped electrode region 16 is located in the deep well and is spaced apart from the second doped electrode region 15. The dielectric structure 18 is, for example, a field oxide (FOX) between the second doped electrode region 15 and the third doped electrode region 16 on the substrate. The top doped region 19 is located within the deep well 12 and below the dielectric structure 18. The gate structure 17 is located above the high turn-off voltage channel region 132 and the dielectric structure 18.

As shown in FIG. 2 and FIG. 3, the semiconductor device 10 further includes an interlayer dielectric layer 21 on the surface of the substrate 11 and exposing the field layer 131, the high-cut voltage channel region 132, and the third doping electrode region 16. And part of the surface of the gate structure 17. The semiconductor device 10 further includes a first electrode 22, a second electrode 23 and a third electrode 24 on the interlayer dielectric layer 21 and respectively with the field layer 131, the high-cut voltage channel region 132, the third doping electrode region 16 and the gate Part of the surface of the pole structure 17 is in contact. In this example, the first electrode 22 is electrically connected to the first doped electrode region 14 and the second doped electrode region 15 , and the second electrode 23 is electrically connected to the third doped electrode region 16 , and the third electrode 24 is electrically connected. It is electrically connected to the gate structure 17, and the three electrodes can be used as an anode (source), a cathode (drain) or a gate of the applied component.

The semiconductor device 10 of the present embodiment can change the output current of the semiconductor device 10 by adjusting the ratio of the high-cut-off voltage channel region 132 covering the second doping electrode region 15. For example, please refer to FIG. 4A and FIG. 4B , which are diagrams showing the relationship between current and voltage of the semiconductor device of FIG. 1B under different high-cut voltage channel coverage angles θ. The semiconductor device of this embodiment is depleted, that is, when it is applied to the gate from the gate to the source voltage V _GS of 0, an output current can be measured. As can be seen from Fig. 4B, the larger the coverage angle θ angle, that is, the larger the ratio of the high-cut-off voltage channel region 132 covering the second doping electrode region 15, the larger the output current (the drain current) of the semiconductor device 10 is. . When θ = 360°, that is, the high-cut voltage channel region 132 is surrounded by a full turn, covering all of the second doped electrode regions, there is a current maximum.

In one embodiment, as shown in FIG. 5A, the number of high-cut-off voltage channel regions 132 may be two or more, and the size of each high-cut-off voltage channel region 132 may be different, and the output current is high in cutoff voltage. The channel region 132 covers the total proportional correlation of the second doped electrode regions 15, for example, related to the sum of the coverage angles θ. In this example, the size of each of the high cutoff voltage channel regions 132 is different, for example, θ ₄ > θ ₃ &gt _; θ ₂ &gt _; θ ₁ . In other embodiments, as shown in FIG. 5B, the interval angle α of each high cutoff voltage channel region may be different, for example, α ₄ >α ₃ >α ₂ >α ₁ .

6A through 14B illustrate a process of a semiconductor device in accordance with an embodiment of the present invention. The diagram labeled A is as shown in FIGS. 6A, 7A, 8A, ... 14A. The cross-sectional view taken along line AA' of the semiconductor device of FIG. 1B shows the position of the section line A-A'. Corresponding to the first well 13 having a high cut-off voltage channel region 132. The diagram labeled B is as shown in sections 6B, 7B, 8B, ... 14B. The cross-sectional view taken along line B-B' of the semiconductor device of Fig. 1B corresponds to the position of the section line B-B'. The first well 13 does not have a high cut-off voltage channel region 132.

In the figure, the P type is the first conductivity type (the conductive state of the substrate 11 and the first doping electrode region 14 and the like), and the N type is the second conductivity type (the deep well 12 and the second doping electrode region 15 and the like) Conductive state is marked as an example. However, the invention is not limited thereto.

Please refer to Figures 6A and 6B. First, a substrate 11 having a first conductivity type is provided, ion implantation is performed to form a deep well 12 having a second conductivity type in the substrate 11 and expanded downward from the surface of the substrate 11, and then ion implantation is performed to form the first well 13 In the deep well 12, and extending from the surface of the substrate 11, the first well 13 may have at least one of a first conductivity type and a second conductivity type, and both of them are taken as an example. A P-type well is also formed on the outside of the deep well 12.

Please refer to Figures 7A and 7B. The ions are implanted to form a top doped region 19 having a first conductivity type within the deep well 12.

Referring to FIGS. 8A and 8B, the ion cloth values are formed to form the field layer 131 having the first conductivity type in the first well and spread downward from the surface of the substrate 11. In Fig. 8A, the size of the field layer 131 is small; and in Fig. 8B, the size of the field layer 131 is large.

Referring to FIGS. 9A and 9B, a dielectric structure 18 is formed on the substrate 11. The dielectric structure 18 is, for example, a field oxide (FOX) and may be located above the top doped region 19 and is not limited to the field oxide as shown, but may also include shallow trench isolation (STI).

Referring to FIGS. 10A and 10B, the ion cloth values are formed to form a high-cut-off voltage channel region 132 having a second conductivity type adjacent to the field layer 131 in the first well 13 and extended downward from the surface of the substrate.

Referring to FIGS. 11A and 11B, a gate structure 17 is formed on the high turn-off voltage channel region 132 and extends onto the dielectric structure 18. The gate structure 17 may include a gate dielectric layer, a gate electrode layer, and a spacer. A gate electrode layer is formed on the gate dielectric layer. A spacer is formed on the opposite sidewalls of the gate dielectric layer and the gate electrode layer. In an embodiment, a sacrificial oxide (SAC oxide) may be formed on the surface of the substrate 11 before the gate dielectric layer is formed, and then removed. Sacrificial oxides are used to help form a good quality gate dielectric layer. The gate electrode layer may include polysilicon and a metal halide such as tungsten telluride formed on the polysilicon. The spacers may include cerium oxide such as Tetraethoxy silane (TEOS).

Please refer to Figures 12A and 12B. Forming a first doped electrode region 14 having a first conductivity type by ion implantation at the first well 13 , forming a second doped electrode region 15 having a second conductivity type at the first well 13 , and forming the second doped electrode region 15 at the first well 13 A third doped electrode region 16 having a second conductivity type is formed. The first doped electrode region 14 is adjacent to the second doped electrode region 15, and the third doped electrode region 16 and the second doped electrode region 15 are separated by a distance from the dielectric structure 18. In FIG. 12A, the first doped electrode region 14 is formed under the field layer 131, and the second doped electrode region is formed under the high cutoff voltage channel region 132.

Please refer to Figures 13A and 13B. Next, a step of depositing and patterning (such as a mask and etching) is performed to form an interlayer dielectric layer 21 on the surface of the substrate 11. The interlayer dielectric layer 21 exposes a portion of the surface of the field layer 131, the high cutoff voltage channel region 132, the gate structure 17, and the third doped electrode region 16.

Please refer to Figures 14A and 14B. Thereafter, a conductive layer is deposited and patterned (such as a mask and an etching step) to form a first electrode 22, a second electrode 23, and a third electrode 24 on the interlayer dielectric layer 21, filling up The openings of the interlayer dielectric layer 21 are in contact with the exposed surfaces of the field layer 131, the high cutoff voltage channel region 132, the third doped electrode region 16, and the gate structure 17, respectively. The first electrode 35, the second electrode 36, and the third electrode 37 can serve as an anode (source), a cathode (drain), and a gate of the application element.

Although the invention has been disclosed above by way of example, it is not intended to be limiting In the present invention, the scope of the present invention is defined by the scope of the appended claims, unless otherwise claimed.

11‧‧‧Substrate

12‧‧‧Shenjing

13‧‧‧First Well

131‧‧‧ field level

132‧‧‧High cut-off voltage channel area

132a‧‧‧ first side

132b‧‧‧Second side

132c‧‧‧ third side

132d‧‧‧4th side

14‧‧‧First doped electrode area

15‧‧‧Second doped electrode region

16‧‧‧ Third doped electrode area

17‧‧‧ gate structure

18‧‧‧Dielectric structure

19‧‧‧Top doped area

21‧‧‧Interlayer dielectric layer

22‧‧‧First electrode

23‧‧‧second electrode

24‧‧‧ third electrode

A-A’, B-B’‧‧‧ hatching

FIG. 1A is a top view of a semiconductor device in accordance with an embodiment of the present invention.

Fig. 1B is a partial enlarged view of Fig. 1A.

Figure 2 is a cross-sectional view of the semiconductor device of Figure 1B taken along section line A-A'.

Figure 3 is a cross-sectional view of the semiconductor device of Figure 1B taken along section line B-B'.

FIG. 4A is a graph showing the relationship between current and voltage of the semiconductor device of FIG. 1B at different coverage angles of the high cutoff voltage channel region.

Fig. 4B is a partial enlarged view of Fig. 4A.

FIG. 5A is a partially enlarged top view of a semiconductor device in accordance with another embodiment of the present invention.

FIG. 5B is a partially enlarged top view of a semiconductor device in accordance with still another embodiment of the present invention.

6A through 14B illustrate a process of a semiconductor device in accordance with an embodiment of the present invention. 6A, 7A, 8A, ... 14A are cross-sectional views taken along section line A-A' of the semiconductor device of FIG. 1B; and pictures 6B, 7B, 8B, ... 14B are shown along the 1B is a cross-sectional view taken along line B-B' of the semiconductor device.

13‧‧‧First Well

131‧‧‧ field level

132‧‧‧High cut-off voltage channel area

132a‧‧‧ first side

132b‧‧‧Second side

132c‧‧‧ third side

132d‧‧‧4th side

14‧‧‧First doped electrode area

15‧‧‧Second doped electrode region

A-A’, B-B’‧‧‧ hatching

Claims (18)

A semiconductor device comprising: a substrate having a first conductivity type; a deep well located in the substrate and having a second conductivity type opposite to the first conductivity type; a first well located in the deep well, and Having at least one of the first conductivity type or the second conductivity type; a first doped electrode region having the first conductivity type and located in the first well; and a second doped electrode region having the first a second conductivity type located in the first well adjacent to the first doped electrode region; a high cutoff voltage channel region located in the first well and having the second conductivity type, the high cutoff voltage channel region being the substrate a surface extending downwardly and covering a portion of the surface of the second doped electrode region; a field layer having the first conductivity type, the field layer being located in the first well adjacent to the high cutoff voltage channel The surface layer extends downward from the surface of the substrate and covers the surface of the first doped electrode region, wherein the surface of the high cutoff voltage channel region has a first side, a second side, and a first Three sides and a fourth side, the first side and The second side is opposite to the fourth side, and the first side and the second side are adjacent to the third side and the fourth side. The semiconductor device of claim 1, comprising more than two of the high-cut voltage channel regions. The semiconductor device of claim 1, further comprising: a third doped electrode region having the second conductivity type, the third doping The electrode region is located within the deep well and extends downwardly from the surface of the substrate and is spaced from the second doped electrode region by a distance. The semiconductor device of claim 3, further comprising: a dielectric structure formed on the substrate between the second doped electrode region and the third doped electrode region. The semiconductor device of claim 4, further comprising: a gate structure on the high cutoff voltage channel region and the dielectric structure. The semiconductor device of claim 5, wherein the gate structure is electrically connected to a voltage source, and when the bias voltage of the voltage source is zero, the semiconductor device provides an output current, the high cutoff voltage channel The higher the ratio of the region covering the second doped electrode region, the larger the output current. The semiconductor device of claim 6, further comprising: a top doped region having the first conductivity type formed in the deep well and located below the dielectric structure. A method of fabricating a semiconductor device, comprising: providing a substrate having a first conductivity type; forming a deep well in the substrate, the deep well extending downward from a surface of the substrate and having a surface opposite to the first conductivity type a second conductivity type; forming a first well in the deep well, the first well extending downward from a surface of the substrate and having at least one of the first conductivity type or the second conductivity type; forming a layer on In the first well, the field layer is extended downward from the surface of the substrate and has the first conductivity type; forming a high cutoff voltage channel region adjacent to the field layer in the first well The high-cut-off voltage channel region is extended downward from the surface of the substrate and has the second conductivity type; forming a first doped electrode region at a position in the first well that does not have the high-off voltage channel region, the first a doped electrode region having the first conductivity type, the first doped electrode region being covered by the field layer; forming a second doped electrode region adjacent to the first doped electrode region, the second doped region having The second conductivity type, a portion of the second doped electrode region is covered by the high off voltage channel region, wherein the semiconductor is determined by adjusting a ratio of the high off voltage channel region covering the second doped electrode region One of the devices outputs current. The method of manufacturing the semiconductor device of claim 8, wherein the surface of the high-cut-off voltage channel region has a first side, a second side, a third side, and a fourth side. The first side edge is opposite to the second side edge, the third side edge is opposite to the fourth side edge, and the first side edge and the second side edge are adjacent to the third side edge and the fourth side edge . The method of fabricating a semiconductor device according to claim 8, wherein the step of forming the high-cut-off voltage channel region is performed by forming the first doped electrode region and forming the second doped region doped electrode region. Before the step. The method of fabricating a semiconductor device according to claim 8, wherein the step of forming the field layer is performed before the step of forming the first doped electrode region and before the step of forming the second doped electrode region. The method for fabricating a semiconductor device according to claim 8 , further comprising: forming a third doped electrode region in the deep well and the second doped Where the polar regions are separated by a distance, the third doped electrode region extends downward from the surface of the substrate and has the second conductivity type. The method of fabricating a semiconductor device according to claim 12, further comprising: forming a dielectric structure between the second doped electrode region and the third doped electrode region on the substrate. The method of fabricating the semiconductor device of claim 13, further comprising: forming a gate structure on the high off voltage channel region and the dielectric structure. The method of fabricating a semiconductor device according to claim 14, wherein the gate structure is electrically connected to a voltage source, and when the bias voltage of the voltage source is zero, the semiconductor device provides the output current. The method of fabricating a semiconductor device according to claim 14, further comprising: forming a top doped region in the deep well and below the dielectric structure, the top doped region having the first conductivity type. A method of operating a semiconductor device, the semiconductor device comprising: a substrate having a first conductivity type; a deep well located in the substrate and having a second conductivity type opposite to the first conductivity type; a first well Locating in the deep well and having at least one of the first conductivity type or the second conductivity type; a first doped electrode region located in the first well and having the first conductivity type; a second doped electrode region having the second conductivity type, located in the first well adjacent to the first doped electrode region; a third doped electrode region having the second conductivity type, the third doping The impurity electrode region is located in the deep well and extends downward from the surface of the substrate and is spaced apart from the second doped electrode region; a high cutoff voltage channel region is located in the first well and has the second conductivity type The high cutoff voltage channel region extends downward from the surface of the substrate and covers a portion of the surface of the second doped electrode region; a field layer having the first conductivity type, the field layer being located at the first And in the well adjacent to the high cutoff voltage channel region, the field layer is extended downward from the surface of the substrate and covers the surface of the first doped electrode region, wherein the surface of the high cutoff voltage channel region has a first side a side, a second side, a third side, and a fourth side, the first side opposite the second side, the third side opposite the fourth side, the first side The semiconductor device is adjacent to the second side and the fourth side of the second side The method includes: applying a bias voltage to the high-cut voltage channel region; coupling the first doped electrode region to a first electrode, the first electrode being one of a cathode and an anode; The third doped electrode region is coupled to a second electrode, and the second electrode is the other of the cathode and the anode. The method of operating a semiconductor device according to claim 17, wherein the semiconductor device provides an output current when the bias voltage is zero.