CN104217950A - Planar VDMOS (vertical double-diffusion metal oxide semiconductor) device and method for manufacturing same - Google Patents
Planar VDMOS (vertical double-diffusion metal oxide semiconductor) device and method for manufacturing same Download PDFInfo
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- CN104217950A CN104217950A CN201310219105.1A CN201310219105A CN104217950A CN 104217950 A CN104217950 A CN 104217950A CN 201310219105 A CN201310219105 A CN 201310219105A CN 104217950 A CN104217950 A CN 104217950A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000009792 diffusion process Methods 0.000 title abstract 2
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000001259 photo etching Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 15
- -1 boron ion Chemical class 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 10
- 238000002347 injection Methods 0.000 description 9
- 239000007924 injection Substances 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/0865—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention discloses a planar VDMOS (vertical double-diffusion metal oxide semiconductor) device and a method for manufacturing the same. The method includes steps of manufacturing a semiconductor substrate, an epitaxial layer and a gate oxide layer; forming two gate regions on the gate oxide layer; forming a doped region inside the epitaxial layer; forming a source region inside the doped region; forming a deep doped region inside the doped region; forming a dielectric layer on the two gate regions and the gate oxide layer; vertically and downwardly etching the middle of the dielectric layer, and sequentially removing the dielectric layer, the gate oxide layer, the source region and the deep doped region by means of etching to form an opening; removing parts of the dielectric layer and parts of the gate oxide layer on the left side and the right side of the opening by means of etching; forming a source metal layer inside the opening and on the dielectric layer. The deep doped region is positioned under the source region. The planar VDMOS device and the method in an embodiment of the invention have the advantages that photoetching operation can be omitted when the source region is manufactured, and accordingly the manufacturing cost of the planar VDMOS device can be reduced.
Description
Technical field
The present invention relates to semiconductor device processing technology field, particularly a kind of plane VDMOS device and manufacture method thereof.
Background technology
In prior art, the manufacture process of plane VDMOS device as shown in Figures 1 to 6, behind formation Semiconductor substrate 101, epitaxial loayer 102, gate oxide 103, two gate regions 104 and doped region 105, form two source areas 106 by photoetching process and ion implantation technology, now photoresist 112 plays the effect that blocks ions is injected, by generating silicon nitride layer 111 and etching silicon nitride layer 111, thus form two side walls 110, in doped region 105, dark doped region 107 is formed by ion implantation technology between two side walls 110, two side walls 110 play the effect of blocks ions injection, thus make the width shared by two source areas 106 be greater than the width of dark doped region 107, the plane VDMOS device finally formed as shown in Figure 6, dielectric layer is wrapped in gate oxide 103, gate regions 104, side wall 110, source metal 109 covers the top of two source areas 106 and dark doped region 107.
In sum, in formation two source areas 106, need first to carry out lithography operations, in addition, in the process manufacturing plane VDMOS device, also need to generate silicon nitride layer 111; The manufacturing process of plane VDMOS device is comparatively complicated.
Summary of the invention
The embodiment of the present invention provides a kind of plane VDMOS device and manufacture method thereof, in order to solve the problem of the plane VDMOS device manufacturing process complexity existed in prior art.
The manufacture method of a kind of plane VDMOS device that the embodiment of the present invention provides comprises the following steps:
Manufacture Semiconductor substrate, epitaxial loayer and gate oxide;
Gate oxide forms two gate regions;
Doped region is formed in epitaxial loayer inside;
Source area is formed in inside, doped region;
The dark doped region be positioned at below source area is formed in inside, described doped region;
Dielectric layer is formed above two gate regions and described gate oxide;
Etch vertically downward from the middle part of dielectric layer, etching removes dielectric layer, gate oxide, source area and dark doped region successively, thus forms opening;
Part dielectric layer and part gate oxide is removed by etching in the left and right sides of opening;
Source metal is formed above the inside and dielectric layer of opening.
A kind of plane VDMOS device that the embodiment of the present invention provides comprises: be positioned at the epitaxial loayer in Semiconductor substrate, be positioned at the doped region of epitaxial loayer inside, be positioned at the source area of inside, doped region and dark doped region, to be positioned at above epitaxial loayer, doped region and source area three and to be positioned at the gate oxide of the left and right sides of epitaxial loayer, be positioned at two gate regions above gate oxide, surround the dielectric layer of two gate regions, be positioned at the source metal of deep dark doped region, above dielectric layer and lower end;
Described dark doped region is positioned at the below of described source area, and the width of described dark doped region is less than the width of described source area;
The width of described source area is greater than the horizontal range between two gate regions.
Beneficial effect of the present invention is as follows: the embodiment of the present invention does not need to carry out lithography operations when manufacturing source area, do not need to manufacture silicon nitride layer simultaneously, reduce the manufacturing cost of plane VDMOS device, any harmful effect is not produced to the electrical property of plane VDMOS device simultaneously.
Accompanying drawing explanation
Fig. 1 is that the source area of prior art midplane VDMOS device forms schematic diagram;
Fig. 2 is that the silicon nitride layer of prior art midplane VDMOS device forms schematic diagram;
Fig. 3 is that the side wall of prior art midplane VDMOS device forms schematic diagram;
Fig. 4 is that the dark doped region of prior art midplane VDMOS device forms schematic diagram;
Fig. 5 is that the dielectric layer of prior art midplane VDMOS device forms schematic diagram;
Fig. 6 is the structural representation of prior art midplane VDMOS device;
Fig. 7 is the flow chart manufacturing plane VDMOS device in the embodiment of the present invention;
Fig. 8 is that the gate oxide of embodiment of the present invention midplane VDMOS device forms schematic diagram;
Fig. 9 is that the gate regions of embodiment of the present invention midplane VDMOS device forms schematic diagram;
Figure 10 is that the doped region of embodiment of the present invention midplane VDMOS device forms schematic diagram;
Figure 11 is that first of the source area of embodiment of the present invention midplane VDMOS device forms schematic diagram;
Figure 12 is that second of the source area of embodiment of the present invention midplane VDMOS device forms schematic diagram;
Figure 13 is that the dark doped region of embodiment of the present invention midplane VDMOS device forms schematic diagram;
Figure 14 is that the dielectric layer of embodiment of the present invention midplane VDMOS device forms schematic diagram;
Figure 15 is the dielectric layer etching schematic diagram of embodiment of the present invention midplane VDMOS device;
Figure 16 is that the opening of embodiment of the present invention midplane VDMOS device forms schematic diagram;
Figure 17 is the enlarged openings upper width schematic diagram of embodiment of the present invention midplane VDMOS device;
Figure 18 is the structural representation of embodiment of the present invention midplane VDMOS device.
Embodiment
The embodiment of the present invention does not need to carry out lithography operations when manufacturing source area, does not need to manufacture silicon nitride layer simultaneously, reduces the manufacturing cost of plane VDMOS device, avoid the problem of plane VDMOS device manufacturing process complexity.
Below in conjunction with accompanying drawing, embodiments of the present invention is further illustrated.
As shown in Figure 7, a kind of manufacture method of plane VDMOS device that the embodiment of the present invention provides comprises the following steps:
Step S1: manufacture Semiconductor substrate;
Step S2: manufacture epitaxial loayer on the semiconductor substrate;
Step S3: form gate oxide on said epitaxial layer there;
Step S4: form two gate regions being positioned at gate oxide both sides on described gate oxide;
Step S5: form doped region in described epitaxial loayer inside, the width of described doped region is greater than the horizontal range between two gate regions;
Step S6: form source area in inside, described doped region, the width of described source area is greater than the horizontal range between two gate regions;
Step S7: form in inside, described doped region the dark doped region be positioned at below source area, the width of dark doped region is less than the width of source area;
Step S8: form dielectric layer above described two gate regions and described gate oxide;
Step S9: etch vertically downward from the middle part of described dielectric layer, etching removes dielectric layer, gate oxide, source area and dark doped region successively, thus forms opening, and the bottom of described opening is positioned at inside, described dark doped region;
Step S10: remove part dielectric layer and part gate oxide by etching in the left and right sides of described opening, now, on the direction of gate oxide upper surface to dielectric layer upper surface, the width of opening expands gradually, and described two gate region are in described dielectric layer;
Step S11: form source metal above the inside of described opening and described dielectric layer.
With reference to figure 7 and Fig. 8, manufacture Semiconductor substrate 201, be illustrated for N type semiconductor substrate in the present embodiment.
When Semiconductor substrate 201 manufacturing epitaxial loayer 202(Semiconductor substrate 201 for N type semiconductor substrate, epitaxial loayer 202 is N-type epitaxy layer);
Epitaxial loayer 202 is formed gate oxide 203, its concrete technology flow process is as follows: in high temperature furnace pipe, utilize the method for dry oxidation to form gate oxide 203, the temperature of carrying out dry oxidation is 800 DEG C ~ 1000 DEG C, and the thickness of the final gate oxide 203 formed is 0.04 μm ~ 0.15 μm.
With reference to figure 7 and Fig. 9, gate oxide 203 forms two gate regions 204 being positioned at gate oxide 203 both sides; Particularly, growing polycrystalline silicon layer in high temperature furnace pipe, polysilicon layer covers the top (not shown) of gate oxide 203, and the thickness of the polysilicon layer of formation is 0.3 μm ~ 0.7 μm, and preferably, the thickness of the polysilicon layer of formation is 0.5 μm; Then manufacturing two gate regions 204 by photoetching process, preferably, when etching polysilicon layer, adopting chlorine or hydrogen bromide to carry out dry etching.
With reference to figure 7 and Figure 10, doped region 205 is formed in epitaxial loayer 202 inside, particularly, when Semiconductor substrate 201 is N type semiconductor substrate, by injecting boron ion in ion implantation technology epitaxial layers 202 between two gate regions 204, formation doped region 205(now doped region 205 is P type doped region), the dosage of injection is 1E13cm
-2, the energy range of injection is 60KeV ~ 120KeV;
In high temperature furnace pipe, carry out boron ion drive in, thus expand the degree of depth and the width of doped region 205, make the width of doped region 205 be greater than horizontal range between two gate regions 204; Carrying out the temperature that boron ion drives in is 1000 DEG C ~ 1200 DEG C, and the time is 90min ~ 240min, and preferably, carrying out the temperature that boron ion drives in is 1150 DEG C, and the time is 180min;
With reference to figure 7 and Figure 11, doped region 205 inside formed source area 206(now source area 206 be N-type source area), particularly, when Semiconductor substrate 201 is N type semiconductor substrate, by injecting phosphonium ion in ion implantation technology epitaxial layers 202 between two gate regions 204, the dosage of injection is 1E15cm
-2, the energy range of injection is 90KeV ~ 120KeV;
With reference to figure 7 and Figure 12, in high temperature furnace pipe, carry out phosphonium ion drive in, thus expand the degree of depth and the width of source area 206, make the width of source area 206 be greater than horizontal range between two gate regions 204; Carrying out the temperature that phosphonium ion drives in is 800 DEG C ~ 1000 DEG C, and the time is 20min ~ 30min, and preferably, carrying out the temperature that phosphonium ion drives in is 900 DEG C, and the time is 25min.As from the foregoing, not needing to carry out lithography operations when manufacturing source area 206, reducing the manufacturing cost of device.
With reference to figure 7 and Figure 13, formed in inside, doped region 205 be positioned at dark doped region 207(below source area 206 now dark doped region 207 be P moldeed depth doped region); Particularly, when Semiconductor substrate 201 is N type semiconductor substrate, between two gate regions 204, inject phosphonium ion by ion implantation technology in doped region 205, the dosage of injection is 1E15cm
-2, the energy range of injection is 90KeV ~ 130KeV; The dark doped region 207 of final formation is positioned at below source area 206, and the width of source area 206 is greater than the width of dark doped region 207, can meet plane VDMOS device electrical property to the requirement of device architecture.
With reference to figure 7 and Figure 14, above two gate regions 204 and gate oxide 203, form dielectric layer 208; Particularly, by chemical vapor deposition (CVD) dielectric layer deposited 208 above two gate regions 204 and gate oxide 203; Preferably, dielectric layer 208 is two layer composite structure, and bottom is plain silicon dioxide layer, and its thickness is 0.2 μm ~ 0.5 μm, and top layer is the silicon dioxide layer of Doping Phosphorus or doped with boron, and its thickness is 0.8 μm ~ 2.0 μm;
With reference to figure 7, Figure 15 and Figure 16, etch vertically downward from the middle part of dielectric layer 208, etching removes dielectric layer 208, gate oxide 203, source area 206 and dark doped region 207 successively, thus forms opening 210; Particularly, adopt dry etch process to remove dielectric layer 208 and gate oxide 203, now, the gas that dry etching uses is fluoroform; Adopt dry etch process to remove source area 206 and dark doped region 207, the gas that now dry etching uses is chlorine or hydrogen bromide.As shown in figure 16, after carrying out dry etching, define opening 210, the bottom of opening 201 is deeply to dark doped region 207.
Preferably, after opening 201 is formed, in dark doped region 207, inject boron ion by ion implantation technology, the dosage of injection is 1E15cm
-2, the energy range of injection is 90KeV ~ 130KeV; By boron ion implantation, further increase the pulse avalanche breakdown energy of plane VDMOS device.
With reference to figure 7 and Figure 17, part dielectric layer 208 and part gate oxide 203 is removed by etching in the left and right sides of described opening 210, now, at gate oxide 203 upper surface on the direction of dielectric layer upper surface 208, the width of opening 210 expands gradually, and described two gate regions 204 are positioned at described dielectric layer 208; The solution that wet etching adopts is hydrofluoric acid cushioning liquid, and the time of carrying out wet etching is 100 seconds to 300 seconds.
With reference to figure 7 and Figure 18, the inside of opening 210 and the top of described dielectric layer 208 form source metal 209; Particularly, adopt sputter coating process, growing metal layer above the inside of opening 210 and described dielectric layer 208, metal level is Al-Si-Cu alloy (mass percent of aluminium copper silicon is respectively 98.5%, 1%, 0.5%), and the thickness of metal level is 1 μm ~ 4 μm; Then, remove partial metal layers by dry etch process, make the upper surface of metal level smooth, thus define source metal 209; The gas that dry etching uses is boron chloride; Now, getting up (source metal 209 is connected source area 206 and dark doped region 207 simultaneously) with dark doped region 207 short circuit in source area 206 by source metal 209, can meet the electrical property needs of plane VDMOS device.
In the manufacture process of above-mentioned plane VDMOS device, there is no the generative process of silicon nitride layer, thus optimize the manufacturing process of device.
The plane VDMOS device of final formation as shown in figure 18, the source electrode of lead-in wire as plane VDMOS device is pulled out from source metal 209, pull out the grid of lead-in wire as plane VDMOS device from two gate regions 204, pull out the drain electrode of lead-in wire as plane VDMOS device from Semiconductor substrate 201.
As shown in figure 18, a kind of plane VDMOS device that the embodiment of the present invention provides comprises: be positioned at the epitaxial loayer 202 in Semiconductor substrate 201, be positioned at the doped region 205 of epitaxial loayer 202 inside, be positioned at source area 206 and the dark doped region 207 of inside, doped region 205, be positioned at epitaxial loayer 202, the gate oxide 203 of the left and right sides of epitaxial loayer 202 is positioned at above doped region 205 and source area 206 three, be positioned at two gate regions 204 above gate oxide 203, surround the dielectric layer 208 of two gate regions 204, be positioned at the source metal 209 of deep dark doped region 207, above dielectric layer 208 and lower end,
Described dark doped region 207 is positioned at the below of described source area 206, and the width of described dark doped region 207 is less than the width of described source area 206;
The width of described source area 206 is greater than the horizontal range between two gate regions 204.
The concrete structure parameter of this plane VDMOS device is illustrated in the manufacture method embodiment of plane VDMOS device, no longer repeats at this.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a manufacture method for plane VDMOS device, is characterized in that, comprises the following steps:
Manufacture Semiconductor substrate, epitaxial loayer and gate oxide;
Gate oxide forms two gate regions;
Doped region is formed in epitaxial loayer inside;
Source area is formed in inside, doped region;
The dark doped region be positioned at below source area is formed in inside, described doped region;
Dielectric layer is formed above two gate regions and described gate oxide;
Etch vertically downward from the middle part of dielectric layer, etching removes dielectric layer, gate oxide, source area and dark doped region successively, thus forms opening;
Part dielectric layer and part gate oxide is removed by etching in the left and right sides of opening;
Source metal is formed above the inside and dielectric layer of opening.
2. the method for claim 1, is characterized in that, manufactures Semiconductor substrate, epitaxial loayer and gate oxide and comprises:
Manufacture Semiconductor substrate;
Form epitaxial loayer on the semiconductor substrate;
Form gate oxide on said epitaxial layer there.
3. the method for claim 1, is characterized in that, described two gate region are in gate oxide both sides.
4. the method for claim 1, is characterized in that, the width of described doped region is greater than the horizontal range between two gate regions.
5. the method for claim 1, is characterized in that, the width of described source area is greater than the horizontal range between two gate regions.
6. the method for claim 1, is characterized in that, the width of described dark doped region is less than the width of source area.
7. the method for claim 1, is characterized in that, the bottom of described opening is positioned at inside, described dark doped region.
8. the method for claim 1, is characterized in that, described two gate region are in described dielectric layer.
9. the method for claim 1, is characterized in that, also comprises: after opening is formed, and injects the first ion from described open bottom to described dark doped region, and the type of described first ion is identical with dark doped region conduction type.
10. a plane VDMOS device, it is characterized in that, comprise: be positioned at the epitaxial loayer in Semiconductor substrate, be positioned at the doped region of epitaxial loayer inside, be positioned at the source area of inside, doped region and dark doped region, be positioned at above epitaxial loayer, doped region and source area three and be positioned at the gate oxide of the left and right sides of epitaxial loayer, being positioned at two gate regions above gate oxide, surround the dielectric layer of two gate regions, be positioned at the source metal of deep dark doped region, above dielectric layer and lower end;
Described dark doped region is positioned at the below of described source area, and the width of described dark doped region is less than the width of described source area;
The width of described source area is greater than the horizontal range between two gate regions.
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| CN201310219105.1A CN104217950A (en) | 2013-06-04 | 2013-06-04 | Planar VDMOS (vertical double-diffusion metal oxide semiconductor) device and method for manufacturing same |
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| CN201310219105.1A CN104217950A (en) | 2013-06-04 | 2013-06-04 | Planar VDMOS (vertical double-diffusion metal oxide semiconductor) device and method for manufacturing same |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298928A (en) * | 2015-06-12 | 2017-01-04 | 北大方正集团有限公司 | VDMOS device and preparation method thereof |
| CN106298532A (en) * | 2015-06-04 | 2017-01-04 | 北大方正集团有限公司 | The manufacture method of plane VDMOS |
| CN110797263A (en) * | 2019-11-14 | 2020-02-14 | 龙腾半导体有限公司 | Power MOSFET device and manufacturing method thereof |
| CN111244182A (en) * | 2020-01-19 | 2020-06-05 | 深圳市昭矽微电子科技有限公司 | Metal oxide semiconductor field effect transistor and manufacturing method thereof |
-
2013
- 2013-06-04 CN CN201310219105.1A patent/CN104217950A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298532A (en) * | 2015-06-04 | 2017-01-04 | 北大方正集团有限公司 | The manufacture method of plane VDMOS |
| CN106298928A (en) * | 2015-06-12 | 2017-01-04 | 北大方正集团有限公司 | VDMOS device and preparation method thereof |
| CN106298928B (en) * | 2015-06-12 | 2019-10-15 | 北大方正集团有限公司 | VDMOS device and preparation method thereof |
| CN110797263A (en) * | 2019-11-14 | 2020-02-14 | 龙腾半导体有限公司 | Power MOSFET device and manufacturing method thereof |
| CN111244182A (en) * | 2020-01-19 | 2020-06-05 | 深圳市昭矽微电子科技有限公司 | Metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN111244182B (en) * | 2020-01-19 | 2023-03-28 | 深圳市昭矽微电子科技有限公司 | Metal oxide semiconductor field effect transistor and manufacturing method thereof |
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