CN106298532A - The manufacture method of plane VDMOS - Google Patents
The manufacture method of plane VDMOS Download PDFInfo
- Publication number
- CN106298532A CN106298532A CN201510303015.XA CN201510303015A CN106298532A CN 106298532 A CN106298532 A CN 106298532A CN 201510303015 A CN201510303015 A CN 201510303015A CN 106298532 A CN106298532 A CN 106298532A
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- China
- Prior art keywords
- gate oxide
- layer
- source region
- polysilicon layer
- ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 43
- 229920005591 polysilicon Polymers 0.000 claims abstract description 41
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 238000002347 injection Methods 0.000 claims abstract description 12
- 239000007924 injection Substances 0.000 claims abstract description 12
- 238000001259 photo etching Methods 0.000 claims abstract description 8
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 claims abstract description 5
- 102000013275 Somatomedins Human genes 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Abstract
The present invention provides the manufacture method of a kind of plane VDMOS, and the method includes: growth gate oxide and polysilicon layer the most successively, and is performed etching described polysilicon layer by photoetching and etching technics, forms body district window；Under the stop of the photoresist on polysilicon layer surface, by etching technics, described gate oxide is performed etching, retain one layer of thin gate oxide, remove photoresist；The injection of perfect aspect district ion and driving in, is formed and is positioned at the body district below described gate oxide；Definition source region, and by the injection of source region ion, form source region, described source region is positioned at the lower section of described polysilicon layer both sides of the edge, is contained in described body district；Somatomedin layer, and form front metal layer on the surface of the component；The metal layer on back of making devices.The manufacture method of the plane VDMOS that the present invention provides, it is possible to avoid, in manufacturing process, polysilicon is caused damage, improve the reliability of device.
Description
Technical field
The present invention relates to semiconductor chip and manufacture field, particularly relate to the making of a kind of plane VDMOS
Method.
Background technology
Planar vertical dmost (VDMOS) has bipolar transistor concurrently
Pipe and the advantage of common MOS device, be widely used in field of switch power.
In traditional plane VDMOS processing technology, the generation thickness of gate oxide is typically 800
Angstrom～1200 angstroms between, after the photoetching and etching technics of polysilicon layer, the loss of gate oxide
Being about 100 angstroms, on the surface of device source region, at least residual thickness is the gate oxide of 700 angstroms.As
Really source region injects ion is arsenic (symbol of element As), then the oxidated layer thickness of 700 angstroms was undoubtedly
Thick, arsenic ion is difficult to penetrate so thick oxide layer and be injected into inside epitaxial layer and go.Therefore, exist
In traditional plane VDMOS technique, need gate oxide is performed etching before source region ion implanting,
Remaining thickness is 200 angstroms～the gate oxide of 300 angstroms, is beneficial to the injection of source region ion.
But, this traditional processing technology, during carrying out gate oxide etching, can damage
To polysilicon layer, make the threshold voltage of device fluctuate, affect the reliability of device.
Summary of the invention
The present invention provides the manufacture method of a kind of plane VDMOS, in order to solve in traditional handicraft, due to
Polysilicon layer is impaired in etching technics, and the device threshold voltage caused fluctuates, and device reliability is not
High problem.
The manufacture method of the plane VDMOS that the present invention provides, including:
Growth gate oxide and polysilicon layer the most successively, and by photoetching and etching technics
Described polysilicon layer is performed etching, forms body district window；
Under the stop of the photoresist on polysilicon layer surface, by etching technics, to described gate oxide
Perform etching, retain one layer of thin gate oxide, remove photoresist；
The injection of perfect aspect district ion and driving in, is formed and is positioned at the body district below described gate oxide；
Definition source region, and by the injection of source region ion, form source region, described source region is positioned at described polycrystalline
The lower section of silicon layer both sides of the edge, is contained in described body district；
Somatomedin layer, and form front metal layer on the surface of the component；
The metal layer on back of making devices.
The manufacture method of the plane VDMOS that the present invention provides, by putting the etching technics of gate oxide
Put after polysilicon layer etching technics, i.e. polysilicon layer is being performed etching, after forming body district window,
I.e. gate oxide is performed etching, form the thin gate oxide being suitable to body district ion implanting, then by body district
With the making that the processing technology of source region and other follow-up technique complete device.Avoid at gate oxide
The damage of the unrepairable in etching process, polysilicon layer caused, and owing to polysilicon layer damages, lead
The problem that the device threshold voltage caused is unstable, thus improve the reliability of device.
Accompanying drawing explanation
The schematic flow sheet of the plane VDMOS manufacture method that Fig. 1 provides for one embodiment of the invention；
Fig. 2 is the implementation schematic flow sheet of step 101 in Fig. 1；
Fig. 3 is the device architecture schematic diagram in execution Fig. 1 after step 101；
Fig. 4 is the device architecture schematic diagram in execution Fig. 1 after step 102；
Fig. 5 is the device architecture schematic diagram in execution Fig. 1 after step 103；
Fig. 6 is the device architecture schematic diagram in execution Fig. 1 after step 104；
Fig. 7 is the implementation schematic flow sheet of step 105 in Fig. 1；
Fig. 8 is the device architecture schematic diagram in execution Fig. 1 after step 106.
Reference:
1-N type dense substrate 2-N type epitaxial layer 3-gate oxide
4-polysilicon layer 5-body district 6-source region
7-photoresist 8-dielectric layer 9-front metal layer
10-metal layer on back 11-body district window
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with this
Accompanying drawing in bright embodiment, is clearly and completely described the technical scheme in the embodiment of the present invention,
Obviously, described embodiment is a part of embodiment of the present invention rather than whole embodiments.Based on
Embodiment in the present invention, those of ordinary skill in the art are obtained under not making creative work premise
The every other embodiment obtained, broadly falls into the scope of protection of the invention.
Succinct in order to describe, it will be apparent to those skilled in the art that following example are by the core to the present invention
Technical scheme is described, and every part relating to existing technique will not illustrate.
The schematic flow sheet of the plane VDMOS manufacture method that Fig. 1 provides for one embodiment of the invention, as
Shown in Fig. 1, the plane VDMOS manufacture method that the present embodiment provides includes:
Step 101, the most successively growth gate oxide 3 and polysilicon layer 4, and pass through light
Carve and described polysilicon layer 4 is performed etching by etching technics, form body district window 11；
Concrete, Fig. 2 is the implementation schematic flow sheet of step 101 in Fig. 1, as in figure 2 it is shown,
Step 101 can be accomplished by:
Step 1011, on the surface of the substrate growth gate oxide 3；
Concrete, growing a layer thickness on the surface of the substrate by gate oxide processing technology is 800
Angstrom～the gate oxide 3 of 1200 angstroms, wherein, it is preferred that described substrate can be to comprise the dense substrate of N-type
1 and the substrate of N-type epitaxy layer 2.Described growth gate oxide 3 on the surface of the substrate, is in substrate
N-type epitaxy layer 2 on carry out the growth of gate oxide.
Step 1012, on the surface of described gate oxide 3 growing polycrystalline silicon layer 4；
Step 1013, respectively two on described polysilicon layer 4 surface from region on be coated with photoetching
Glue 7, and under the stop of described photoresist 7, described polysilicon layer 4 is performed etching, until exposing
Till described gate oxide 3, forming body district window 11 as shown in Figure 3, Fig. 3 is for performing to walk in Fig. 1
Device architecture schematic diagram after rapid 101.
Step 102, photoresist 7 on polysilicon layer surface stop under, by etching technics, right
Described gate oxide 3 performs etching, and retains one layer of thin gate oxide, removes photoresist 7；
Preferably, under the stop of photoresist 7, by dry etch process, gate oxide 3 is carved
Erosion, remaining thickness is 200 angstroms～the gate oxide of 300 angstroms, and removes photoresist 7, is formed such as Fig. 4 institute
The device architecture shown, Fig. 4 is the device architecture schematic diagram in execution Fig. 1 after step 102.
In this step, owing to being coated with photoresist 7 on the surface of polysilicon layer, therefore, dry in employing
When gate oxide is performed etching by method etching technics, the upper surface of polysilicon layer 4 is in the protection of photoresist 7
Under will not sustain damage, and the both sides of polysilicon layer are not owing to being protected by photoresist, it will be subject to
To damage.
Step 103, the injection of perfect aspect district ion and drive in, formed and be positioned at below described gate oxide 3
Body district 5；
Concrete, under the stop of polysilicon layer 4, using p-type ion as place, ion pair body district of body district
Region carry out ion implanting and driving in, wherein, it is preferred that described p-type ion can be boron ion,
I.e. with boron ion for body district ion, and it is 1.0 × 10 at implantation dosage13～1.0 × 1015Individual/cm2, inject energy
Under conditions of amount is for 60KEV～100KEV, the region at place, body district is carried out ion implanting, and is driving in
Temperature is 900～1200 degree, and the time of driving in is to drive in boron ion under conditions of 50～200min,
Forming body district 5 as shown in Figure 5, Fig. 5 is the device architecture schematic diagram in execution Fig. 1 after step 103.
Here it should be understood that owing to the thickness of the most remaining gate oxide only has 200
Angstrom～300 angstroms, therefore, when carrying out body district ion implanting, only need to be less 20KEV～40KEV than traditional handicraft
Implantation Energy, i.e. can reach the injection degree of depth identical with traditional handicraft.
Here it may also be noticed that: the present embodiment is carrying out while body district ion drives in, in addition it is also necessary to logical
Entering nitrogen and oxygen, wherein, the flow of nitrogen is preferred with 8～12 liters per minute, and the flow of oxygen is with often
Minute 0.04～0.2 liter is preferred.
In this step, can occur with the oxygen being passed through due to the silicon atom of polysilicon layer both sides undamaged portion
Reaction generates silicon dioxide, and therefore, the undamaged portion of polysilicon layer can be repaired in this step.
Step 104, definition source region, and by the injection of source region ion, form source region 6, described source region 6
It is positioned at the lower section of described polysilicon layer both sides of the edge, is contained in described body district 5；
Concrete, step 104 can be accomplished in that
By coating photoresist on the surface of gate oxide 3, and in photoresist and the resistance of polysilicon layer 4
Carry out source region ion implanting under gear, form source region 6 as shown in Figure 6, and remove photoresist.Wherein,
Fig. 6 is the device architecture schematic diagram in execution Fig. 1 after step 104.
Further, source region ion is preferably arsenic ion, and the implantation dosage of arsenic ion is preferably 1.0 × 1015~
1.0×1016Individual/cm2, Implantation Energy is preferably 50KEV～120KEV.
Step 105, somatomedin layer 8, and form front metal layer 9 on the surface of the component；
Concrete, as it is shown in fig. 7, step 105 can be accomplished by:
Step 1051, being formed on the surface of the component by the way of deposit, apparent height is higher than described many
The dielectric layer 8 of crystal silicon layer apparent height；
Step 1052, the dielectric layer in described body district window 11 is performed etching, until exposing described base
Till the surface at the end, forming contact hole, the width of described contact hole is less than the width of described body district window 11；
Step 1053, being formed on the surface of the component by the way of deposit, apparent height is higher than being given an account of
The metal level 9 of matter layer apparent height, wherein, it is preferred that described metal level 9 is Al-Si-Cu alloy.
Here it should be understood that being formed after metal level 9, photoetching to be passed through and the side of etching
Method, performs etching metal level 9, forms pressure welding point, and this does not maps similarly to the prior art
Illustrate and release.
Step 106, the metal layer on back 10 of making devices.
Concrete, the concrete processing technology of step 106 similarly to the prior art, here repeats no more.
The device architecture formed after step 106 is as shown in Figure 8.
The manufacture method of the plane VDMOS that the present embodiment provides, by by the etching technics of gate oxide
After being placed on polysilicon layer etching technics, i.e. polysilicon layer is being performed etching, formed body district window it
After, i.e. gate oxide is performed etching, form the thin gate oxide being suitable to body district ion implanting, then pass through
Body district and the processing technology of source region and other follow-up technique complete the making of device.Avoid at grid oxygen
Change the damage of the unrepairable in layer etching process, polysilicon layer caused, and owing to polysilicon layer damages,
The problem that the device threshold voltage caused is unstable, thus improve the reliability of device.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than right
It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common
Skilled artisans appreciate that the technical scheme described in foregoing embodiments still can be modified by it,
Or the most some or all of technical characteristic is carried out equivalent；And these amendments or replacement, and
The essence not making appropriate technical solution departs from the scope of various embodiments of the present invention technical scheme.
Claims (7)
1. the manufacture method of a plane VDMOS, it is characterised in that including:
Growth gate oxide and polysilicon layer the most successively, and by photoetching and etching technics
Described polysilicon layer is performed etching, forms body district window；
Under the stop of the photoresist on polysilicon layer surface, by etching technics, to described gate oxide
Perform etching, retain one layer of thin gate oxide, remove photoresist；
The injection of perfect aspect district ion and driving in, is formed and is positioned at the body district below described gate oxide；
Definition source region, and by the injection of source region ion, form source region, described source region is positioned at described polycrystalline
The lower section of silicon layer both sides of the edge, is contained in described body district；
Somatomedin layer, and form front metal layer on the surface of the component；
The metal layer on back of making devices.
The manufacture method of plane VDMOS the most according to claim 1, it is characterised in that at base
Grow gate oxide and polysilicon layer on the surface at the end successively, and pass through photoetching and etching technics to described many
Crystal silicon layer performs etching, and forms body district window, including:
The surface of described substrate grows gate oxide；
Growing polycrystalline silicon layer on the surface of described gate oxide；
Respectively two on described polysilicon layer surface from region on coating photoresist, and described
Under the stop of photoresist, described polysilicon layer is performed etching, till exposing described gate oxide,
Form described body district window.
The manufacture method of plane VDMOS the most according to claim 1, it is characterised in that described
By etching technics, described gate oxide is performed etching, including:
Use dry etch process, described gate oxide is performed etching.
The manufacture method of plane VDMOS the most according to claim 1, it is characterised in that described
Body district ion is boron ion, and the implantation dosage of described boron ion is 1.0 × 1013～1.0 × 1015Individual/cm2,
Energy is 60KEV～100KEV.
The manufacture method of plane VDMOS the most according to claim 1, it is characterised in that entering
While row described body district ion drives in, be passed through nitrogen and oxygen, wherein, be passed through the flow of nitrogen be 8～
12 liters/min, the flow being passed through oxygen is 0.04～0.2 liter/min.
The manufacture method of plane VDMOS the most according to claim 1, it is characterised in that described
Definition source region, and by the injection of source region ion, form source region, including:
The region at described source region place is determined by photoetching process, and in photoresist and the stop of polysilicon layer
Under, complete the injection of arsenic ion, form described source region, remove photoresist；
Wherein, the implantation dosage of described arsenic ion is 1.0 × 1015～1.0 × 1016Individual/cm2, energy is
50KEV～120KEV.
The manufacture method of plane VDMOS the most according to claim 1, it is characterised in that described
Somatomedin layer, and form front metal layer on the surface of the component, including:
Dielectric layer deposited on the surface of the component, the apparent height of described dielectric layer is higher than described polysilicon layer
Apparent height；
Dielectric layer in described body district window is performed etching, till exposing the surface of described substrate,
Forming contact hole, the width of described contact hole is less than the width of described body district window；
Growing metal level on the surface of the component, the apparent height of described metal level is higher than described dielectric layer
Apparent height.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510303015.XA CN106298532A (en) | 2015-06-04 | 2015-06-04 | The manufacture method of plane VDMOS |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510303015.XA CN106298532A (en) | 2015-06-04 | 2015-06-04 | The manufacture method of plane VDMOS |
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| CN201510303015.XA Pending CN106298532A (en) | 2015-06-04 | 2015-06-04 | The manufacture method of plane VDMOS |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113327845A (en) * | 2020-02-28 | 2021-08-31 | 上海先进半导体制造有限公司 | Transistor and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060115948A1 (en) * | 2004-11-26 | 2006-06-01 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
| CN104103503A (en) * | 2013-04-02 | 2014-10-15 | 无锡华润上华科技有限公司 | Formation method of semiconductor device gate oxide layer |
| CN104217950A (en) * | 2013-06-04 | 2014-12-17 | 北大方正集团有限公司 | Planar VDMOS (vertical double-diffusion metal oxide semiconductor) device and method for manufacturing same |
-
2015
- 2015-06-04 CN CN201510303015.XA patent/CN106298532A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060115948A1 (en) * | 2004-11-26 | 2006-06-01 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
| CN104103503A (en) * | 2013-04-02 | 2014-10-15 | 无锡华润上华科技有限公司 | Formation method of semiconductor device gate oxide layer |
| CN104217950A (en) * | 2013-06-04 | 2014-12-17 | 北大方正集团有限公司 | Planar VDMOS (vertical double-diffusion metal oxide semiconductor) device and method for manufacturing same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113327845A (en) * | 2020-02-28 | 2021-08-31 | 上海先进半导体制造有限公司 | Transistor and manufacturing method thereof |
| CN113327845B (en) * | 2020-02-28 | 2024-02-13 | 上海积塔半导体有限公司 | Transistor and manufacturing method thereof |
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Application publication date: 20170104 |