CN102142459A - Coolmos structure - Google Patents
Coolmos structure Download PDFInfo
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- CN102142459A CN102142459A CN 201010607814 CN201010607814A CN102142459A CN 102142459 A CN102142459 A CN 102142459A CN 201010607814 CN201010607814 CN 201010607814 CN 201010607814 A CN201010607814 A CN 201010607814A CN 102142459 A CN102142459 A CN 102142459A
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- 238000000034 method Methods 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 5
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 5
- 230000001105 regulatory effect Effects 0.000 claims abstract 2
- 238000009792 diffusion process Methods 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- General Physics & Mathematics (AREA)
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Abstract
The invention discloses a Cool metal oxide semiconductor (MOS) structure, which is used for increasing a breakdown voltage. The structure is used for manufacturing a CoolMOS. A drift region and a situation showing a dosage concentration of the drift region are involved. The situation showing the dosage concentration of the drift region is marked by a virtual line. The method comprises a step of manufacturing the drift region, and a step of regulating the dosage concentration of the drift region during manufacturing of the drift region so that the aim of increasing the breakdown voltage can be fulfilled. On the basis of the method, a new method is provided for increasing the breakdown voltage of a vertical double-diffused (VD) MOS under the condition of not adding a mask plate and not increasing the manufacturing cost.
Description
Technical field
A kind of CoolMOS structure belongs to the semiconductor power device technology field, relates in particular to longitudinal double diffusion metal oxide semiconductor field-effect tube structure and manufacture method thereof.
Background technology
Double diffusion technique oxide semiconductor field effect pipe (DMOS, Double-diffused MOSFET) device is the power device of using always, comprise lateral double diffusion metal oxide semiconductor field effect transistor (LDMOS, Lateral Double-diffused MOSFET) and vertical double-diffusion metal-oxide-semiconductor field effect transistor (VDMOS, Vertical Double-diffused MOSFET).Puncture voltage is to weigh the important parameter of DMOS device performance, and the meaning of its ordinary representation is under the not breakdown situation of guaranty period, and the DMOS source electrode is with the maximum voltage that can apply between the drain electrode.
The VDMOS device is in the low pressure applications field, can obtain comparatively ideal conducting resistance and switching characteristic, but continuous rising along with voltage, conducting resistance mainly is that the resistance by the high resistant epitaxial loayer decides, and constantly increase along with 2.4～2.6 powers of drain-source breakdown voltage, be a constantly direction of development of VDMOS device so will make high withstand voltage VDMOS device obtain lower conduction loss always.
Traditional VDMOS device architecture schematic diagram, as shown in Figure 1, wherein, the 11st, polysilicon gate, the 12nd, spacer medium, the 13rd, source metal, the 14th, N
+Source region, the 15th, P type base, the 16th, N
-Drift region, the 17th, N
+Substrate, the 18th, drain metal.What wherein polysilicon gate 11 adopted is planar gate structure, electric current is when flowing to the raceway groove parallel with the surface, a technotron (JFET) that is fenced up by P type base 15 below the grid 11 is the only way which must be passed of electric current, it becomes the existence of a series resistance on the current channel, makes traditional VDMOS device be difficult to obtain lower conduction loss.
For more effective raising puncture voltage, the device of a kind of CoolMOS of being called has been proposed again, its structure as shown in Figure 2, wherein, the 21st, polysilicon gate, the 22nd, spacer medium, the 23rd, source metal, the 24th, N
+Source region, the 25th, P type base, the 26th, N post, the 27th, N
+Substrate, the 28th, drain metal, the 29th, P post.It adopts the P post 29 of interleaved and the form of N post 26, effectively utilizes land productivity electric charge compensation principle, and when device was in the forward inactive state, electric field was also decayed not only in vertical direction in the horizontal direction, thereby obtained thinner N
-The N type of drift region or higher concentration mixes, and conduction voltage drop has reduced by 5 times more with respect to traditional VDMOS structure.The CoolMOS structure is to adopt repeatedly the deposit epitaxial loayer and repeatedly inject P post 29 and a kind of structure of formation, but along with the increase of BV, the deposit number of times of epitaxial loayer also can correspondingly increase thereupon, this has just increased cost greatly, makes that also conducting resistance increases gradually.
Summary of the invention
The invention provides a kind of CoolMOS structure and manufacture method thereof, to improve the puncture voltage of this CoolMOS structure.
The invention provides a kind of CoolMOS structure, comprise the manufacture method of drift region and the distribution situation of drift region doping content.
The invention provides a kind of CoolMOS structure, do not need to increase any mask plate when making this CoolMOS device.
Regulate the resistance of this epitaxial loayer when optionally, described drift region concentration adjustment is each deposit epitaxial loayer.
Optionally, the concentration of described drift region is not changeless, but linear change.
Optionally, described device architecture is the CoolMOS structure.
Optionally, described CoolMOS structure is the VDMOS structure.
The embodiment of the invention provides CoolMOS structure making process, and this CoolMOS structure comprises the drift region, comprises the manufacture method of drift region and the distribution situation of drift region doping content.The drift region of this CoolMOS structure repeatedly deposit epitaxial loayer obtains, and regulates the resistance of epitaxial loayer and can realize described CoolMOS structure in the deposit epitaxial loayer.Wherein the concentration of drift region is linear change, and the linearity of this concentration is used for improving puncture voltage.Realize that this structure does not need to increase any extra mask plate.
Description of drawings
Fig. 1 is traditional VDMOS device architecture schematic diagram;
Fig. 2 is a CoolMOS device architecture schematic diagram;
Fig. 3 is the CoolMOS device architecture of a kind of effective raising puncture voltage provided by the invention;
Fig. 4 is that vertical doping content of epitaxial loayer drift region distributes;
Fig. 5 is the Electric Field Distribution of extension sheaf space charged region in the device architecture.
Embodiment
Traditional CoolMOS structure is to put forward on the basis of VDMOS device, main being repeatedly the deposit epitaxial loayer and repeatedly injecting the P post and a kind of structure of forming of adopting, and the concentration of each deposit epitaxial loayer is the same in this structure.This method effectively utilizes the charge compensation principle, and when device was in the forward inactive state, electric field was also decayed not only in vertical direction in the horizontal direction, thereby obtained thinner N
-The N type of drift region or higher concentration mixes, and conduction voltage drop has reduced by 5 times more with respect to traditional VDMOS structure.But along with the increase of puncture voltage BV, the deposit number of times of epitaxial loayer also can correspondingly increase thereupon, and this has just increased cost greatly, makes that also conducting resistance increases gradually.Under the situation that does not increase epitaxial loayer deposit number of times, in order to improve puncture voltage BV, we adopt the method for epitaxial layer concentration linear change to improve puncture voltage.
Fig. 3 is a N type CoolMOS cross-sectional structure schematic diagram in the first embodiment of the invention.Wherein, the 31st, polysilicon gate, the 32nd, spacer medium, the 33rd, source metal, the 34th, N
+Source region, the 35th, P type base, the 36th, N post, the 37th, N
+Substrate, the 38th, drain metal, the 39th, P post.
This CoolMOS device is the same with the manufacturing step of traditional CoolMOS device, and that all adopts is repeatedly deposit epitaxial loayer 36 and repeatedly injects P post 39 and form the drift region.But different is, need regulate the doping content (or resistance) of each deposit epitaxial loayer in deposit epitaxial loayer 36, makes the doping content of epitaxial loayer of this step deposit less than the doping content of the rapid deposit epitaxial loayer of previous step, as shown in Figure 4.In forming last CoolMOS device architecture, the concentration of epitaxial loayer forms an approximately linear and distributes from the source end to drain terminal, thereby reaches the purpose that improves puncture voltage.
If traditional C oolMOS structure epitaxial loayer deposit concentration is N, deposition thickness is L, the epitaxial loayer deposit concentration of this CoolMOS structure is N1, N2, N3 ... Nm, corresponding deposition thickness is L1, L2, L3 ... Lm, require L=L1+L2+L3+ ... + Lm, this method is to wish that bigger change does not take place drift zone resistance, under the situation that does not increase conducting resistance, can better improve puncture voltage BV like this.
The manufacture method of this CoolMOS structure is the same with the manufacturing step of traditional CoolMOS structure, just in the deposit epitaxial loayer its doping content (or resistance) is carried out certain adjusting, therefore, does not increase any mask plate.
Fig. 5 is the Electric Field Distribution of epitaxial loayer space charge region of this CoolMOS structure and the Electric Field Distribution of traditional C oolMOS structure.The slope of electric field is represented the doping content size of epitaxial loayer.As can be seen from the figure, the puncture voltage of the device architecture after the invention obviously puncture voltage than traditional C oolMOS structure is big, and dash area is exactly increase that part of among the figure.
The embodiment of the invention has mainly proposed this CoolMOS structure making process, and this CoolMOS structure comprises the drift region, comprises the manufacture method of drift region and the distribution situation of drift region doping content.The drift region of this CoolMOS structure repeatedly deposit epitaxial loayer obtains, and regulates the resistance of epitaxial loayer and can realize described CoolMOS structure in the deposit epitaxial loayer.Wherein the concentration of drift region is linear change, and the linearity of this concentration is used for improving puncture voltage.Realize that this structure does not need to increase any extra mask plate.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (9)
1. CoolMOS structure comprises the distribution situation of doping content in drift region and the drift region, and the drift region is obtained by deposit epitaxial loayer repeatedly, it is characterized in that regulating in the deposit epitaxial loayer resistance of epitaxial loayer.
2. CoolMOS structure as claimed in claim 1 is characterized in that the ladder of this drift region concentration is used for improving puncture voltage.
3. CoolMOS structure as claimed in claim 1 is characterized in that, described drift region repeatedly deposit epitaxial loayer obtains.
4. CoolMOS structure as claimed in claim 2 is characterized in that, regulates the resistance of this epitaxial loayer in each deposit epitaxial loayer.
5. CoolMOS structure as claimed in claim 3 is characterized in that the concentration of described drift region is linear change.
6. CoolMOS structure as claimed in claim 3 is characterized in that, the manufacture method of the drift region of CoolMOS device does not need to increase any mask plate.
7. CoolMOS structure as claimed in claim 1 is characterized in that, described CoolMOS structure is a double-diffusion metal oxide semiconductor field effect tube structure.
8. CoolMOS structure as claimed in claim 1 is characterized in that, described CoolMOS structure is the longitudinal double diffusion metal oxide semiconductor field-effect tube structure.
9. CoolMOS structure as claimed in claim 1 is characterized in that, described CoolMOS is realized by BCD technology.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010607814 CN102142459A (en) | 2010-12-23 | 2010-12-23 | Coolmos structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010607814 CN102142459A (en) | 2010-12-23 | 2010-12-23 | Coolmos structure |
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| CN102142459A true CN102142459A (en) | 2011-08-03 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956448A (en) * | 2011-08-11 | 2013-03-06 | 英飞凌科技奥地利有限公司 | Method for manufacturing semiconductor device e.g. mosfet, involves removing semiconductor body from side up to range defined by foreign substances or pn junction, where pn junction is defined by foreign substances |
| CN105489500A (en) * | 2015-12-30 | 2016-04-13 | 西安龙腾新能源科技发展有限公司 | Preparation method for super-junction VDMOS and super-junction VDMOS device |
| CN107482060A (en) * | 2016-06-08 | 2017-12-15 | 深圳尚阳通科技有限公司 | Superjunction devices and its manufacture method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10108046A1 (en) * | 2001-02-20 | 2002-09-12 | Infineon Technologies Ag | Semiconductor device e.g. compensation FET has compensation regions connected to active zone via resistance |
| CN101383287A (en) * | 2008-09-27 | 2009-03-11 | 电子科技大学 | Manufacturing method for vertical DMOS device |
| CN101515547A (en) * | 2008-02-20 | 2009-08-26 | 中国科学院微电子研究所 | Method for preparing super-junction VDMOS device |
| CN101752252A (en) * | 2008-12-16 | 2010-06-23 | 上海华虹Nec电子有限公司 | Forming method of longitudinal P-shaped district in CoolMOS structure |
-
2010
- 2010-12-23 CN CN 201010607814 patent/CN102142459A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10108046A1 (en) * | 2001-02-20 | 2002-09-12 | Infineon Technologies Ag | Semiconductor device e.g. compensation FET has compensation regions connected to active zone via resistance |
| CN101515547A (en) * | 2008-02-20 | 2009-08-26 | 中国科学院微电子研究所 | Method for preparing super-junction VDMOS device |
| CN101383287A (en) * | 2008-09-27 | 2009-03-11 | 电子科技大学 | Manufacturing method for vertical DMOS device |
| CN101752252A (en) * | 2008-12-16 | 2010-06-23 | 上海华虹Nec电子有限公司 | Forming method of longitudinal P-shaped district in CoolMOS structure |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956448A (en) * | 2011-08-11 | 2013-03-06 | 英飞凌科技奥地利有限公司 | Method for manufacturing semiconductor device e.g. mosfet, involves removing semiconductor body from side up to range defined by foreign substances or pn junction, where pn junction is defined by foreign substances |
| US9613804B2 (en) | 2011-08-11 | 2017-04-04 | Infineon Technologies Austria Ag | Method of manufacturing semiconductor devices which allows reproducible thinning of a semiconductor body of the semiconductor devices |
| CN105489500A (en) * | 2015-12-30 | 2016-04-13 | 西安龙腾新能源科技发展有限公司 | Preparation method for super-junction VDMOS and super-junction VDMOS device |
| CN105489500B (en) * | 2015-12-30 | 2018-08-07 | 西安龙腾新能源科技发展有限公司 | The preparation method and its hyperconjugation VDMOS device of hyperconjugation VDMOS |
| CN107482060A (en) * | 2016-06-08 | 2017-12-15 | 深圳尚阳通科技有限公司 | Superjunction devices and its manufacture method |
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Application publication date: 20110803 |