CN101752252A - Forming method of longitudinal P-shaped district in CoolMOS structure - Google Patents
Forming method of longitudinal P-shaped district in CoolMOS structure Download PDFInfo
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- CN101752252A CN101752252A CN 200810044107 CN200810044107A CN101752252A CN 101752252 A CN101752252 A CN 101752252A CN 200810044107 CN200810044107 CN 200810044107 CN 200810044107 A CN200810044107 A CN 200810044107A CN 101752252 A CN101752252 A CN 101752252A
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000005516 engineering process Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 10
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 66
- 235000012239 silicon dioxide Nutrition 0.000 claims description 33
- 239000000377 silicon dioxide Substances 0.000 claims description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000000407 epitaxy Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 230000014759 maintenance of location Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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Abstract
The invention discloses a forming method of a longitudinal P-shaped district in a CoolMOS structure. The longitudinal P-shaped district of the CoolMPS is formed by the steps of: opening a deep groove on a N-shaped extension, then growing P-shaped monocrystalline silicon inside the groove to form a P-shaped area on the N-shaped extension by using an extension technology, and then etching the P-shaped extension monocrystal growing in the groove to be parallel and level with the surface of the groove by using an etchback technology. The method reduces the complexity and the processing time of the technology.
Description
Technical field
The present invention relates to a kind of method of manufacturing technology of semiconductor integrated circuit, be specifically related to the manufacture method of a kind of CoolMOS (a kind of high-pressure MOS field-effect transistor), relate in particular to the formation method in longitudinal P type district in a kind of CoolMOS structure.
Background technology
CoolMOS is a kind of novel high-voltage MOSFET (MOS field-effect transistor) structure, and its advantage is that this device can provide the conducting resistance than the little order of magnitude of conventional high-tension MOSFET in high pressure resistant work.
The feature structure of CoolMOS is to be to have introduced in N type epitaxial region a lot of p type island region territories that sink to the bottom the district that extend to from the extension top, cause metal-oxide-semiconductor under the high-pressure work state except producing longitudinally from the electric field of drain-to-source, also have because the transverse electric field of horizontal PN district appearance.Cause the even distribution of electric field on horizontal and vertical in different directions under the acting in conjunction of electric field, make high withstand voltage metal-oxide-semiconductor on the low-resistivity epitaxial wafer thereby be implemented in.
P type island region on the N type extension of CoolMOS be formed with several different methods, usual way is to adopt the method for repeatedly diffusion to realize in epitaxial process, comprises following processing step:
Step 1 as shown in Figure 1, after the epitaxial growth, defines the P district by photoresist, carries out P type implantation annealing then;
Step 2, as shown in Figure 2, epitaxial growth again defines the P district by photoresist, carries out P type implantation annealing then;
Step 3 as shown in Figure 3, repeatedly repeats above-mentioned steps and reaches required epitaxial thickness, finishes the formation in longitudinal P district simultaneously.
Step 4, as shown in Figure 4, the growth of grid silicon dioxide film, grid polycrystalline silicon (polycrystalline grid) is grown, and body injects and forms the tagma, and formation CoolMOS such as forming the source region is injected in the source.
CoolMOS is as a kind of novel high-pressure device, and by means of the low on-resistance that its special construction brings, low-power consumption and the advantage of low switch time have very big competitive advantage in the high-voltage applications field.But the processing mode of aforesaid traditional repeatedly extension, photoetching, injection makes process complications, has limited the processing cost and the campaign of product.
Summary of the invention
The technical problem to be solved in the present invention provides the formation method in longitudinal P type district in a kind of CoolMOS structure, and this method has reduced the complexity and the process time of technology.
For solving the problems of the technologies described above, the invention provides the formation method in longitudinal P type district in a kind of CoolMOS structure, comprise the steps:
(1) property growth N type extension once on silicon substrate;
(2) growth layer of silicon dioxide film on N type extension is selected on N type extension then and is wanted the portion in growing P-type district to separate deep trench;
(3) under the state of retention surface silicon dioxide film, utilize epitaxy method growing P-type epitaxial silicon in order to fill deep trench;
(4) epitaxial silicon of using back carving technology to remove to go out in the silicon dioxide film superficial growth, and the P type extension in the deep trench etched near N type epitaxial surface;
(5) remove silicon dioxide film, expose epitaxial surface, growth grid silicon dioxide film on extension, the grid polycrystalline silicon of growing on the grid silicon dioxide film, body inject and form the tagma, and the source is injected and is formed the source region, finally forms the longitudinal P type district epitaxial structure of CoolMOS.
Step (3) utilizes epitaxy method growing P-type epitaxial silicon in order to fill deep trench, at the inner p type single crystal silicon that forms of deep trench.
Step (4) utilizes silicon dioxide film as etching stop layer, and P type extension is returned quarter, removes the P type epitaxial silicon that goes out in the silicon dioxide film superficial growth, and the P type extension of control trench area is etched near N type epitaxial surface, guarantees the smooth of silicon chip surface.
Step (5) adopts wet etching to remove silicon dioxide film.
Compare with prior art, the present invention has following beneficial effect: compare traditional repeatedly epitaxial growth, and photoetching, the method for injection, the present invention has reduced the complexity and the process time of technology.The present invention can carry out the formation in p type island region territory on the good basis of the disposable growth of extension, simplified the repeatedly extension of existing process application, photoetching, the technical process of injection.The present invention proposes under the situation that keeps the flute surfaces silicon dioxide film growing epitaxial in groove, only can reach in the inner effect that forms the selective growth extension of monocrystalline silicon of groove, can also make things convenient for processes as next step time carving technology mask.Utilize method proposed by the invention can significantly reduce restriction in production and processing, further improve competitiveness of product.
Description of drawings
Fig. 1 is a transistorized structural representation after the step 1 of prior art is finished;
Fig. 2 is a transistorized structural representation after the step 2 of prior art is finished;
Fig. 3 is a transistorized structural representation after the step 3 of prior art is finished;
Fig. 4 is a transistorized structural representation after the step 4 of prior art is finished;
Fig. 5 is a transistorized structural representation after step 1 of the present invention is finished;
Fig. 6 is a transistorized structural representation after step 2 of the present invention is finished;
Fig. 7 is a transistorized structural representation after step 3 of the present invention is finished;
Fig. 8 is a transistorized structural representation after step 4 of the present invention is finished;
Fig. 9 is a transistorized structural representation after step 5 of the present invention is finished.
Embodiment
The present invention is further detailed explanation below in conjunction with drawings and Examples.
The present invention proposes and a kind ofly on EPI (extension), open deep trench, and then utilize epitaxy technique in groove, to grow p type single crystal silicon to be formed on p type island region territory on the N extension, then by return carving technology the P type epitaxy single-crystal of growing in the groove is etched into concordant with flute surfaces, to form the longitudinal P type zone of CoolMOS.
The present invention forms the longitudinal P district of CoolMOS, the main technique step of employing following (with reference to figure 2) by the mode of selective epitaxial add-back carving technology:
Step 1. as shown in Figure 5, direct disposable growth N type extension on silicon substrate, it is fixed that epitaxial thickness requires according to device application;
Step 2. as shown in Figure 6; after the epitaxial growth of N type; regrowth layer of silicon dioxide film on the epitaxial region; surface protection film and later step 4 etching stop layer that return carving technology mentioned of this silicon dioxide film during as the etching deep trench set the etching speed of silicon dioxide and the ratio of extension etching speed when gash depth that the selection of silicon dioxide film thickness is processed as required and groove processing.For example processing the deep trench of the 20um degree of depth, is 20: 1 condition adopting the extension etching speed to silicon dioxide etching speed ratio, and the above silicon dioxide film of 1um is adopted in suggestion.The selected part that needs the growing P-type district on N type epitaxial region is opened deep trench on this part then, and the degree of depth and the width of the p type island region that needs in the deep trench degree of depth and width and the CoolMOS structure are identical;
Step 3. under the state of retention surface silicon dioxide film, utilizes epitaxy method growing P-type epitaxial silicon in order to fill deep trench as shown in Figure 7, at the inner p type single crystal silicon that forms of groove, constitutes the longitudinal P type zone of CoolMOS;
Step 4. as shown in Figure 8, utilize the surperficial silicon dioxide film that before epitaxial growth, keeps as etching stop layer, with returning the P type epitaxial silicon that the carving technology removal goes out in the silicon dioxide film superficial growth, and the P type extension in the groove etched into flute surfaces to flush (promptly etch near N type epitaxial surface, that is etch into the intersection of N type epitaxial region and silicon dioxide film), guarantee the smooth of silicon chip surface;
Step 5. as shown in Figure 9, remove the flute surfaces silicon dioxide film with wet etching, expose epitaxial surface, growth grid silicon dioxide film on extension, the grid polycrystalline silicon (polycrystalline grid) of on the grid silicon dioxide film, growing, body injects and forms the tagma, and the source is injected and formed the source region, finally all forms the alternate CoolMOS epitaxial structure of N type P type in silicon face and body.
Claims (4)
1. the formation method in longitudinal P type district in the CoolMOS structure is characterized in that, comprises the steps:
(1) property growth N type extension once on silicon substrate;
(2) growth layer of silicon dioxide film on N type extension is selected on N type extension then and is wanted the portion in growing P-type district to separate deep trench;
(3) under the state of retention surface silicon dioxide film, utilize epitaxy method growing P-type epitaxial silicon in order to fill deep trench;
(4) epitaxial silicon of using back carving technology to remove to go out in the silicon dioxide film superficial growth, and the P type extension in the deep trench etched near N type epitaxial surface;
(5) remove silicon dioxide film, expose epitaxial surface, growth grid silicon dioxide film on extension, the grid polycrystalline silicon of growing on the grid silicon dioxide film, body inject and form the tagma, and the source is injected and is formed the source region, finally forms the longitudinal P type district epitaxial structure of CoolMOS.
2. the formation method in longitudinal P type district is characterized in that in the CoolMOS structure as claimed in claim 1, and step (3) utilizes epitaxy method growing P-type epitaxial silicon in order to fill deep trench, at the inner p type single crystal silicon that forms of deep trench.
3. the formation method in longitudinal P type district in the CoolMOS structure as claimed in claim 1, it is characterized in that, step (4) utilizes silicon dioxide film as etching stop layer, P type extension is returned quarter, the P type epitaxial silicon that removal goes out in the silicon dioxide film superficial growth, and the P type extension of control trench area is etched near N type epitaxial surface, guarantees the smooth of silicon chip surface.
4. the formation method in longitudinal P type district is characterized in that in the CoolMOS structure as claimed in claim 1, and step (5) adopts wet etching to remove silicon dioxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810044107 CN101752252A (en) | 2008-12-16 | 2008-12-16 | Forming method of longitudinal P-shaped district in CoolMOS structure |
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| CN 200810044107 CN101752252A (en) | 2008-12-16 | 2008-12-16 | Forming method of longitudinal P-shaped district in CoolMOS structure |
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| CN 200810044107 Pending CN101752252A (en) | 2008-12-16 | 2008-12-16 | Forming method of longitudinal P-shaped district in CoolMOS structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142459A (en) * | 2010-12-23 | 2011-08-03 | 上海北京大学微电子研究院 | Coolmos structure |
| WO2012167715A1 (en) * | 2011-06-08 | 2012-12-13 | 无锡华润上华半导体有限公司 | Method for forming deep-channel super-pn junction |
| CN105510263A (en) * | 2016-01-23 | 2016-04-20 | 河北科技大学 | HPLC analytical method for 3-amino piperidine isomer |
-
2008
- 2008-12-16 CN CN 200810044107 patent/CN101752252A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142459A (en) * | 2010-12-23 | 2011-08-03 | 上海北京大学微电子研究院 | Coolmos structure |
| WO2012167715A1 (en) * | 2011-06-08 | 2012-12-13 | 无锡华润上华半导体有限公司 | Method for forming deep-channel super-pn junction |
| EP2709142A1 (en) * | 2011-06-08 | 2014-03-19 | CSMC Technologies Fab1 Co., Ltd. | Method for forming deep-channel super-pn junction |
| EP2709142A4 (en) * | 2011-06-08 | 2015-01-07 | Csmc Technologies Fab1 Co Ltd | Method for forming deep-channel super-pn junction |
| CN105510263A (en) * | 2016-01-23 | 2016-04-20 | 河北科技大学 | HPLC analytical method for 3-amino piperidine isomer |
| CN105510263B (en) * | 2016-01-23 | 2018-08-31 | 河北科技大学 | A kind of HPLC analysis methods of 3- amino piperidines isomers |
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Application publication date: 20100623 |