CN103123898B

CN103123898B - The manufacture method of super junction DMOS device

Info

Publication number: CN103123898B
Application number: CN201110372018.0A
Authority: CN
Inventors: 张帅; 刘远良
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-11-21
Filing date: 2011-11-21
Publication date: 2015-12-02
Anticipated expiration: 2031-11-21
Also published as: CN103123898A

Abstract

The invention discloses a kind of manufacture method of super junction DMOS device, in a substrate upper end growth N-type epitaxy layer; Utilize high annealing to be injected by P trap to advance; Multiple first groove is formed in described N-type epitaxy layer; In described first groove, fill p type single crystal silicon, form P type post; Cmp CMP is adopted to be removed by the p type single crystal silicon of described first groove top surface; Utilize thermal oxidation at the apical growth layer of silicon dioxide film of described N-type epitaxy layer; Wet etching is adopted to be removed completely by described silica membrane; Second groove is formed between two P type posts; In described second groove, fill polysilicon, utilize dry etching to carry out back carving, the polysilicon outside the second groove is removed; Ion implantation is utilized to form source area in the P trap of described first groove both sides; Drain electrode is formed at the back side of described substrate.The present invention can improve the stability of process, and then improves the electrical property of device.

Description

The manufacture method of super junction DMOS device

Technical field

The present invention relates to semiconductor integrated circuit field, particularly relate to a kind of field effect transistor manufacture method with super junction.

Background technology

Super junction power device is rapid, the widely used Novel power semiconductor of a kind of development.It is on the basis of common double diffused metal oxide emiconductor (DMOS), by introducing super junction (SuperJunction) structure, make it DMOS input impedance be high, switching speed is fast, operating frequency is high except possessing, easy voltage control, thermally-stabilised good, drive circuit simple, be easy to except the feature such as integrated, the conducting resistance also overcoming DMOS is pressed into the shortcoming that 2.5 power relations increase along with breakdown potential.

Current super junction DMOS has been widely used in power supply towards PC, notebook computer, net book, mobile phone, illumination (high-voltage gas discharging light) product and the consumption electronic product such as television set (liquid crystal or plasma TV) and game machine or adapter.

The preparation method of existing super junction DMOS is mainly divided into two large classes: a kind of is utilize repeatedly the mode of extension and injection in N-type epitaxial substrate, form multiple spaced P type post; Another carries out the column filling of P type after deep plough groove etched.

Adding P type column filling mode utilizing deep trench prepares in the process of super junction power device, usually the VDMOS (vertical proliferation field-effect transistor) of plane is made, easily like this between two P traps closed on, form JFET (knot effect transistor), thus cause the conducting resistance of device to increase.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of manufacture method of super junction DMOS device, can improve the stability of process, and then improves the electrical property of device.

For solving the problems of the technologies described above, the manufacture method of super junction DMOS device of the present invention adopts following technical scheme to realize:

Step 1, grows in a substrate upper end N-type epitaxy layer that one deck has adequate thickness;

Step 2, utilizes light shield to define the region needing P trap to inject in the upper end of described N-type epitaxy layer, utilizes high annealing to be injected by P trap and advances;

Step 3, defines the pattern of groove by one deck light shield, adopt dry etching, form multiple first grooves of certain depth in described N-type epitaxy layer;

Step 4, adopts the filling mode of selective epitaxial deposition, in described first groove, fills p type single crystal silicon, forms P type post;

Step 5, adopts cmp CMP to be removed by the p type single crystal silicon of described first groove top surface, makes the surface rubbing of this first groove;

Step 6, utilizes thermal oxidation at the apical growth layer of silicon dioxide film of described N-type epitaxy layer;

Step 7, adopts wet etching to be removed completely by described silica membrane;

Step 8, adopts photoetching and is dry-etched between two P type posts and forms second groove;

Step 9, fills polysilicon in described second groove, utilizes dry etching to carry out back carving, is removed by the polysilicon outside the second groove;

Step 10, utilizes ion implantation to form source area in the P trap of described first groove both sides;

Step 11, to described substrate back, thinning and steaming gold, forms drain electrode at the back side of described substrate.

Method of the present invention adds P column filling mode in existing deep trench to prepare on the process basis of super junction power device, by improving manufacturing process flow, adopt the mode of selective epitaxial to fill P type post that deep trench formed is dense and do not have hole; By adding growth and the removal of one deck sacrificial oxide layer after the cmp process, the silicon that can weaken or remove deep trench annex remains.There is in conjunction with groove-shaped VDMOS process processing the field effect transistor of super junction simultaneously, effectively can remove junction transistors effect (JFET), thus reduce the conducting resistance of VDMOS; Can process stabilizing be improved like this, reduce power consumption, and then improve the electrical property of device.

Accompanying drawing explanation

Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:

Fig. 1-11 is manufacture method control flow schematic diagrames of super junction DMOS device.

Embodiment

Shown in composition graphs 1-11, in one embodiment, the step of specific implementation is as follows for the manufacture method of described super junction DMOS device:

Step 1, shown in Figure 2, end growth one deck has the N-type epitaxy layer 3 of adequate thickness on the substrate 2.The thickness of described N-type epitaxy layer 3 determined by the withstand voltage of device layout.The resistivity of N-type epitaxy layer 3 is higher, normally 1 ~ 8ohm.cm; And the resistivity of substrate 2 is low, be approximately 1 ~ 5mohm.cm.

Step 2, as shown in Figure 3, utilizes light shield to define in the upper end of described N-type epitaxy layer 3 region needing P trap 5 to inject, and then utilizes high-temperature annealing process to be injected by P trap 5 and advances.

Step 3, as shown in Figure 4, defines the pattern of deep trench by one deck light shield, adopt dry etching, form multiple deep trench 9 of certain depth in described N-type epitaxy layer 3.The degree of depth of deep trench 9 can decide according to the puncture voltage of device.

Oxide skin(coating) can be adopted during dry etching deep trench 9 as hard mask layer (Hardmask), first etch hard mask layer, and then etch deep trench 9; Also can not adopt hard mask layer, directly carry out dry etching and form deep trench 9.

Step 4, as shown in Figure 5, adopts the filling mode of selective epitaxial deposition, in deep trench 9, fills p type single crystal silicon, forms P type post 4.

Step 5, as shown in Figure 6, adopts CMP (cmp) method to be removed by the p type single crystal silicon of deep trench 9 top surface, make the surface rubbing of deep trench 9, but have portion of monocrystalline silicon in the both sides, top of deep trench 9 residual.

Step 6, as shown in Figure 7, utilize the mode of thermal oxidation at the apical growth layer of silicon dioxide film 10 of described N-type epitaxy layer 3, this film thickness can be determined according to the monocrystalline silicon thickness that the both sides, top of deep trench 9 are residual, and monocrystalline silicon residual thickness of making peace greatly is consistent.

Step 7, as shown in Figure 8, adopts the method for wet etching to be removed completely by described silica membrane 10.

Step 8, as shown in Figure 9, adopts traditional photoetching and dry etch process method between two P type posts 4, form a new groove 7, the degree of depth greatly about 2-4 μm, in order to form groove type MOS pipe.

Step 9, as shown in Figure 10, fills polysilicon 8 in the new groove 7 formed, and utilizes dry etching to carry out back carving subsequently, is removed by the polysilicon 8 outside groove 7.

Step 10, as shown in figure 11, utilizes ion implantation to form source area 6 in the P trap 5 of deep trench 9 both sides.

Step 11, as shown in Figure 1, after all processing steps waiting device to prepare have carried out, carry out substrate 2 back side (substrate 2 lower end shown in Fig. 1) thinning and steam gold, the back side of substrate 2 formed drain electrode 1.

Above by embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims

1. a manufacture method for super junction DMOS device, is characterized in that, comprises the steps:

Step 6, utilizes thermal oxidation at the apical growth layer of silicon dioxide film of described N-type epitaxy layer, and the monocrystalline silicon thickness that the thickness of described silica membrane is residual with the first both sides, groove top is equal;

2. the method for claim 1, is characterized in that: the resistivity of described N-type epitaxy layer is greater than the resistivity of substrate.

3. the method for claim 1, is characterized in that: oxide skin(coating) can be adopted as hard mask layer during implementation step 3 dry etching the first groove, first etch hard mask layer, and then etch the first groove; Also can directly carry out dry etching and form the first groove.

4. the method for claim 1, is characterized in that: during implementation step 6, and the monocrystalline silicon thickness that the thickness of described silica membrane is residual with the first both sides, groove top is equal.

5. the method for claim 1, is characterized in that: during implementation step 8, and the degree of depth of described second groove is 2-4 μm, in order to form groove type MOS pipe.