CN103065966B - A kind of process of preparing of super junction - Google Patents
A kind of process of preparing of super junction Download PDFInfo
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- CN103065966B CN103065966B CN201110323883.6A CN201110323883A CN103065966B CN 103065966 B CN103065966 B CN 103065966B CN 201110323883 A CN201110323883 A CN 201110323883A CN 103065966 B CN103065966 B CN 103065966B
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Abstract
The invention discloses a kind of process of preparing of super junction, comprise the steps: 1, prepare a slice N-type epitaxial silicon chip and do substrate; 2, defined the pattern of deep trench by one deck light shield, adopt the method for dry etching, form deep trench; 3, in deep trench, fill P-type silicon, form P post, with chemical and mechanical grinding method, silicon chip surface is polished subsequently; 4, the region utilizing light shield to define to need P trap to inject, recycling energetic ion implanting p-type impurity forms P trap, then adopts the method for rapid thermal treatment to activate Doped ions; 5, deposition one deck silica and doped polycrystalline silicon are as grid successively, then form grid by photoetching and etching technics; 6, utilize ion implantation to form source electrode; 7, after all techniques waiting device to prepare have been carried out, then carry out crystalline substance the back of the body thinning and steam gold chip back surface formed drain electrode.The present invention effectively can reduce the heat budget of P trap, reduces P trap lateral diffusion length, increases the number of transistors in unit are.
Description
Technical field
The invention belongs to electronic technology field, relate to power semiconductor, be specifically related to a kind of process of preparing of super junction.
Background technology
Super junction power device is rapid, the widely used Novel power semiconductor of a kind of development.It is on the basis of common double diffused metal oxide emiconductor (DMOS), by introducing super junction (SuperJunction) structure, except possessing, DMOS input impedance is high, switching speed is fast, operating frequency is high, easy voltage control, thermally-stabilised good, drive circuit are simple, be easy to except the feature such as integrated, and the conducting resistance also overcoming DMOS is pressed into the shortcoming that 2.5 power relations increase along with breakdown potential.Current super junction DMOS has been widely used in power supply towards PC, notebook computer, net book, mobile phone, illumination (high-voltage gas discharging light) product and the consumption electronic product such as television set (liquid crystal or plasma TV) and game machine or adapter.
The preparation technology of current super junction power device is mainly divided into two large classes, and a kind of is utilize repeatedly the mode of extension and injection to form P post in N-type epitaxial substrate; Another is formed in the mode of the deep plough groove etched P of adding column filling.
Add P post utilizing deep trench to insert mode and prepare in the technique of super junction, P trap was formed by thermal diffusion usually before P post is formed.The P trap formed in this way causes more greatly the horizontal proliferation area of P trap larger due to heat budget in processing procedure (thermalbudget), and then cause the gross area of device to increase, be unfavorable for that the cellular of device layout is integrated, thus cause device performance to decline, cost increases.
Metal-oxide semiconductor (MOS) (VDMOS) is spread for comparatively popular vertical double diffusion at present, as shown in Figure 1, if adopt traditional process before P post 14 is formed, the technique adopting ion implantation to increase temperature annealing prepares P trap 15, in order to reach certain depth, then P trap lateral diffusion length 18 also can expand thereupon.Simultaneously in order to avoid punch through (punch through) operationally occurs adjacent two P traps 15, minimum spacing must be ensured between two P traps 15, thus limit transistor number integrated in unit are.
Summary of the invention
The technical problem to be solved in the present invention is by improving super junction preparation technology, optimize the design with the semiconductor separation part of super-junction structures, the heat budget of effective reduction P trap, reduce P trap lateral diffusion length, increase the number of transistors in unit are, thus raising device performance, reduce manufacturing cost, simultaneously this technique also convenient threshold voltage regulating components and parts.
For solving the problems of the technologies described above, the invention provides a kind of process of preparing of super junction, comprising the steps:
Step 1, prepares a slice N-type epitaxial silicon chip and does substrate;
Step 2, defines the pattern of deep trench by one deck light shield, adopt the method for dry etching, forms deep trench;
Step 3, fills P-type silicon in deep trench, forms P post, is polished by silicon chip surface subsequently with chemical and mechanical grinding method;
Step 4, the region utilizing light shield to define to need P trap to inject, then utilizes energetic ion implanting p-type impurity to form P trap, then adopts the method for rapid thermal treatment to activate Doped ions;
Step 5, deposition one deck silica and doped polycrystalline silicon are as grid successively, then form grid by photoetching and etching technics;
Step 6, utilizes ion implantation to form source electrode;
Step 7, after all techniques waiting device to prepare have been carried out, then carry out crystalline substance the back of the body thinning and steam gold chip back surface formed drain electrode.
In step 1, described substrate is made up of two-layer, and one deck is the monocrystalline silicon piece that resistivity is lower, and then utilize epitaxially grown mode to grow the higher epitaxial loayer of a layer resistivity in the above, epitaxy layer thickness is decided by the withstand voltage of device.
In step 2, the dry ionic etching technics that is formed by of described deep trench is formed, and the degree of depth of deep trench decides according to the puncture voltage of device; When dry etching deep trench, the hard mask of band can be adopted or be not with hard mask two kinds of techniques.The technique of the hard mask of described band is specially: adopt oxide, nitride or carbide lamella as hard mask, first etch hard mask, and then etch deep trench; The described technique not with hard mask is specially: employing photoresist is that the dry etching direct etching of mask forms deep trench.
In step 3, the formation of described P post is that the mode adopting extension to fill p type single crystal silicon or polysilicon deposition fills P-type silicon in deep trench.
In step 4, after P trap injects, increase by a step ion implantation be used for the threshold voltage of special adjusting means.
Compared to the prior art, the present invention has following beneficial effect: the present invention mainly adds P post for deep trench and inserts the technique that mode prepares super junction, by improving the manufacturing process flow of super junction, after the formation process of P trap being placed in the formation of P post, energetic ion injection technology is adopted to carry out the injection of P trap, after P trap injects, add the injection of a step for adjusting threshold voltage simultaneously, then carry out quick high-temp heat treatment and will inject the activation of ion original position.Effectively can reduce the heat budget of P trap like this, reduce P trap lateral diffusion length, increase the number of transistors in unit are.The present invention, by improving super junction preparation technology, optimizes the design with the semiconductor separation part of super-junction structures, thus improves device performance, reduces manufacturing cost, simultaneously this technique also convenient threshold voltage regulating components and parts.
Accompanying drawing explanation
Fig. 1 is the structural representation of the super junction adopting traditional process to be formed;
Fig. 2 be the super junction adopting present invention process method to be formed structural representation (namely the inventive method step 7 complete after schematic diagram);
Fig. 3 is the schematic diagram after the inventive method step 1 completes;
Fig. 4 is the schematic diagram after the inventive method step 2 completes;
Fig. 5 is the schematic diagram after the inventive method step 3 completes;
Fig. 6 is the schematic diagram after the inventive method step 4 completes;
Fig. 7 is the schematic diagram after the inventive method step 5 completes;
Fig. 8 is the schematic diagram after the inventive method step 6 completes.
Description of reference numerals is as follows:
In FIG, 11 is drain electrode; 12 is monocrystalline silicon piece; 13 is epitaxial loayer; 14 is P post; 15 is P trap, and 16 is source electrode, and 17 is grid, and 18 is P trap lateral diffusion length.
In Fig. 2-Fig. 8,1 is drain electrode; 2 is monocrystalline silicon piece; 3 is epitaxial loayer; 4 is P post; 5 is P trap, and 6 is source electrode, and 7 is grid, and 8 is P trap lateral diffusion length.
Embodiment
Below in conjunction with drawings and Examples, the present invention is further detailed explanation.
The process of preparing of a kind of super junction of the present invention, mainly comprises the steps:
1. as shown in Figure 3, preparation a slice does substrate with the N-type epitaxial silicon chip of adequate thickness, and described substrate is made up of two-layer, and one deck is the monocrystalline silicon piece 2 that resistivity is lower, then utilizes epitaxially grown mode to grow the higher epitaxial loayer of a layer resistivity 3 in the above.And epitaxial loayer 3 thickness determined by the withstand voltage (i.e. rated voltage) of device layout.
2. as shown in Figure 4, the pattern (namely adopting the photoetching process that this area is conventional) of deep trench 9 is defined by one deck light shield, adopt the method for dry etching, form the deep trench 9 of certain depth, its deep trench degree of depth can decide according to the puncture voltage of device.In this process, band oxide, nitride or carbide lamella can be adopted during dry etching deep trench 9 as hard mask layer (Hard mask, or be called hard mask), first etch hard mask, and then etch deep trench 9.Or without hard mask, can adopt photoresist be mask dry etching direct etching formed deep trench 9.
3. as shown in Figure 5, adopt extension to fill the mode of p type single crystal silicon or polysilicon deposition, in deep trench, fill P-type silicon, form P post 4, use CMP (cmp) method to be polished by silicon chip surface subsequently.
4. as shown in Figure 6, the region (namely adopting the photoetching process that this area is conventional) utilizing light shield to define to need P trap to inject, then utilize energetic ion implanting p-type impurity to form P trap 5, such as adopt boron ion, Implantation Energy scope is at 1-2.5Mev.P trap can increase by a step P type ion implantation after injecting, and as boron ion implantation, its Implantation Energy scope is at 100-150Kev.Because this ion implantation is in the channel surface of device, the threshold voltage of special adjusting means thus can be used for.Then the method for rapid thermal treatment is adopted to carry out original position activation to Doped ions.The temperature suggestion of rapid thermal treatment is 900-1200 DEG C, and the time is 20-90 second.In this step, the injection of P trap 5 must be placed on after P post 4 formed, and the mode of its ion implantation is that energetic ion injects.
5. as shown in Figure 7, deposition one deck silica and polysilicon are as grid successively, then form grid 7 by photoetching and etching technics.
6. as shown in Figure 8, utilize ion implantation to form source electrode 6, the energy injection arsenic of 60-100Kev can be utilized to form source electrode 6.
7. as shown in Figure 2, after all techniques waiting device to prepare have been carried out, then carry out crystalline substance the back of the body thinning and steam gold chip back surface formed drain electrode 1.
After adopting the inventive method, as shown in Figure 2, because P trap 5 is placed on preparation after P post 4 is formed, when such one side can avoid P post 4 to make, pyroprocess is on the impact of P trap horizontal proliferation, on the other hand because have employed the mode of energetic ion injection, can by the depth down of ion implantation, thus reduce the time of subsequent thermal process or directly use the technique of rapid thermal annealing (Rapid thermal process) instead, so just can reduce P trap lateral diffusion length 8 (compare with the P trap lateral diffusion length 18 in Fig. 1 and have obvious reduction) further, increase the number of transistors in unit are, thus raising device performance, reduce manufacturing cost, also facilitate the threshold voltage regulating components and parts simultaneously.
Claims (10)
1. a process of preparing for super junction, is characterized in that, comprises the steps:
Step 1, prepares a slice N-type epitaxial silicon chip and does substrate;
Step 2, defines the pattern of deep trench by one deck light shield, adopt the method for dry etching, forms deep trench;
Step 3, fills P-type silicon in deep trench, forms P post, is polished by silicon chip surface subsequently with chemical and mechanical grinding method;
Step 4, the region utilizing light shield to define to need P trap to inject, then utilize energetic ion implanting p-type impurity to form P trap, Implantation Energy scope, at 1-2.5Mev, then adopts the method for rapid thermal treatment to activate Doped ions;
Step 5, deposition one deck silica and doped polycrystalline silicon are as grid successively, then form grid by photoetching and etching technics;
Step 6, utilizes ion implantation to form source electrode;
Step 7, after all techniques waiting device to prepare have been carried out, then carry out crystalline substance the back of the body thinning and steam gold chip back surface formed drain electrode.
2. the process of preparing of super junction according to claim 1, it is characterized in that: in step 1, described substrate is made up of two-layer, one deck is monocrystalline silicon piece, then epitaxially grown mode is utilized to grow one deck epitaxial loayer in the above, the resistivity of epitaxial loayer is higher than the resistivity of monocrystalline silicon piece, and epitaxy layer thickness is decided by the withstand voltage of device.
3. the process of preparing of super junction according to claim 1, is characterized in that: in step 2, and the dry ionic etching technics that is formed by of described deep trench is formed, and the degree of depth of deep trench decides according to the puncture voltage of device; When dry etching deep trench, the hard mask of band can be adopted or be not with hard mask two kinds of techniques.
4. the process of preparing of super junction according to claim 3, is characterized in that: the technique of the hard mask of described band is specially: adopt oxide, nitride or carbide lamella as hard mask, first etch hard mask, and then etch deep trench; The described technique not with hard mask is specially: employing photoresist is that the dry etching direct etching of mask forms deep trench.
5. the process of preparing of super junction according to claim 1, is characterized in that: in step 3, and the formation of described P post is that the mode adopting extension to fill p type single crystal silicon or polysilicon deposition fills P-type silicon in deep trench.
6. the process of preparing of super junction according to claim 1, is characterized in that: in step 4, and the described energetic ion implanting p-type impurity formation P trap that utilizes is specially: adopt boron ion implantation.
7. the process of preparing of super junction according to claim 1, is characterized in that: in step 4, increases by a step P type ion implantation and be used for the threshold voltage of special adjusting means after P trap injects.
8. the process of preparing of super junction according to claim 7, is characterized in that: described in the rear increase of P trap injection one step P type ion implantation, this step P type ion implantation specifically adopts boron ion implantation, and its Implantation Energy scope is at 100-150Kev.
9. the process of preparing of super junction according to claim 1, is characterized in that: in step 4, and the temperature of described rapid thermal treatment is 900-1200 DEG C, and the time is 20-90 second.
10. the process of preparing of super junction according to claim 1, is characterized in that: in step 6, and described ion implantation adopts arsenic ion to inject, and its Implantation Energy is 60-100Kev.
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| CN104134609B (en) * | 2013-05-03 | 2017-08-11 | 无锡华润微电子有限公司 | The semiconductor devices and its manufacture method of multilayer epitaxial super junction framework |
| CN112117330A (en) * | 2020-09-21 | 2020-12-22 | 南京华瑞微集成电路有限公司 | Device structure for improving voltage resistance of deep-groove super-junction MOSFET and process method thereof |
| CN116646252A (en) * | 2023-07-27 | 2023-08-25 | 北京智芯微电子科技有限公司 | Super junction device manufacturing method, super junction device, chip and circuit |
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