CN102709191A - Process for manufacturing series of intermediate-voltage N-type vertical conduction double-diffused metal oxide semiconductor transistors by using composite epitaxy - Google Patents
Process for manufacturing series of intermediate-voltage N-type vertical conduction double-diffused metal oxide semiconductor transistors by using composite epitaxy Download PDFInfo
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Abstract
The invention discloses a process for manufacturing series of intermediate-voltage N-type vertical conduction double-diffused metal oxide semiconductor (VDMOS) transistors by using composite epitaxy. The process comprises the steps of: batch feeding, first-step epitaxy, second-step epitaxy, third-step epitaxy, fourth-step epitaxy, field oxidation, etching of an active area, high-concentration boron injection and junction depth increasing, phosphorus injection and junction depth increasing, gate oxidation, polycrystalline silicon gate deposition and doping, PWELL boron injection and junction depth increasing, source N+ arsenic injection and junction depth increasing, contact hole etching, aluminum evaporation and corrosion, back thinning evaporation and the like. By a process platform, any additional procedure and operation is avoided, and on-resistance can be lowered by 10 percent on the basis of ensuring withstand voltage; by the VDMOS transistor manufactured by the process, a high-current intense-electric field effect can be effectively suppressed, and the safety working area of a device is enlarged to a certain extent; and the on-resistance is lowered, so that power consumption is greatly reduced, energy sources are saved, and the reliability of a circuit is greatly improved.
Description
Technical field
The present invention is a kind of anti-pressure N type series (withstand voltage 600V, the conducting electric current is at 1 ampere to 15 amperes) VDMOS process that is used for making, and belongs to semiconductor and processes technical field.
Background technology
The full name of VDMOS is Vertical conduction double-diffused metal oxide semiconductor, and promptly the vertical DMOS field-effect transistor was proposed by people such as H.W.Collins in 1979.
Vdmos transistor has been obtained significant progress at present through the development in surplus 30 years.He has obtained extensive use at aspects such as switching power supply, high-frequency heating, computer interface circuit and power amplifiers at present with high input impedance, low conducting resistance and high a series of advantages such as switching speed.Can affirm that Along with people's is to the further in-depth of energy-saving and emission-reduction understanding, VDMOS is that the switch power supply system of main devices will show more wide application prospect.
Because it is more and more lower that portable set and radio communication require power consumption, thereby reduce conducting resistance, reduce the top priority that power consumption is the VDMOS research and development.For VDMOS type power device, obtain sufficiently high drain-source breakdown voltage (
BV) and alap conducting resistance (
ROn) be to need two main aspects of consideration simultaneously in the design.For withstand voltage high MOS device,
ROn is mainly determined by epitaxial region resistance.Epitaxial loayer is thicker, and resistivity is high more, and puncture voltage is also higher, and conducting resistance is also big more simultaneously.Therefore, there is the contradiction of puncture voltage and conducting resistance in the MOS device, and the two all depends primarily on epitaxial region parameter (thickness and doping content).
The processing of VDMOS chip now all is to adopt even epitaxy technology.The serial VDMOS chip of middle pressure is the difference that difference is conducting resistance between the different conducting current specification, and different specifications is to rely on the variation of chip area to realize the differential of conducting resistance.In other words, the corresponding a kind of conducting resistance normal values of current specification, corresponding corresponding chip area.
Conventional VDMOS technological process is as shown in Figure 1, and the main technique step is:
1) feeds intake;
2) evenly extension (epi) growth;
3) oxidation;
4) active area etching;
5) high concentration P+ (boron) injects, and knot is dark;
6) phosphorus injects, and knot is dark;
7) gate oxidation, the oxide layer of long 800-1100A;
8) polysilicon gate deposit and doping;
9) PWELL (P trap) boron injects, and knot is dark;
10) arsenic of source electrode N+ injects, and knot is dark;
11) contact hole etching;
12) evaporation of aluminum, corrosion aluminium;
13) thinning back side, back side back of the body silver.
About the theory of optimizing the VDMOS extension many researchs have been arranged at present, conclusion all is the gradual the best that is doped to.But in reality processing, so gradual doped epitaxial technology is difficult for realizing up to the present, also do not have the optimization epitaxy technique of practicality to be used for manufacturing.The present invention is according to the theoretical principle of VDMOS; Real process in conjunction with epitaxy technique; Through the segmentation control of epitaxial process,, develop the manufacture crafts of the compound extension that is used for a large amount of production pressure VDMOS to the serial N type of middle pressure VDMOS (all referring to N type VDMOS in the back literary composition).Adopt compound epitaxy technique to press that the actual measurement of serial VDMOS is withstand voltage still to have 650V in making, but conducting resistance has descended 10% than the VDMOS that adopts common process to make.
Summary of the invention
The object of the invention is through the compound extension of processing, produced the vertical double diffusion FET technology of the serial N type of middle pressure that performance more optimizes then, and it is simple that this technology has technical process, and the photoetching number of times is few, and cost is low, processes the simple advantage of control.
The present invention adopts following technical scheme for realizing above-mentioned purpose:
Press the manufacture craft of N type series MOS FET during a kind of compound extension is made, the detailed process of its technology is following:
(1) feed intake: mix arsenic or mix antimony silicon substrate material, resistivity is at 0.03ohm.cm and following;
(2) the extension first step: growth 3-5um thickness, the N type extension of resistivity 0.5-1.5 ohm.cm;
(3) second step of extension: growth 3-5um thickness, the N type extension of resistivity 8-12 ohm.cm;
(4) the 3rd step of extension: growth 38-46um thickness, the N type extension of resistivity 14-22 ohm.cm;
(5) the 4th step of extension, growth 5-8um thickness, the N type extension of resistivity 10-16 ohm.cm;
(6) oxidation: the oxide layer of growth 0.8-1.2um thickness;
(7) active area etching: the oxide layer that will do the position of device is corroded clean;
(8) high concentration boron P+ injects, and knot is dark: inject energy 40-80kev, dosage 8e14-1.5e15/cm
2, knot adopts 1100 ℃-1200 ℃ deeply, 80-150 minute N
2Add little O
2(volume ratio 0%-5.5%);
(9) phosphorus injects, and knot is dark: inject energy 80-130kev, dosage 1e12-2e12/cm
2Knot is dark to adopt 1100 ℃-1200 ℃, 80-150 minute N
2Add little O
2(volume ratio 0%-5.5%);
(10) gate oxidation: the about 850-1200 of oxidated layer thickness;
(11) polysilicon gate deposit and doping: polycrystalline deposition 4000-7500, adopt phosphorous diffusion to mix;
(12) P trap boron injects, and knot is dark: inject energy 40-80kev, dosage 2.9e13-3.9e13/cm
2, knot adopts 1100 ℃ of-1200 ℃ of 80-150 minute N deeply
2Add little O
2(volume ratio 0%-5.5%);
(13) arsenic of source electrode N+ injects, and knot is dark: inject energy 80-130kev, dosage 5e15-1.5e16/cm
2Knot is dark to adopt 950 ℃-1000 ℃, 150-250 minute N
2Add little O
2(volume ratio 0%-5.5%);
(14) contact hole etching: adopt the silicon dioxide in the clean hole of dry etching, form the hole of back aluminium contact;
(15) evaporation of aluminum, corrosion aluminium: evaporation thickness is the metal level of 3-5um, forms surface electrode grid and source electrode;
(16) the attenuate back of the body steams: thinning back side is to 200-280um thickness, and back side evaporation 0.8-1.2um thickness is silver-colored.
Under this technique platform, the vertical structure of the final VDMOS that forms is as shown in Figure 3.
The epitaxial process here is divided into 4 parts, and in the actual course of processing, the extension program of the original common processes of just simple adjustment is accomplished.Original epitaxial process is divided into 4 parts, is the setting on the program fully, does not increase any manufacturing procedure and step.
Utilize this technique platform, we can not increase any extra procedure and operation, are guaranteeing on the withstand voltage basis conducting resistance to be reduced by 10%.And the VDMOS pipe that adopts this technology to make can effectively suppress the big field effect of big electric current, widen the safety operation area of device to a certain extent.Reducing of conducting resistance makes power consumption reduce greatly, saved the energy, also improved the reliability of circuit simultaneously greatly.
Description of drawings
Fig. 1 is conventional VDMOS process flow diagram.
Fig. 2 is a process flow diagram of the present invention.
Fig. 3 is the vertical structure sketch map of the final device that forms of the present invention.
Embodiment
Press the technology of serial vertical double diffusion FET during a kind of compound extension as shown in Figure 2 is made, concrete implementation is following:
1) feed intake: mix arsenic or mix antimony silicon substrate material, resistivity is at 0.03ohm.cm and following.
2) the extension first step: growth 4um thickness, the N type extension of resistivity 1 ohm.cm.Be used for forming the high concentration transition region with the high concentration substrate.Can reduce conducting resistance.
3) second step of extension: growth 4um thickness, the N type extension of resistivity 10 ohm.cm.Concentration transition region in being used for forming with high concentration first extension.Also can reduce conducting resistance.
4) the 3rd step of extension: growth 42um thickness, the N type extension of resistivity 18 ohm.cm.For VDMOS provides Withstand voltage layer, guarantee above withstand voltage of the 630V of VDMOS.
5) the 4th step of extension, growth 6um thickness, the N type extension of resistivity 14 ohm.cm.The surface is high concentration layer slightly, and after removing the junction depth of surperficial Pwell, effectively thickness is greatly about 2-3um.The slightly conductive path of high concentration is provided, the pinched resistor part in the highly effective reduction VDMOS conducting resistance during for the VDMOS conducting.
6) oxidation: in 1000 ℃ of wet oxidations 350 minutes, the oxide layer of growth 1um thickness, the part of device is not done in protection.
7) active area etching: the window that will do the position of device is opened.
8) high concentration P+ (boron) injects, and knot is dark: inject energy 60kev, dosage 1.0e15/cm
21150 ℃ of 100 minutes N of the dark employing of knot
2Add little O
2(2.5%).Form the surperficial potential dividing ring of VDMOS, guarantees withstand voltagely, specifically junction depth can be according to withstand voltage suitable adjustment.
9) phosphorus injects, and knot is dark: injection energy 120kev (kiloelectron-volt), dosage 1e12/cm
21150 ℃ of 120 minutes N of the dark employing of knot
2Add little O
2(2.5%).。Improve surface concentration, the 4th part of purpose and extension is the same to be in order to reduce the pinched resistor part in the VDMOS conducting resistance.
10) gate oxidation: 850 ℃ of 200 minutes wet oxygens add TCA.Oxidated layer thickness about 1100.
11) polysilicon gate deposit and doping: should advance boiler tube behind the grid oxygen at once and carry out polycrystalline deposition, in order to avoid surperficial pickup.Polycrystalline deposition 6000 adopts phosphorous diffusion to mix.Form the grid of VDMOS.
12) PWELL (P trap) boron injects, and knot is dark: what the P trap formed is the channel region of VDMOS, and the concentration of adjusting it can be adjusted the cut-in voltage of VDMOS.Inject energy 80kev, dosage 3.5e13/cm
21150 ℃ of 120 minutes N of the dark employing of knot
2Add little O
2(1.5%).。
13) arsenic of source electrode N+ injects, and knot is dark: inject energy 120kev, dosage 1e16/cm
2Knot is dark to adopt 975 ℃, 200 minutes N
2Add little O
2(1.5%).。
14) contact hole etching: adopt the silicon dioxide in the clean hole of dry etching, form the hole of back aluminium contact.
15) evaporation of aluminum, corrosion aluminium: evaporation thickness is the aluminium copper silicon layer of 4um, forms surface electrode grid and source electrode.
16) the attenuate back of the body steams: thinning back side is to 250um thickness, and back side evaporation 0.9um thickness silver forms device.
A cover domain same with 2 amperes of specifications among the serial VDMOS of middle pressure is designed to example: adopt common process processing, withstand voltage representative value 650V, conducting resistance representative value are 3.8ohm; Adopt the chip of our new technology processing, withstand voltage representative value is 650V still, and the conducting resistance representative value is 3.4ohm.Conducting resistance descends clearly, approximately is original 90%.The decline of conducting resistance, the power consumption the when client uses just descends, can be effectively energy-conservation, reduce system temperature, improve life-span and the reliability of using greatly.
Claims (1)
1. press the manufacture craft of N type series MOS FET during a compound extension is made, the detailed process of its technology is following:
(1) feed intake: mix arsenic or mix antimony silicon substrate material, resistivity is at 0.03ohm.cm and following;
(2) the extension first step: growth 3-5um thickness, the N type extension of resistivity 0.5-1.5 ohm.cm;
(3) second step of extension: growth 3-5um thickness, the N type extension of resistivity 8-12 ohm.cm;
(4) the 3rd step of extension: growth 38-46um thickness, the N type extension of resistivity 14-22 ohm.cm;
(5) the 4th step of extension, growth 5-8um thickness, the N type extension of resistivity 10-16 ohm.cm;
(6) oxidation: the oxide layer of growth 0.8-1.2um thickness;
(7) active area etching: the oxide layer that will do the position of device is corroded clean;
(8) high concentration boron P+ injects, and knot is dark: inject energy 40-80kev, dosage 8e14-1.5e15/cm
2, knot adopts 1100 ℃-1200 ℃ deeply, 80-150 minute N
2Add little O
2, volume ratio 0%-5.5%;
(9) phosphorus injects, and knot is dark: inject energy 80-130kev, dosage 1e12-2e12/cm
2Knot is dark to adopt 1100 ℃-1200 ℃, and 80-150 minute, N
2Add little O
2, volume ratio 0%-5.5%;
(10) gate oxidation: the about 850-1200 of oxidated layer thickness;
(11) polysilicon gate deposit and doping: polycrystalline deposition 4000-7500, adopt phosphorous diffusion to mix;
(12) P trap boron injects, and knot is dark: inject energy 40-80kev, dosage 2.9e13-3.9e13/cm
2, knot adopt deeply 1100 ℃-1200 ℃ 80-150 minute, N
2Add little O
2, volume ratio 0%-5.5%);
(13) arsenic of source electrode N+ injects, and knot is dark: inject energy 80-130kev, dosage 5e15-1.5e16/cm
2
Knot is dark to adopt 950 ℃-1000 ℃, and 150-250 minute, N
2Add little O
2, volume ratio 0%-5.5%;
(14) contact hole etching: adopt the silicon dioxide in the clean hole of dry etching, form the hole of back aluminium contact;
(15) evaporation of aluminum, corrosion aluminium: evaporation thickness is the metal level of 3-5um, forms surface electrode grid and source electrode;
(16) the attenuate back of the body steams: thinning back side is to 200-280um thickness, and back side evaporation 0.8-1.2um thickness is silver-colored.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016058277A1 (en) * | 2014-10-15 | 2016-04-21 | 无锡华润华晶微电子有限公司 | Shallow-trench semi-super-junction vdmos device and manufacturing method therefor |
| CN105869989A (en) * | 2015-01-21 | 2016-08-17 | 北大方正集团有限公司 | Power device manufacturing method and power device |
| CN106935483A (en) * | 2015-12-31 | 2017-07-07 | 无锡华润华晶微电子有限公司 | A kind of cleaning method of semiconductor chip |
| CN107170672A (en) * | 2017-05-18 | 2017-09-15 | 上海先进半导体制造股份有限公司 | VDMOS gate oxide growth method |
| CN109524471A (en) * | 2018-12-26 | 2019-03-26 | 无锡浩真微电子有限公司 | The epitaxial structure and manufacturing method of anti-radiation power MOSFET |
| CN113690320A (en) * | 2021-10-25 | 2021-11-23 | 陕西亚成微电子股份有限公司 | Vertical DMOSFET (bipolar diffused Metal oxide semiconductor field Effect transistor), preparation method thereof and BCD (Bipolar complementary Metal-oxide-semiconductor field Effect transistor) device |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016058277A1 (en) * | 2014-10-15 | 2016-04-21 | 无锡华润华晶微电子有限公司 | Shallow-trench semi-super-junction vdmos device and manufacturing method therefor |
| CN105869989A (en) * | 2015-01-21 | 2016-08-17 | 北大方正集团有限公司 | Power device manufacturing method and power device |
| CN105869989B (en) * | 2015-01-21 | 2019-04-05 | 北大方正集团有限公司 | The preparation method and power device of power device |
| CN106935483A (en) * | 2015-12-31 | 2017-07-07 | 无锡华润华晶微电子有限公司 | A kind of cleaning method of semiconductor chip |
| CN107170672A (en) * | 2017-05-18 | 2017-09-15 | 上海先进半导体制造股份有限公司 | VDMOS gate oxide growth method |
| CN109524471A (en) * | 2018-12-26 | 2019-03-26 | 无锡浩真微电子有限公司 | The epitaxial structure and manufacturing method of anti-radiation power MOSFET |
| CN113690320A (en) * | 2021-10-25 | 2021-11-23 | 陕西亚成微电子股份有限公司 | Vertical DMOSFET (bipolar diffused Metal oxide semiconductor field Effect transistor), preparation method thereof and BCD (Bipolar complementary Metal-oxide-semiconductor field Effect transistor) device |
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Application publication date: 20121003 |