CN109524471A - The epitaxial structure and manufacturing method of anti-radiation power MOSFET - Google Patents
The epitaxial structure and manufacturing method of anti-radiation power MOSFET Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 230000003471 anti-radiation Effects 0.000 title claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 230000003139 buffering effect Effects 0.000 claims abstract description 36
- 238000000407 epitaxy Methods 0.000 claims abstract description 28
- 238000007789 sealing Methods 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 17
- 239000012535 impurity Substances 0.000 claims description 14
- 239000000872 buffer Substances 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 22
- 230000005684 electric field Effects 0.000 abstract description 14
- 230000001939 inductive effect Effects 0.000 abstract description 11
- 230000005540 biological transmission Effects 0.000 abstract description 5
- 230000005855 radiation Effects 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 238000005457 optimization Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000001976 improved effect Effects 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
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- 230000003014 reinforcing effect Effects 0.000 description 1
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- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The invention discloses the epitaxial structures and manufacturing method of a kind of anti-radiation power MOSFET.The epitaxial structure includes: back sealing, silicon substrate, buffering epitaxial layer and secondary epitaxy layer, the back sealing is provided on the back side of the silicon substrate, the front of the silicon substrate is provided with the buffering epitaxial layer, is provided with the secondary epitaxy layer on the buffering epitaxial layer.It realizes that the peak electric field of the transmission range between epitaxial layer and silicon substrate is lower than the peak electric field of second breakdown, improves the second breakdown for inducing NPN pipe.
Description
Technical field
The present invention relates to the VDMOS product related fields that is suitable for space or aerospace applications, in particular to one
The epitaxial structure and manufacturing method of the anti-radiation power MOSFET of kind.
Background technique
The vdmos transistor of various voltage and current grades is high frequency switch power device selected to use, it is current they
It applies and controls and converted in application in the multiple power sources of space and aerospace system.In addition, applying in the outer space as communication is defended
Star, meteorological satellite, GPS(global positioning system) and Earthwatch satellite on, due to the switching speed of power MOSFET high, low
Conduction loss, small space hold and largely use.
To work the outer space MOS(metal-oxide semiconductor (MOS)) device particular/special requirement, be long-term reliability with
And for ionising radiation, high energy particle and other high endurances.The threshold voltage (Vth) of VDMOS power transistor, breakdown
Voltage (BVdss), leakage current (Idss), mutual conductance (gm) and conducting resistance (Rdson) are all influenced by ionising radiation, therefore, are fitted
Together in the power MOSFET of this application environment " radiation hardening (radiation should be carried out by designing and manufacturing technique
hardened)”。
Originally VDMOS device is used in space application, single event burnout becomes it in a large amount of heavy ion beam current environment
The major limitation that middle commercialization uses.Single event burnout (SEB) is absorbed in there are many research and is improved in heavy ion bombardment
The ability of lower VDMOS device.The study found that the charge " sheath " that a high energy ion generates in semiconductor along its path,
It is proportional to its linear energy transfer value (LET).
If the drain bias of VDMOS device is more than some values (or the electric field in device close to characteristic value), this
When, part or less than 1 micron diameter in the range of, electron-hole pair density increase, leading to current density is more than 104A/
cm2, hole can constantly drive below the surface and VDMOS device active layer of N-channel MOS FET, it is easy to generate one it is close
Or the pressure drop more than 0.7V, thus open in any VDMOS structure all parasitism existing for induce bipolar transistor.When inducing
Bipolar transistor is opened, and NPN transistor (for N ditch VDMOS) enters second breakdown, or is " snapback " mould of work
Formula.Once secondary-breakdown phenomenon is triggered, the entire energy of power supply can be gathered in the place that the operating mode starts on chip, with
Temperature will increase acutely afterwards, and the knot of device then can be short-circuit due to diffusing into for upper layer metal.It reduces and induces the unlatching of NPN pipe
Conventional method is the doping of p-well below increase source.Increase limiting doped with it for clamper inductive switch (UIS) implanted layer, this
The doping of layer is accessible to the interface (channel region) of silicon and silica, when this occurs, the threshold value of that position
Voltage can quickly increase, and can form " dead " MOSFET in that position when serious.Numerous studies, simulation and it is demonstrated experimentally that
If using double epitaxial layers and the transmission range electric field between epitaxial layer and substrate is adjusted to appropriate level, the secondary of NPN pipe is induced
Breakdown can improve.
Although the use of double epitaxial layers has improvement effect to the second breakdown for inducing NPN pipe, but " snapback " phenomenon is still
In the presence of.The defect of this method is the increase due to epitaxial layer and influences the Rdson of VDMOS.Therefore the technology solved is needed to ask
Topic is: seeking a compromise between second breakdown and opening feature, while needing to find a better method and reinforcing power
MOSFET element capability of resistance to radiation.
Summary of the invention
In order to solve problems in the prior art, the embodiment of the invention provides the epitaxy junctions of anti-radiation power MOSFET a kind of
Structure and manufacturing method.The technical solution is as follows:
In a first aspect, providing the epitaxial structure of anti-radiation power MOSFET a kind of, the epitaxial structure includes: back sealing, silicon
Substrate buffers epitaxial layer and secondary epitaxy layer, is provided with the back sealing on the back side of the silicon substrate, the silicon substrate is just
Face is provided with the buffering epitaxial layer, is provided with the secondary epitaxy layer on the buffering epitaxial layer.
Optionally, the dopant type of silicon substrate doping is As, the silicon substrate with a thickness of 150 ~ 800 μm, resistance
Rate is 0.001 ~ 0.01 Ω .cm.
Optionally, it is described buffering epitaxial layer doping impurity be As or P, it is described buffering epitaxial layer with a thickness of 5 ~ 30 μ
M, resistivity are 0.05 ~ 2.05 Ω .cm.
Optionally, the dopant type of secondary epitaxy layer doping is As or P, the secondary epitaxy layer with a thickness of 8 ~ 45
μm, resistivity is 0.15 ~ 9.15 Ω .cm.
Optionally, it is described back sealing with a thickness of 0.5 ~ 5.0 μm.
Second aspect provides a kind of manufacturing method of the epitaxial structure of anti-radiation power MOSFET, which comprises
POLY-Si and LTO back envelope is carried out at the back side of silicon substrate, forms the back sealing for protection；
It carries out being epitaxially-formed buffering epitaxial layer for the first time on the silicon substrate, carries out second on the buffering epitaxial layer
It is secondary to be epitaxially-formed secondary epitaxy layer.
Optionally, the method also includes:
The impurity As in the silicon substrate, the silicon substrate with a thickness of 150 ~ 800 μm, resistivity is 0.001 ~
0.01Ω.cm。
Optionally, the method also includes:
The impurity As or P in the buffering epitaxial layer, the buffering epitaxial layer with a thickness of 5 ~ 30 μm, resistivity is
0.05~2.05Ω.cm。
Optionally, the method also includes:
The impurity As or P in the secondary epitaxy layer, the secondary epitaxy layer with a thickness of 8 ~ 45 μm, resistivity 0.15
~9.15Ω.cm。
Optionally, it is described back sealing with a thickness of 0.5 ~ 5.0 μm.
Technical solution provided in an embodiment of the present invention has the benefit that
The epitaxial structure and manufacturing method that above scheme provides, realize the peak electric field of the transmission range between epitaxial layer and silicon substrate
Lower than the peak electric field (in actual implementation can be 5E5 V/cm) of second breakdown, improve the second breakdown for inducing NPN pipe.Pass through
In the case where conducting resistance meets the requirements, breakdown voltage is maximum, by optimization design buffer epitaxial layer thickness and concentration (
Buffer the impurity adulterated in epitaxial layer), allow to seek between second breakdown and opening feature a compromise, improves
The capability of resistance to radiation of MOSFET element.By the optimization design buffering thickness of epitaxial layer (closer to that layer of silicon substrate) and dense
It spends (increasing its doping), increases the breakdown voltage for inducing NPN pipe, high electric field occurs and heavy ion is generated caused by charge occurs and carried
Stream multiplication can minimize.Also can be lower by generating lower electric field " charge multiplication effect ", while less carrier quilt
It drives to bottom end, the chance for inducing npn bipolar transistor breakdown is also lower.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is the structural schematic diagram of the epitaxial structure of the anti-radiation power MOSFET provided in one embodiment of the invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Referring to FIG. 1, it illustrates the structural schematic diagram of the epitaxial structure of anti-radiation power MOSFET, as shown in Figure 1, institute
Stating epitaxial structure includes back sealing 1, silicon substrate 2, buffering epitaxial layer 3 and secondary epitaxy layer 4, is set on the back side of the silicon substrate 2
It is equipped with the back sealing 1, the front of the silicon substrate 2 is provided with the buffering epitaxial layer 3, is arranged on the buffering epitaxial layer 3
There is the secondary epitaxy layer 4.
The back side of silicon substrate 2 described in the present embodiment and front are respectively two sides opposite in silicon substrate 2, practical real
Now, not distinguishing which face is front, which face is the back side.
Wherein, the dopant type that the silicon substrate 2 adulterates is As, the silicon substrate 2 with a thickness of 150 ~ 800 μm, resistance
Rate is 0.001 ~ 0.01 Ω .cm.It is described back sealing 1 with a thickness of 0.5 ~ 5.0 μm.
The impurity that the buffering epitaxial layer 3 adulterates is As or P, the buffering epitaxial layer 3 with a thickness of 5 ~ 30 μm, resistance
Rate is 0.05 ~ 2.05 Ω .cm.In actual implementation, epitaxial layer 3 is too thick will increase conducting resistance for buffering, too thin to reduce breakdown potential
Pressure, therefore the present embodiment is buffered outer by the breakdown voltage maximum in the case where conducting resistance meets the requirements by optimization design
The thickness and concentration (namely impurity for adulterating in buffering epitaxial layer 3) for prolonging layer 3, allow to second breakdown and opening feature it
Between seek one compromise, improve the capability of resistance to radiation of MOSFET element.Optionally, the present embodiment only with resistivity be 0.05 ~
2.05 Ω .cm come for example, in actual implementation, being authenticated according to experiment, the resistivity for buffering epitaxial layer can be 1.68 Ω
.cm。
The dopant type that the secondary epitaxy layer 4 adulterates is As or P, the secondary epitaxy layer 4 with a thickness of 8 ~ 45 μm, electricity
Resistance rate is 0.15 ~ 9.15 Ω .cm.
Extension may be implemented by the design of double epitaxial layers namely buffering epitaxial layer 3 and secondary epitaxy layer 4 in the present embodiment
The peak electric field of transmission range between layer and silicon substrate 2 (can be 5E5 V/ lower than the peak electric field of second breakdown in actual implementation
Cm), improve the second breakdown for inducing NPN pipe.
In addition, by optimization design buffer epitaxial layer 3(closer to silicon substrate 2 that layer) thickness and concentration (increase
It is adulterated), increase the breakdown voltage for inducing NPN pipe, high electric field occurs and heavy ion generates carrier times caused by charge occurs
Increasing can minimize.Also can be lower by generating lower electric field " charge multiplication effect ", while less carrier is driven to
Bottom end, the chance for inducing npn bipolar transistor breakdown are also lower.
Above-mentioned is only that As or P comes for example, real to buffer the impurity adulterated in epitaxial layer 3 and secondary epitaxy layer 4
When border is realized, As and P can also be adulterated simultaneously, and buffering the impurity adulterated in epitaxial layer 3 and secondary epitaxy layer 4 can be identical
Or it is different, to this and without limitation.
In addition, the embodiment of the invention also provides a kind of for manufacturing the manufacturing method of epitaxial structure shown in FIG. 1, the party
Method includes:
First, POLY-Si and LTO back envelope is carried out at the back side of silicon substrate, forms the back sealing for protection.
Carry on the back sealing with a thickness of 0.5 ~ 5.0 μm.In addition, the present embodiment is lifted so that the material for carrying on the back sealing is POLY-Si and LTO
Example explanation can also be in actual implementation other materials, the present embodiment is to this and without limitation.
Second, it carries out being epitaxially-formed buffering epitaxial layer for the first time on the silicon substrate, in the buffering epitaxial layer
It is upper to be epitaxially-formed secondary epitaxy layer for the second time.
Optionally, during growth forms buffering epitaxial layer on a silicon substrate, As can be adulterated in buffering epitaxial layer
Perhaps P and then formation group are divided into the buffering epitaxial layer of silicon and As or silicon and the mixture of P, and with a thickness of 5 ~ 30 μm, resistivity is
0.05~2.05Ω.cm。
During forming secondary epitaxy layer on buffering epitaxial layer, As or P can be adulterated in secondary epitaxy layer, into
And formation group is divided into the secondary epitaxy layer of silicon and As or silicon and the mixture of P, and with a thickness of 8 ~ 45 μm, resistivity is 0.15 ~
9.15Ω.cm。
In addition, in actual implementation, can impurity As in a silicon substrate, form the mixture of silicon and As, also, described
Silicon substrate with a thickness of 150 ~ 800 μm, resistivity is 0.001 ~ 0.01 Ω .cm.
The epitaxial structure manufactured by the above-mentioned manufacture method realizes the peak electric field of the transmission range between epitaxial layer and silicon substrate
Lower than the peak electric field (in actual implementation can be 5E5 V/cm) of second breakdown, improve the second breakdown for inducing NPN pipe.
Those of ordinary skill in the art will appreciate that realizing that all or part of the steps of above-described embodiment can pass through hardware
It completes, relevant hardware can also be instructed to complete by program, the program can store in a kind of computer-readable
In storage medium, storage medium mentioned above can be read-only memory, disk or CD etc..
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of epitaxial structure of anti-radiation power MOSFET, which is characterized in that the epitaxial structure includes: back sealing (1), silicon
Substrate (2) buffers epitaxial layer (3) and secondary epitaxy layer (4), is provided with the back sealing on the back side of the silicon substrate (2)
(1), the front of the silicon substrate (2) is provided with the buffering epitaxial layer (3), is provided on the buffering epitaxial layer (3) described
Secondary epitaxy layer (4).
2. epitaxial structure according to claim 1, which is characterized in that the dopant type of silicon substrate (2) doping is As,
The silicon substrate (2) with a thickness of 150 ~ 800 μm, resistivity is 0.001 ~ 0.01 Ω .cm.
3. epitaxial structure according to claim 1, which is characterized in that the impurity of buffering epitaxial layer (3) doping is As
Or P, buffering epitaxial layer (3) with a thickness of 5 ~ 30 μm, resistivity is 0.05 ~ 2.05 Ω .cm.
4. epitaxial structure according to claim 1, which is characterized in that the dopant type of secondary epitaxy layer (4) doping
For As or P, the secondary epitaxy layer (4) with a thickness of 8 ~ 45 μm, resistivity is 0.15 ~ 9.15 Ω .cm.
5. epitaxial structure according to claim 1, which is characterized in that it is described back sealing (1) with a thickness of 0.5 ~ 5.0 μm.
6. a kind of manufacturing method of the epitaxial structure of anti-radiation power MOSFET, which is characterized in that the described method includes:
POLY-Si and LTO back envelope is carried out at the back side of silicon substrate, forms the back sealing for protection；
It carries out being epitaxially-formed buffering epitaxial layer for the first time on the silicon substrate, carries out second on the buffering epitaxial layer
It is secondary to be epitaxially-formed secondary epitaxy layer.
7. according to the method described in claim 6, it is characterized in that, the method also includes:
The impurity As in the silicon substrate, the silicon substrate with a thickness of 150 ~ 800 μm, resistivity is 0.001 ~
0.01Ω.cm。
8. according to the method described in claim 6, it is characterized in that, the method also includes:
The impurity As or P in the buffering epitaxial layer, the buffering epitaxial layer with a thickness of 5 ~ 30 μm, resistivity is
0.05~2.05Ω.cm。
9. according to the method described in claim 6, it is characterized in that, the method also includes:
The impurity As or P in the secondary epitaxy layer, the secondary epitaxy layer with a thickness of 8 ~ 45 μm, resistivity 0.15
~9.15Ω.cm。
10. according to the method described in claim 6, it is characterized in that, it is described back sealing with a thickness of 0.5 ~ 5.0 μm.
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