ES2103671A1 - Method of manufacturing VDMOS transistors. - Google Patents

Method of manufacturing VDMOS transistors.

Info

Publication number
ES2103671A1
ES2103671A1 ES09402670A ES9402670A ES2103671A1 ES 2103671 A1 ES2103671 A1 ES 2103671A1 ES 09402670 A ES09402670 A ES 09402670A ES 9402670 A ES9402670 A ES 9402670A ES 2103671 A1 ES2103671 A1 ES 2103671A1
Authority
ES
Spain
Prior art keywords
manufacturing
diffusion
vdmos
drain
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES09402670A
Other languages
Spanish (es)
Other versions
ES2103671B1 (en
Inventor
Garcia Juan Fernandez
Marti Josep Montserrat
Hernandez Miquel Vellvehi
Casas Enric Cabruja
Berenguer Esteve Farres
Palacios Jose Andres Rebollo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Standard Electrics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Standard Electrics SA filed Critical Alcatel Standard Electrics SA
Priority to ES9402670A priority Critical patent/ES2103671B1/en
Publication of ES2103671A1 publication Critical patent/ES2103671A1/en
Application granted granted Critical
Publication of ES2103671B1 publication Critical patent/ES2103671B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

Method of manufacturing VDMOS transistors. The basic steps are described of the process of manufacturing a low-voltage, low-conducting-resistance VDMOS power device. This electrical behaviour is achieved by a triple ion implantation for forming the source 108, drain 106 and short-circuit p+ diffusion 107 regions between the two, followed by the appropriate subsequent heat treatments. The diffusion of boron in the drain region 106 is carried out at a level such that, by maintaining the greatest possible resistivity for it, the breakdown voltage of the device does not substantially decrease. Furthermore, with the object of preventing the activation of the parasitic bipolar transistor inherent to the structure of the VDMOS transistor, the p+ diffusion 107 between source 108 and drain 106 is the surface type, which does not degrade the breakdown voltage of the device for the same thickness of epitaxial layer 102, so that the device's resistance is not altered.
ES9402670A 1994-12-29 1994-12-29 MANUFACTURE METHOD OF VDMOS TRANSISTORS. Expired - Lifetime ES2103671B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES9402670A ES2103671B1 (en) 1994-12-29 1994-12-29 MANUFACTURE METHOD OF VDMOS TRANSISTORS.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES9402670A ES2103671B1 (en) 1994-12-29 1994-12-29 MANUFACTURE METHOD OF VDMOS TRANSISTORS.

Publications (2)

Publication Number Publication Date
ES2103671A1 true ES2103671A1 (en) 1997-09-16
ES2103671B1 ES2103671B1 (en) 1998-05-01

Family

ID=8288420

Family Applications (1)

Application Number Title Priority Date Filing Date
ES9402670A Expired - Lifetime ES2103671B1 (en) 1994-12-29 1994-12-29 MANUFACTURE METHOD OF VDMOS TRANSISTORS.

Country Status (1)

Country Link
ES (1) ES2103671B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102709191A (en) * 2012-06-07 2012-10-03 无锡市晶源微电子有限公司 Process for manufacturing series of intermediate-voltage N-type vertical conduction double-diffused metal oxide semiconductor transistors by using composite epitaxy

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4055444A (en) * 1976-01-12 1977-10-25 Texas Instruments Incorporated Method of making N-channel MOS integrated circuits
US4417385A (en) * 1982-08-09 1983-11-29 General Electric Company Processes for manufacturing insulated-gate semiconductor devices with integral shorts
EP0251506A1 (en) * 1986-06-05 1988-01-07 SILICONIX Incorporated Process for producing a double diffused MOS transistor structure
EP0407704A1 (en) * 1989-05-15 1991-01-16 Kabushiki Kaisha Toshiba Diffusion of implanted dopant and polysilicon oxidation processes for VDMOS

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4055444A (en) * 1976-01-12 1977-10-25 Texas Instruments Incorporated Method of making N-channel MOS integrated circuits
US4417385A (en) * 1982-08-09 1983-11-29 General Electric Company Processes for manufacturing insulated-gate semiconductor devices with integral shorts
EP0251506A1 (en) * 1986-06-05 1988-01-07 SILICONIX Incorporated Process for producing a double diffused MOS transistor structure
EP0407704A1 (en) * 1989-05-15 1991-01-16 Kabushiki Kaisha Toshiba Diffusion of implanted dopant and polysilicon oxidation processes for VDMOS

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102709191A (en) * 2012-06-07 2012-10-03 无锡市晶源微电子有限公司 Process for manufacturing series of intermediate-voltage N-type vertical conduction double-diffused metal oxide semiconductor transistors by using composite epitaxy

Also Published As

Publication number Publication date
ES2103671B1 (en) 1998-05-01

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