CN206471335U - Super-junction semiconductor device with terminal protection area - Google Patents
Super-junction semiconductor device with terminal protection area Download PDFInfo
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- CN206471335U CN206471335U CN201720132638.XU CN201720132638U CN206471335U CN 206471335 U CN206471335 U CN 206471335U CN 201720132638 U CN201720132638 U CN 201720132638U CN 206471335 U CN206471335 U CN 206471335U
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Abstract
The utility model is related to a kind of super-junction semiconductor device with terminal protection area, and device area, straight flange terminal protection area and turning terminal protection area are included in top plan view.In straight flange terminal protection area, the super-junction structure being made up of first the second post of conduction type and second the second post of conduction type is extended in the first conduction type drift layer from semiconductor surface through-thickness, and alternately regular array.In turning terminal protection area, some groups by a pair or several are mutually perpendicular to non-intersect arrangement to the super-junction structure group that the post of the first conduction type the 3rd and the post of the second conduction type the 3rd are constituted.The different posts of the second conduction type the 3rd is not connected electrically from each other, and the post of the second conduction type the 3rd is not connected electrically with straight flange terminal protection area the second post of the second conduction type.Device of the present utility model has terminal size small, high pressure, and the design of terminal turning protection zone is simple, easily realizes charge balance.
Description
Technical field
The utility model is related to a kind of super-junction semiconductor device, especially a kind of superjunction semiconductor with terminal protection area
Device.
Background technology
In mesohigh power semiconductor field, super-junction structure（Super Junction）It has been be widely adopted that, it is right
Than the semiconductor devices of conventional power, it is pressure-resistant with turning on that the semiconductor devices with super-junction structure can obtain more excellent device
The tradeoff of resistance.By taking 600V super-junction MOSFET devices as an example, the super node MOSFET device of identical voltage specification and chip area
The conducting resistance of part is only 20~30% or so of conventional VDMOS.Super-junction semiconductor device generally comprises offer current flow paths
Active area and ensure to be provided with super-junction structure, superjunction in the pressure-resistant terminal protection area of device, active area and terminal protection area
By being arranged in drift semiconductor area alternately, the P-type semiconductor post and N-type semiconductor post of adjacent arrangement are constituted structure, p-type half
Conductor pin keeps charge balance with N-type semiconductor post, therefore, in the pressure-resistant work of device, P-type semiconductor post and N-type semiconductor
Depletion layer produced by post provides necessary voltage resistance layer for device.
But in the pressure-resistant design in terminal protection area of super-junction semiconductor device, there is also many problems.With N-channel superjunction
Exemplified by MOSFET, common super-junction semiconductor device terminal structure is designed as shown in Figure 11, Figure 12.Cell region wherein,
Due to the P Zhu YuPXing Ti areas connection in drift layer, PXing Ti areas are connected with device source electrode and keep equal potentials；N posts are with partly leading
Body substrate layer has identical conduction type and correspondence is connected, and semiconductor substrate layer is connected with device drain and keeps equal electricity
Position.Therefore, the potential difference between the same device drain-source electrode of potential difference between the P posts in cell region and N posts is equal.And device
In part terminal protection area, because P posts are not connected all with PXing Ti areas, the P posts that this part Wei YuPXing Ti areas are connected are floating
Install, therefore the potential difference between floating P posts and N posts is less than the potential difference between device drain-source electrode.When device is pressure-resistant
When, the super-junction structure in cell region can cmpletely exhaust, and the part P posts and N posts in terminal protection area can not be complete
Exhaust, so as to limit the voltage endurance capability in terminal protection area.
General solution is, by adjusting terminal area N post width, and to increase the P post numbers of terminal area suspension at present
Measure to ensure that device terminal is pressure-resistant, but so can serious waste device area, increase device cost.Patent application CN
Although 102623504 A are by improving Terminal Design structure, optimize by the way of terminal whole P Zhu YuPXing Ti areas are connected
The voltage endurance capability of device terminal, reduces terminal size.But in device terminal corner region, the structure has many techniques and design bureau
Limit, such as, in terminal corner region, the width of P posts and N posts must have one or more kinds of in the in-plane direction using width
Gradual change, but in the P/N posts of width gradual change charge balance can be caused to be difficult to realize, meanwhile, the semiconductor column of width gradual change is in technique
On also have very big limitation.Therefore, the method for the patent can not ensure the pressure-resistant optimization of terminal corner region in actual product.
In addition, when actual super-junction semiconductor device is manufactured, can typically use multilayer epitaxial, injection, Annealing Scheme or depth
The schemes such as etching groove extension filling.In multiple extension, injection, Annealing Scheme, the annealing knot effect of extension in itself causes P
Post can be presented that bottom is wide, the narrow pattern in top.In deep plough groove etched extension padding scheme, due to etching technics and
To ensure filling effect, general deep trench can be etched into the wide pattern in narrow base, top, cause the P posts ultimately formed to present
The effect that lower bottom part is narrow, top is wide.This pattern will also result in product partial charge imbalance, and influence device terminal region is pressure-resistant
Efficiency.
Utility model content
The purpose of this utility model is to overcome the deficiencies in the prior art to have the super of terminal protection area there is provided a kind of
Junction-semiconductor device, it has voltage endurance good, and terminal protection area area is small, design it is simple and with existing super-junction semiconductor device
The characteristics of manufacturing process is mutually compatible.
The technical scheme provided according to the utility model, the super-junction semiconductor device with terminal protection area, it is special
Levying is：Include device area, straight flange terminal protection area and turning terminal protection area in top plan view, device area is whole by straight flange
End protection zone and turning terminal protection area are surrounded, each turning terminal protection area and two orthogonal straight flange terminal protections
Area is adjacent；Include the first conductivity type substrate and the first conduction type drift layer in the cross-direction, in the drift of the first conduction type
Move in layer and super-junction structure is set；
Super-junction structure is replaced by first the first post of conduction type and second the first post of conduction type in the device area
Arrangement is formed, and first the first post of conduction type and second the first post of conduction type are extended by semiconductor substrate surface through-thickness
To the first conduction type drift layer；It is conductive provided with multiple discontinuous second in the semiconductor substrate surface of the device area
The first body of type area, second the first post of conduction type and corresponding the first body of second conduction type area electrical communication；
Super-junction structure is by first the second post of conduction type and the second conduction type second in the straight flange terminal protection area
Post is arranged alternately to be formed, and first the second post of conduction type and second the second post of conduction type are by semiconductor substrate surface along thickness side
To extending in the first conduction type drift layer；It is electrical with second the first body of conduction type area having close to device area side
Second the second body of conduction type area of connection, second conduction type the second post one end is overlapped with second the second body of conduction type area,
And second the second post of conduction type extends to the direction away from second the second body of conduction type area；
Super-junction structure is by the post of the first conduction type the 3rd and the second conduction type the 3rd in the turning terminal protection area
Post is arranged alternately to be formed, and the post of the first conduction type the 3rd and the post of the second conduction type the 3rd are by semiconductor substrate surface along thickness side
To extending in the first conduction type drift layer；In top plan view, some groups by a pair or several to the first conduction type the 3rd
The super-junction structure group that post and the post of the second conduction type the 3rd are constituted is mutually perpendicular to, the orthogonal post of second conduction type the 3rd
There is certain distance between one end and adjacent one end of the adjacent and vertical post of the second conduction type the 3rd；
The different posts of the second conduction type the 3rd is not connected electrically each other, and the post of the second conduction type the 3rd with it is straight
Side terminal protection area the second post of the second conduction type is not connected electrically；
The overlapping one end of the post of second conduction type second and second the second body of conduction type area and adjacent device regions
Second the first post of conduction type side there is distance from top W10, W10 value to be less than or equal to 1/2 × W3, W3 is first conductive
The top width of the post of type first；
One end of the orthogonal post of second conduction type the 3rd and the adjacent and vertical post of the second conduction type the 3rd
Distance from top is W11, and W11 values are between 1/2 × W9 and 1/2 × W9-（W7-W8）Between；Wherein, W7 is the second conduction type the
The top width of three posts, W8 is the bottom width of the post of the second conduction type the 3rd, and W9 is the top of the post of the first conduction type the 3rd
Width.
Further, the first column top of the second conduction type width W1 is identical, and bottom width W2 is identical；Described first
The first column top of conduction type width W3 is identical.
Further, the second column top of the second conduction type width W4 is identical, and bottom width W5 is identical；Described first
The second column top of conduction type width W6 is identical.
Further, the column top width W7 of the second conduction type the 3rd is identical, and bottom width W8 is identical；Described first
The column top width W9 of conduction type the 3rd is identical.
Further, the first conduction type source region is set in the first body of the second conduction type area；Partly led described
Structure base board surface is provided with the gate electrode by gate oxide and the encirclement of the first insulating medium layer, is covered on the first insulating medium layer
Source metal, source metal and second conduction type the first body area and the first conduction type source region Ohmic contact；In the straight flange
Terminal protection area and turning terminal protection area surface cover the second insulating medium layer；Cause the back side of type substrates described first
Drain metal, drain metal and the first conductivity type substrate Ohmic contact are set, and drain metal spreads all over device area, straight flange terminal
Protection zone and turning terminal protection area.
Further, second the second post of conduction type and second the second body of conduction type in the straight flange terminal protection area
The part that area is not overlapped is not less than second the first post of conduction type to away from the length on second conduction type the second body area direction
From semiconductor material surface to the depth extended in vivo.
Further, the length of side in the turning terminal protection area is not less than second the first post of conductivity type columns from semiconductor material
Expect surface to the depth extended in vivo.
The utility model has advantages below：
（1）Terminal size is small, high pressure；
（2）The design of terminal turning protection zone is simple, easily realizes charge balance；
（3）Device terminal protection structure is designed and manufacturing step is simple, is adapted to volume production.
Brief description of the drawings
Fig. 1 is the plan view from above of the super-junction semiconductor device described in the utility model with terminal protection area.
Fig. 2 is Fig. 1 A-A ' sectional views.
Fig. 3 is Fig. 1 B-B ' sectional views.
Fig. 4 is Fig. 1 C-C ' sectional views.
Fig. 5 is the sectional view of semiconductor substrate.
Fig. 6 is the sectional view after selective etch mask.
Fig. 7 is the sectional view after etching deep trench.
Fig. 8 is that monocrystalline silicon epitaxy is filled and removes the sectional view after hard mask.
Fig. 9 is the sectional view to be formed after device trench gate structure.
Figure 10 is the sectional view to be formed after device body area and source region.
Figure 11 is conventional super node MOSFET terminal protection area top view.
Figure 12 is the sectional view in conventional super node MOSFET terminal protection area.
Description of reference numerals：Device area 01, straight flange terminal protection area 02, turning terminal protection area 03, N-type drift layer
001st, N+ substrates 002, the first p-type post 11, the first N-type post 12, the first PXing Ti areas 13, gate oxide 14, gate electrode 15, N+ types
Source region 16, the first insulating medium layer 17, source metal 18, drain metal 19, the second p-type post 21, the second N-type post 22, the second p-type
Body area 23, the second insulating medium layer 24, the 3rd p-type post 31, the 3rd N-type post 32, hard mask layer 41, deep trench 42.
Embodiment
With reference to specific accompanying drawing, the utility model is described in further detail.
By taking N type groove grid super node MOSFET devices as an example, to the superjunction half in specific terminal protection area described in the utility model
Conductor device and its manufacture method are illustrated.
As shown in figure 1, be the plan view from above of the super-junction semiconductor device described in the utility model with terminal protection area,
The super-junction semiconductor device includes device area 01, straight flange terminal protection area 02, wherein turning terminal protection area 03, device area
01 is surrounded by four straight flange terminal protection areas 02 and four turnings terminal protection area 03, each turning terminal protection area 03 and two
Orthogonal straight flange terminal protection area 02 is adjacent.
In the cross-wise direction of super-junction semiconductor device, as shown in figs. 2 to 4, the superjunction with terminal protection area half
The semi-conducting material of conductor device includes N+ substrates 002 and N-type drift layer 001.
As shown in Fig. 2 in the device area 01, the superjunction knot being made up of the first N-type post 12 and the first p-type post 11
Structure is extended in N-type drift layer 001 from semiconductor material surface through-thickness, and alternately regular array.First p-type post 11
Top has same widths W1, and bottom has same widths W2；First N-type post 12 has same top width W3.In device region
Multiple discontinuous first PXing Ti areas 13 are provided with domain 01, the first p-type post 11 electrically connects with corresponding first PXing Ti areas 13
It is logical.N+ types source region 16 is set in the first PXing Ti areas 13.It is provided with semiconductor material surface by gate oxide 14 and
One insulating medium layer 17 surround gate electrode 15, on the first insulating medium layer 17 cover source metal 18, source metal 18 with
First PXing Ti areas 13 and the Ohmic contact of N+ types source region 16.
As shown in Figure 2 to 4, in the straight flange terminal protection area 02, by the second N-type post 22 and the institute of the second p-type post 21
The super-junction structure of composition is extended in N-type drift layer 001 from semiconductor surface through-thickness, and alternately regular array.The
The top of two p-type post 21 has same widths W4, and bottom has same widths W5；Second N-type post 22 has same top width W6.
There is the second PXing Ti areas 23 with the electrical communication of the first PXing Ti areas 13 in device area 01 close to the side of device area 01,
Second PXing Ti areas 23 can be same manufacture floor or different manufacture floor from the first PXing Ti areas 13 of device area 01.
The one end of second p-type post 21 is overlapped with the second PXing Ti areas 23, and is extended to the direction away from the second PXing Ti areas 23.Second p-type post
21 and second the overlapping one end in PXing Ti areas 23 there is distance from top with the side of the first p-type post 11 in adjacent device area 01
W10, W10 value are less than or equal to 1/2 × W3.
In the turning terminal protection area 03, the super-junction structure being made up of the 3rd N-type post 32 and the 3rd p-type post 31 from
Semiconductor surface through-thickness is extended in N-type drift layer 001, and alternately regular array, wherein the top of the 3rd p-type post 31
With same widths W7, bottom has same widths W8；3rd N-type post 32 has same top width W9.In top plan view,
Some groups by a pair or several are mutually perpendicular to non-intersect arrangement to the super-junction structure group that the 3rd N-type post 32 and the 3rd p-type post 31 are constituted.
One end of orthogonal 3rd p-type post 31 is W11 with the distance from top of the 3rd adjacent and vertical p-type post 31, and W11 values are situated between
In 1/2 × W9 and 1/2 × W9-（W7-W8）Between.Superjunction devices P posts usually using the manufacture of deep trench extension filling mode are in
It is existing wide at the top and narrow at the bottom, i.e. W7-W8 be on the occasion of；Using multiple extension filling mode make superjunction devices P posts easily present it is upper it is narrow under
Width, i.e. W7-W8 are negative value.The 3rd different p-type posts 31 is not connected electrically from each other, and the 3rd p-type post 31 and straight flange are whole
The second p-type post 21 in the protection zone 02 of end is not connected electrically.
In the straight flange terminal protection area 02 and the surface of turning terminal protection area 03 typically the second insulating medium layer 24 of covering,
Second insulating medium layer 24 can be same manufacture layer or different systems from the first insulating medium layer 17 of device area 01
Make layer.Drain metal 19, drain metal 19 and the Ohmic contact of N+ substrates 002, drain metal 19 are set at the back side of N+ substrates 002
Spread all over device area 01, straight flange terminal protection area 02 and turning terminal protection area 03.In addition it is general in straight flange terminal protection area 02
The conventional structures such as ring are drawn and end with field plate, grid is additionally provided with away from device area 01 in turning terminal protection area 03, by
In not being explanation emphasis of the present utility model, thus it is not shown in embodiment and relevant drawings.
In super-junction semiconductor device described in the utility model, the second p-type post 21 in straight flange terminal protection area 02 and
The part that two PXing Ti areas 13 are not overlapped is to the length away from the extension of the direction of the second PXing Ti areas 13 not less than the first p-type post 11 from partly
Conductor material surface is to the depth extended in vivo.
In super-junction semiconductor device described in the utility model, the length of side in turning terminal protection area 03 is not less than the first p-type
Post 11 is from semiconductor material surface to the depth extended in vivo.
On the section of super-junction semiconductor device described in the utility model, the active area includes plane grid-type device architecture
With trench gate device architecture.
Using the super node MOSFET product of the present embodiment, because terminal P posts can fully exhaust, terminal protection area size
What can be done is smaller.In addition, in the utility model turning terminal protection area design, make device terminal corner region P/N posts consume
To the greatest extent more fully, speed relative equilibrium is exhausted in all directions, device corner design is simpler, pressure-resistant more efficient.
As shown in Fig. 5~Figure 10, the N-type trench gate mosfet device of above-described embodiment can be obtained by following processing step
Arrive, specifically, manufacture method comprises the following steps：
A, as shown in Figure 5 there is provided the N-type semiconductor substrate with two opposing main faces, the N-type semiconductor substrate includes
N-type drift region 001 and N+ types substrate layer 002；
B, the upper surface deposit hard mask layer 41 in the semiconductor substrate, the material of hard mask layer 41 must drift about with N-type
The semi-conducting material in area 001 has high etching selection ratio；Hard mask layer 41 is optionally sheltered and etched, multiple grooves is formed and carves
The hard mask window of erosion；In device area 01, each A/F is W1, and spacing is W3；In straight flange terminal protection area 02, often
The width of individual opening is W4, and spacing is W6；In turning terminal protection area 03, the width being each open is W7, and spacing is W9；Formed
Section after hard mask opening is as shown in Figure 6；
C, by above-mentioned hard mask window, etch multiple deep trench 42 on the surface using anisotropic etching method,
The deep trench 42 extends vertically downward in N-type drift region 001 from the upper surface of semiconductor substrate；In device area 01, often
The individual top width of deep trench 42 is W1, and bottom width is W2；In straight flange terminal protection area 02, each top width of deep trench 42 is
W4, bottom width is W5；In turning terminal protection area 03, each top width of deep trench 42 is W7, and bottom width is W8；Formed
Section after deep trench 42 is as shown in Figure 7；
D, the upper surface deposit p-type epitaxial layer in the semiconductor substrate, the p-type epitaxial layer are filled in above-mentioned deep trench
In 42；It is polished and planarizes, and remove hard mask layer 41, forms the first p-type post 11, the second p-type post 21, the 3rd p-type post
31.The N-type semiconductor post that P-type semiconductor post in N-type drift region 001 is formed after being spaced with N-type drift layer collectively forms super
Junction structure.By selecting the impurity concentration of suitable p-type epitaxial layer, super-junction structure charge balance can be reached, it is ensured that period is resistance to
Voltage levels.The section formed after super-junction structure is as shown in Figure 8；
E, as shown in figure 9, above-mentioned semiconductor substrate upper surface using etching, oxidation, chemical vapor deposition, photoetching, quarter
The conventional semiconductor process such as erosion, form gate oxide 14 and gate electrode 15；
F, using conventional semiconductor process such as photoetching, injection, knots, the first PXing Ti areas 13 formed in device area 01
With the second PXing Ti areas 23 in straight flange terminal protection area 01；The second PXing Ti areas 23 and the second p-type in straight flange terminal protection area 02
Post 22 has overlapping；
Afterwards N+ types source region 16 is formed in the first PXing Ti areas 13 of device area 01.Can also be in straight flange terminal protection
The cut-off region of device is formed in area 02 and turning terminal protection area 03.The section formed after N+ types source region 16 is as shown in Figure 10；
G, the first insulating medium layer 17 and straight flange in semiconductor substrate deposits insulating medium layer, formation device area 01
The second insulating medium layer 24 in terminal protection area 02 and turning terminal protection area 03.Wherein the first insulating medium layer 17 and second
Insulating medium layer 24 can be same manufacture layer or different manufacture layers；
By conventional semiconductor process such as photoetching, etching, evaporation sputterings, the first PXing Ti areas with device area 01 are formed
The source metal 18 of the Ohmic contact of 13 and N+ source electrodes 16 and the drain metal 19 with the Ohmic contact of N+ types substrate layer 002.
The material of above-mentioned hard mask layer 41 includes LPTEOS, silica, silicon nitride etc..
In above-mentioned steps f, the first PXing Ti areas 13 and the second PXing Ti areas 23 can be same manufacture floor or difference
Manufacture layer is formed.
The manufacture method of the present embodiment and existing super node MOSFET manufacture method are completely compatible, do not increase extra technique step
Rapid and manufacturing cost.
Claims (7)
1. a kind of super-junction semiconductor device with terminal protection area, it is characterized in that：Include device area in top plan view
（01）, straight flange terminal protection area（02）With turning terminal protection area（03）, device area（01）By straight flange terminal protection area（02）
With turning terminal protection area（03）Surrounded, each turning terminal protection area（03）With two orthogonal straight flange terminal protections
Area（02）It is adjacent；Include the first conductivity type substrate and the first conduction type drift layer in the cross-direction, in the first conductive-type
Super-junction structure is set in type drift layer；
In the device area（01）Middle super-junction structure is replaced by first the first post of conduction type and second the first post of conduction type
Arrangement is formed, and first the first post of conduction type and second the first post of conduction type are extended by semiconductor substrate surface through-thickness
To the first conduction type drift layer；In the device area（01）Semiconductor substrate surface be provided with multiple discontinuous second
The first body of conduction type area, second the first post of conduction type and corresponding the first body of second conduction type area electrical communication；
In the straight flange terminal protection area（02）Middle super-junction structure is by first the second post of conduction type and the second conduction type second
Post is arranged alternately to be formed, and first the second post of conduction type and second the second post of conduction type are by semiconductor substrate surface along thickness side
To extending in the first conduction type drift layer；Close to device area（01）Side has and second the first body of conduction type area
Handed over second the second body of conduction type area second the second body of conduction type area of electrical communication, second conduction type the second post one end
Fold, and second the second post of conduction type extends to the direction away from second the second body of conduction type area；
In the turning terminal protection area（03）Middle super-junction structure is by the post of the first conduction type the 3rd and the second conduction type the 3rd
Post is arranged alternately to be formed, and the post of the first conduction type the 3rd and the post of the second conduction type the 3rd are by semiconductor substrate surface along thickness side
To extending in the first conduction type drift layer；In top plan view, some groups by a pair or several to the first conduction type the 3rd
The super-junction structure group that post and the post of the second conduction type the 3rd are constituted is mutually perpendicular to, the orthogonal post of second conduction type the 3rd
There is certain distance between one end and adjacent one end of the adjacent and vertical post of the second conduction type the 3rd；
The different posts of the second conduction type the 3rd is not connected electrically each other, and the post of the second conduction type the 3rd and straight flange are whole
End protection zone the second post of the second conduction type is not connected electrically；
The of the overlapping one end in the post of second conduction type second and second the second body of conduction type area and adjacent device regions
There is distance from top W10, W10 value to be less than or equal to 1/2 × W3 for two the first post of conduction type sides, and W3 is the first conduction type
The top width of first post；
One end of the orthogonal post of second conduction type the 3rd and the top of the adjacent and vertical post of the second conduction type the 3rd
Distance is W11, and W11 values are between 1/2 × W9 and 1/2 × W9-（W7-W8）Between；Wherein, W7 is the post of the second conduction type the 3rd
Top width, W8 be the post of the second conduction type the 3rd bottom width, W9 be the post of the first conduction type the 3rd top width.
2. there is the super-junction semiconductor device in terminal protection area as claimed in claim 1, it is characterized in that：Second conductive-type
The first column top of type width W1 is identical, and bottom width W2 is identical；The first column top of first conduction type width W3 is identical.
3. there is the super-junction semiconductor device in terminal protection area as claimed in claim 2, it is characterized in that：Second conductive-type
The second column top of type width W4 is identical, and bottom width W5 is identical；The second column top of first conduction type width W6 is identical.
4. there is the super-junction semiconductor device in terminal protection area as claimed in claim 1, it is characterized in that：Second conductive-type
The column top width W7 of type the 3rd is identical, and bottom width W8 is identical；The column top width W9 of first conduction type the 3rd is identical.
5. there is the super-junction semiconductor device in terminal protection area as claimed in claim 1, it is characterized in that：It is conductive described second
First conduction type source region is set in the first body of type area；It is provided with the semiconductor substrate surface by gate oxide and first
The gate electrode that insulating medium layer is surrounded, covers source metal, source metal and the second conduction type on the first insulating medium layer
First body area and the first conduction type source region Ohmic contact；In the straight flange terminal protection area（02）With turning terminal protection area
（03）Surface covers the second insulating medium layer；The back side for causing type substrates described first sets drain metal, drain metal
With the first conductivity type substrate Ohmic contact, drain metal spreads all over device area（01）, straight flange terminal protection area（02）And turning
Terminal protection area（03）.
6. there is the super-junction semiconductor device in terminal protection area as claimed in claim 1, it is characterized in that：The straight flange terminal is protected
The part that second the second post of conduction type and second the second body of conduction type area in shield area are not overlapped is to away from the second conductive-type
Length on type the second body area direction is not less than second the first post of conduction type from semiconductor material surface to the depth extended in vivo
Degree.
7. there is the super-junction semiconductor device in terminal protection area as claimed in claim 1, it is characterized in that：The turning terminal is protected
The length of side for protecting area is not less than second the first post of conductivity type columns from semiconductor material surface to the depth extended in vivo.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720132638.XU CN206471335U (en) | 2017-02-14 | 2017-02-14 | Super-junction semiconductor device with terminal protection area |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720132638.XU CN206471335U (en) | 2017-02-14 | 2017-02-14 | Super-junction semiconductor device with terminal protection area |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206471335U true CN206471335U (en) | 2017-09-05 |
Family
ID=59708826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720132638.XU Withdrawn - After Issue CN206471335U (en) | 2017-02-14 | 2017-02-14 | Super-junction semiconductor device with terminal protection area |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206471335U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106711191A (en) * | 2017-02-14 | 2017-05-24 | 无锡新洁能股份有限公司 | Super junction semiconductor device with terminal protection zone and manufacturing method thereof |
| CN115602709A (en) * | 2022-10-24 | 2023-01-13 | 上海功成半导体科技有限公司（Cn） | Super junction device terminal protection layout structure |
-
2017
- 2017-02-14 CN CN201720132638.XU patent/CN206471335U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106711191A (en) * | 2017-02-14 | 2017-05-24 | 无锡新洁能股份有限公司 | Super junction semiconductor device with terminal protection zone and manufacturing method thereof |
| CN115602709A (en) * | 2022-10-24 | 2023-01-13 | 上海功成半导体科技有限公司（Cn） | Super junction device terminal protection layout structure |
| CN115602709B (en) * | 2022-10-24 | 2023-12-19 | 上海功成半导体科技有限公司 | Territory structure for protecting super junction device terminal |
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