CN209461470U - MOSFET terminal structure - Google Patents
MOSFET terminal structure Download PDFInfo
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- CN209461470U CN209461470U CN201920234661.9U CN201920234661U CN209461470U CN 209461470 U CN209461470 U CN 209461470U CN 201920234661 U CN201920234661 U CN 201920234661U CN 209461470 U CN209461470 U CN 209461470U
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Abstract
The utility model provides a kind of MOSFET terminal structure, and MOSFET terminal structure includes: the substrate of the first conduction type；The epitaxial layer of first conduction type；First source polysilicon；First medium layer；Second source polysilicon；Second dielectric layer, the thickness of second dielectric layer are less than the thickness of first medium layer；Gate polysilicon layer；Gate oxide；Dielectric isolation layer；First body area of the second conduction type；The source region of first conduction type.The MOSFET terminal structure of the utility model can make the breakdown voltage of termination environment higher than the breakdown voltage of active area, so that effective protection MOSFET terminal structure, improves the performance of MOSFET terminal structure；The concentration of the drift layer of active area can be improved, to optimize the conducting resistance of MOSFET terminal structure than relatively thin in the thickness of the second dielectric layer of the side wall and bottom of second groove in active area in the MOSFET terminal structure of the utility model.
Description
Technical field
The utility model belongs to IC design and manufacturing technology field, more particularly to a kind of MOSFET terminal knot
Structure.
Background technique
In the design of power semiconductor, the design in terminal protection area is extremely important.The design of active area determines function
The characteristics such as the resistance capacitance of rate semiconductor devices and breakdown voltage, but it is limited to validity and the face of terminal protection design
Product.
Since the performance of deep groove device is better than conventional groove device, deep groove device is occupied in power semiconductor
Ratio is increasing.In the existing MOSFET terminal part with deep trench in active area the thickness of dielectric layers of zanjon groove sidewall with
The thickness of the dielectric layer of zanjon groove sidewall in termination environment, but the pressure resistance of above-mentioned MOSFET terminal part termination environment is lower than active area
Pressure resistance, the whole pressure resistance of the MOSFET terminal part is limited, so that the reliability of the MOSFET terminal part is lower；
In order to improve the whole pressure resistance of the MOSFET terminal part, need to increase the thickness of the dielectric layer of zanjon groove sidewall in active area
And in termination environment the dielectric layer of zanjon groove sidewall thickness, and the thickness of the dielectric layer of zanjon groove sidewall is too thick in active area to lead
Cause the conducting resistance of the MOSFET terminal part higher, to influence the performance of the MOSFET terminal part.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of MOSFET terminal knots
Structure, for solving in MOSFET terminal part in the prior art in active area in the thickness of dielectric layers and termination environment of zanjon groove sidewall
The whole pressure resistance of MOSFET terminal part caused by the thickness of the dielectric layer of zanjon groove sidewall, reliability be lower and conducting resistance
The problems such as higher.
In order to achieve the above objects and other related objects, the utility model provides a kind of MOSFET terminal structure, described
MOSFET terminal structure includes:
The substrate of first conduction type；
The epitaxial layer of first conduction type, positioned at the upper surface of the substrate of first conduction type；Described first is conductive
The substrate of the epitaxial layer of type and first conduction type includes the active area being transversely distributed and termination environment；
First source polysilicon in the epitaxial layer of first conduction type, and is located in the termination environment；
First medium layer, between first source polysilicon and the epitaxial layer of first conduction type；
Second source polysilicon in the epitaxial layer of first conduction type, and is located in the active area；
Second dielectric layer, between second source polysilicon and the epitaxial layer of first conduction type, institute
The thickness for stating second dielectric layer is less than the thickness of the first medium layer；
Gate polysilicon layer in the epitaxial layer of first conduction type, and is located at second source polysilicon
The top of layer；
Gate oxide, between second source polysilicon and the epitaxial layer of first conduction type；
Dielectric isolation layer in the epitaxial layer of first conduction type, and is located at the gate polysilicon layer and institute
It states between the second source polysilicon；
First body area of the second conduction type, positioned at the periphery of the gate oxide；
The source region of first conduction type positioned at the periphery of the gate oxide, and is located at the of second conduction type
Above integrated area.
Optionally, the thickness of the gate oxide is less than the thickness of the first medium layer.
Optionally, first conduction type includes N-type, and second conduction type includes p-type.
Optionally, first conduction type includes p-type, and second conduction type includes N-type.
Optionally, the MOSFET terminal structure further include:
Gate electrode is connected with the gate polysilicon layer；
Source electrode, the first body area, first source polysilicon and described second with second conduction type
Source polysilicon is connected；
Drain electrode, positioned at the lower surface of the substrate of first conduction type.
Optionally, first source polysilicon and be coated on described the of the first source polysilicon outer wall
One dielectric layer constitute terminal protection device, the MOSFET terminal structure include at least one second conduction type the second body area and
Multiple terminal protection devices；Multiple terminal protection devices are intervally arranged in the termination environment, and described second is conductive
Second body area of type is between the adjacent terminal protection device；The source electrode also with second conduction type
Second body area is connected.
As described above, the MOSFET terminal structure of the utility model has the advantages that
In the MOSFET terminal structure of the utility model, first Jie of the side wall of first groove and bottom in termination environment
The thickness of matter layer is greater than the thickness of the second dielectric layer of the side wall and bottom that are located in active area second groove, can make terminal
The breakdown voltage in area is higher than the breakdown voltage of active area, so that effective protection MOSFET terminal structure, improves MOSFET terminal knot
The performance of structure；
The side wall of second groove and the second dielectric layer of bottom in active area in the MOSFET terminal structure of the utility model
Thickness the concentration of the drift layer of active area can be improved, to optimize the electric conduction of MOSFET terminal structure than relatively thin
Resistance.
Detailed description of the invention
Fig. 1 is shown as the flow chart of the preparation method of the MOSFET terminal structure provided in the utility model embodiment one.
Fig. 2 is shown as in the preparation method of the MOSFET terminal structure in the utility model embodiment one knot obtained by step 1)
The cross section structure schematic diagram of structure.
Fig. 3 to Fig. 4 is shown as step 2) in the preparation method of the MOSFET terminal structure in the utility model embodiment one
The cross section structure schematic diagram of resulting structures.
Fig. 5 to Fig. 9 is shown as step 3) in the preparation method of the MOSFET terminal structure in the utility model embodiment one
The cross section structure schematic diagram of resulting structures.
Figure 10 to Figure 14 is shown as step in the preparation method of the MOSFET terminal structure in the utility model embodiment one
4) cross section structure schematic diagram of resulting structures.
Figure 15 is shown as in the preparation method of the MOSFET terminal structure in the utility model embodiment one obtained by step 5)
The cross section structure schematic diagram of structure.
Figure 16 to Figure 18 is shown as step in the preparation method of the MOSFET terminal structure in the utility model embodiment one
6) cross section structure schematic diagram of resulting structures.
Figure 19 to Figure 20 is shown as step in the preparation method of the MOSFET terminal structure in the utility model embodiment one
7) cross section structure schematic diagram of resulting structures.
Figure 21 to Figure 24 is shown as step in the preparation method of the MOSFET terminal structure in the utility model embodiment one
8) cross section structure schematic diagram of resulting structures.
Component label instructions
The substrate of 10 first conduction types
The epitaxial layer of 11 first conduction types
12 active areas
13 termination environments
14 first grooves
15 second grooves
16 first medium layers
17 first source polysilicons
18 second dielectric layer
19 second source polysilicons
20 dielectric isolation layers
21 gate oxides
22 gate polysilicon layers
23 terminal protection devices
First body area of 24 second conduction types
Second body area of 25 second conduction types
The source region of 26 first conduction types
27 source electrodes
28 drain electrodes
29 mask layers
291 opening figures
Specific embodiment
Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to FIG. 1 to FIG. 24.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though it is only shown with related component in the utility model rather than when according to actual implementation in diagram
Component count, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind
Become, and its assembly layout kenel may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the utility model provides a kind of preparation method of MOSFET terminal structure, the MOSFET terminal knot
The preparation method of structure comprising steps of
1) substrate of the first conduction type is provided, it is conductive that the upper surface of the substrate of the first conduction type of Yu Suoshu forms first
The epitaxial layer of type；The substrate of the epitaxial layer of first conduction type and first conduction type includes transversely being distributed
Active area and termination environment；
2) first groove and second groove are formed in the epitaxial layer of the first conduction type of Yu Suoshu, wherein first ditch
In in the termination environment, the second groove is located in the active area slot position；
3) first medium layer formed on the side wall of Yu Suoshu first groove and bottom, and in forming first in the first groove
Source polysilicon；
4) second dielectric layer is formed on the side wall of Yu Suoshu second groove and bottom, and in the surface shape of the second dielectric layer
At the second source polysilicon；Wherein, the thickness of the second dielectric layer is less than the thickness of the first medium layer；
5) upper surface of the second source polysilicon of Yu Suoshu and the upper surface of the second dielectric layer, which are formed, is dielectrically separated from
Layer；
6) upper portion side wall of Yu Suoshu second groove forms gate oxide, and in forming gate polycrystalline in the second groove
Silicon layer, the gate polysilicon layer are located on the dielectric isolation layer；
7) top of the epitaxial layer of the first conduction type of Yu Suoshu forms the first body area of the second conduction type and first leads
The source region of electric type；Wherein, the source region of first conduction type is located at the first body Qu Shangfang of second conduction type, institute
First body area of the source region and second conduction type of stating the first conduction type is respectively positioned on the periphery of the second groove, and position
In in the active area and between the second groove and the first groove.
In step 1), S1 step and Fig. 2 in Fig. 1 are please referred to, the substrate 10 of the first conduction type, Yu Suoshu are provided
The upper surface of the substrate 10 of one conduction type forms the epitaxial layer 11 of the first conduction type；The epitaxial layer of first conduction type
11 and the substrate 10 of first conduction type include the active area 12 that is transversely distributed and termination environment 13.
As an example, the substrate 10 of first conduction type may include but be not limited only to the silicon lining of the first conduction type
The germanium silicon substrate at bottom, the silicon carbide substrates of the first conduction type or the first conduction type.Preferably, in the present embodiment, described
The substrate 10 of one conduction type is the silicon substrate of the first conduction type.Specifically, the substrate 10 of first conduction type can be with
For the substrate formed by the ion implanting for carrying out the first conduction type to intrinsic substrate.
As an example, can be epitaxially-formed using epitaxy technique in the surface of the substrate 10 of first conduction type
The epitaxial layer 11 of first conduction type.
As an example, the epitaxial layer 11 of first conduction type can be used as drift region.
In step 2), the epitaxial layer 11 of the first conduction type of S2 step and Fig. 3 to Fig. 4, Yu Suoshu in Fig. 1 is please referred to
Interior formation first groove 14 and second groove 15, wherein the first groove 14 is located in the termination environment 13, second ditch
Slot 15 is located in the active area 12.
As an example, step 2) may include steps of:
Patterned masking layer (not shown) 2-1) is formed in the epitaxial layer 11 of the first conduction type of Yu Suoshu, it is described graphical
Opening (not shown) is formed in mask layer, the opening defines the position of the first groove 14 and the second groove 15
And shape；
It is 2-2) conductive to described first using dry etch process or wet-etching technology according to the Patterned masking layer
The epitaxial layer 11 of type performs etching, to obtain the first groove 14 and the second groove 15；
2-3) remove the Patterned masking layer.
As an example, the depth of the first groove 14 can be identical with the depth of the second groove 15, it can also not
Together；The depth of the first groove 14 is less than the thickness of the epitaxial layer 11 of first conduction type, the second groove 15
Depth is less than the thickness of the epitaxial layer 11 of first conduction type.
As an example, the width of the first groove 14 can be identical with the width of the second groove 15, it can also not
Together, it is preferable that in the present embodiment, the width of the first groove 14 is greater than the width of the second groove 15.
As an example, the quantity of the first groove 14 formed in the termination environment 13 can carry out according to actual needs
Setting, the quantity of the first groove 14 can be one (as shown in Figure 3), or multiple (as shown in Figure 4, wherein figure
4 be only two as an example, the quantity of the first groove 14 is unlimited in actual example with the quantity of the first groove 14
In two, can for three, four, five it is even more).
In step 3), the S3 step and Fig. 5 to Fig. 7 in Fig. 1, the side wall of Yu Suoshu first groove 14 and bottom are please referred to
First medium layer 16 is formed, and in forming the first source polysilicon 17 in the first groove 14.
As an example, step 3) may include steps of:
3-1) upper surface of the epitaxial layer 11 of interior, described first conduction type of Yu Suoshu second groove 15, first ditch
The first medium layer 16 is formed on the side wall of slot 14 and bottom, as shown in Figure 5；
3-2) in the Yu Suoshu first groove 14 and upper surface of the first medium layer 16 forms the first source electrode polycrystalline
Silicon layer 17, as shown in Figure 6；
3-3) removal is located at the first medium layer 16 and the position of the upper surface of the epitaxial layer 11 of first conduction type
In first source polysilicon 17 on the epitaxial layer 11 of first conduction type, as shown in Figure 7.
As an example, step 3-1) in formed the first medium layer 16 thickness be less than the first groove 14 width
The half of degree, to ensure still to be reserved with the first source electrode polycrystalline in the first groove 14 after the first medium layer 16 is formed
The space of silicon layer 17；The first medium layer 16 can fill up the second groove 15, certainly, the first medium layer 16
It can be with the unfilled second groove 15；Specifically, physical gas-phase deposition, chemical vapor deposition process or heat can be used
Oxidation technology forms the first medium layer 16；The first medium layer 16 may include but be not limited only to silicon oxide layer.
As an example, step 3-2) in, institute can be formed using physical gas-phase deposition or chemical vapor deposition process
State the first source polysilicon 17；First source polysilicon 17 fills up the first groove 14；It should be noted that institute
Stating the first source polysilicon 17 is preferably doped polysilicon layer, to ensure the electric conductivity of first source polysilicon 17.
As an example, step 3-3) in, described the can be located at using etching technics or chemical mechanical milling tech removal
The first medium layer 16 of the upper surface of the epitaxial layer 11 of one conduction type and epitaxial layer positioned at first conduction type
First source polysilicon 17 on 11.
As an example, step 3-3) further include later following steps:
3-4) upper surface of the epitaxial layer 11 of the first conduction type of Yu Suoshu forms mask layer 29, shape in the mask layer 29
At there is opening figure 291, the opening figure 291 at least exposes the second groove 15, as shown in Figure 8；
3-5) removal is located at the first medium layer 16 in the second groove 15, as shown in Figure 9.
As an example, step 3-4) in the mask layer 29 that is formed may include hard mask layer, for example silicon nitride mask
Layer etc..
As an example, step 3-5) in, described the can be located at using dry etch process or wet-etching technology removal
The first medium layer 16 in two grooves 15.
In step 4), the S4 step and Figure 10 to Figure 14 in Fig. 1, the side wall of Yu Suoshu second groove 15 and bottom are please referred to
Portion forms second dielectric layer 18, and forms the second source polysilicon 19 in the surface of the second dielectric layer 18；Wherein, described
The thickness of second dielectric layer 18 is less than the thickness of the first medium layer 16.
As an example, step 4) may include steps of:
4-1) upper surface of Yu Suoshu mask layer 29, exposed first conduction type epitaxial layer 11 upper surface,
The bottom of the second groove 15 and side wall form second dielectric layer 18, as shown in Figure 10；
4-2) remove the epitaxial layer 11 of the upper surface and exposed first conduction type that are located at the mask layer 29
The second dielectric layer 18 of upper surface, as shown in figure 11；
4-3) upper surface of Yu Suoshu mask layer 29, exposed first conduction type epitaxial layer 11 upper surface,
The bottom of the second groove 15 and side wall form the second source polysilicon 19, as shown in figure 12；
4-4) remove the epitaxial layer 11 of the upper surface and exposed first conduction type that are located at the mask layer 29
Second source polysilicon 19 of upper surface, and etch part second source that removal is located in the second groove 15
Pole polysilicon layer 19, so that remaining in the upper surface of second source polysilicon 19 in the second groove 15 lower than institute
The top surface of second groove 15 is stated, as shown in figure 13；
4-5) etching removal is located at the part second dielectric layer 18 in the second groove 15, so that remaining in described
The upper surface of the second dielectric layer 15 in second groove 15 is lower than the top surface of the second groove 15, as shown in figure 14.
As an example, step 4-1) formed the second dielectric layer 18 thickness be less than the second groove 15 width
Half, to ensure still to be reserved with second source polysilicon in the second groove 15 after the second dielectric layer 18 is formed
The space of layer 19；Specifically, can be formed using physical gas-phase deposition, chemical vapor deposition process or thermal oxidation technology
The second dielectric layer 18；The second dielectric layer 18 may include but be not limited only to silicon oxide layer.
As an example, step 4-2) in, the upper surface of the mask layer 29 and naked can be located at using etching technics removal
The second dielectric layer 18 of the upper surface of the epitaxial layer 11 of first conduction type of dew.
As an example, step 4-3) in, institute can be formed using physical gas-phase deposition or chemical vapor deposition process
State the second source polysilicon 19；Second source polysilicon 19 fills up the second groove 15；It should be noted that institute
Stating the second source polysilicon 19 is preferably doped polysilicon layer, to ensure the electric conductivity of second source polysilicon 19.
As an example, step 4-4) in, the mask layer 29 first can be located at using chemical mechanical milling tech removal
Second source polysilicon 19 of the upper surface of the epitaxial layer 11 of upper surface and exposed first conduction type, then adopt
It is more that part second source electrode for carving and removing and being located in the second groove 15 is returned with dry etch process or wet-etching technology
Crystal silicon layer 19.
As in exemplary step 4-5), can be located at using dry etch process or wet-etching technology etching removal described
The part second dielectric layer 18 in second groove 15.
In step 5), S5 step and Figure 15 in Fig. 1, the upper surface of the second source polysilicon of Yu Suoshu 19 are please referred to
And the upper surface of the second dielectric layer 18 forms dielectric isolation layer 20.
As an example, the dielectric isolation layer can be formed using physical gas-phase deposition or chemical vapor deposition process
20；Second source polysilicon 19 is at least completely covered in the dielectric isolation layer 20.
As an example, the material of the dielectric isolation layer 20 can be identical as the material of the second dielectric layer 18, preferably
Ground, in the present embodiment, the material of the dielectric isolation layer 20 may include but be not limited only to silicon oxide layer.
As an example, further including the steps that removing the mask layer 29 after step 5).
In step 6), the S6 step and Figure 16 to Figure 18 in Fig. 1, the upper portion side wall of Yu Suoshu second groove 15 are please referred to
Gate oxide 21 is formed, and in forming gate polysilicon layer 22 in the second groove 15, the gate polysilicon layer 22 is located at
On the dielectric isolation layer 20.
As an example, step 6) may include steps of:
6-1) upper portion side wall of Yu Suoshu second groove 15, the upper surface of the dielectric isolation layer 20 and first conduction
The upper surface of the epitaxial layer 11 of type forms the gate oxide 21, as shown in figure 16；
6-2) upper surface of Yu Suoshu gate oxide 21 forms the gate polysilicon layer 22, the gate polysilicon layer 22
It fills up the second groove 15 and part is located on the epitaxial layer 11 of first conduction type, as shown in figure 17；
6-3) removal is located at the gate polysilicon layer 22 on the epitaxial layer 11 of first conduction type and is located at institute
The gate oxide 21 on the epitaxial layer 11 of the first conduction type is stated, as shown in figure 18.
As an example, step 6-1) in, physical gas-phase deposition, chemical vapor deposition process or thermal oxide can be used
Technique forms the gate oxide 21, and the thickness of the gate oxide 21 is less than the half of the width of the second groove 15, with
After ensuring that the gate oxide 21 is formed, the space of the gate polysilicon layer 22 is still reserved in the second groove 15.
The gate oxide 21 may include but be not limited only to silicon oxide layer, and the thickness of the gate oxide 21 is less than the first medium
The thickness of layer 16.
As an example, step 6-2) in, institute can be formed using physical gas-phase deposition or chemical vapor deposition process
State second grid polysilicon layer 22；It should be noted that the gate polysilicon layer 22 is preferably doped polysilicon layer, to ensure
The electric conductivity of the gate polysilicon layer 22.
As an example, step 6-3) in, described the can be located at using etching technics or chemical mechanical milling tech removal
The gate polysilicon layer 22 on the epitaxial layer 11 of one conduction type and on the epitaxial layer 11 of first conduction type
The gate oxide 21.
In step 7), the epitaxial layer of the first conduction type of S7 step and Figure 19 to Figure 20, Yu Suoshu in Fig. 1 is please referred to
First body area 24 of the second conduction type and the source region 26 of the first conduction type are formed at 11 top；Wherein, described first is conductive
The source region 26 of type is located at 24 top of the first body area of second conduction type, the source region 26 of first conduction type and institute
The the first body area 26 for stating the second conduction type is respectively positioned on the periphery of the second groove 15, and is located in the active area 12 and institute
It states between second groove 15 and the first groove 14.
As an example, the can be carried out from the top of the epitaxial layer 11 of first conduction type using ion implantation technology
The ion implanting of two conduction types, to form the first body area 26 of second conduction type.
As an example, the first conduction type can be carried out in the first body area 26 of established second conduction type
Ion injection, the source of first conduction type is formed with the upper surface in the first body area 26 of second conduction type
Area 26.
It should be noted that when the quantity of the first groove 14 is multiple, the extension of the first conduction type of Yu Suoshu
While first body area 24 of second conduction type is formed at the top of floor 11, the epitaxial layer of the first conduction type of Yu Suoshu
Second body area 25 of the second conduction type is formed at 11 top, and the second body area 25 of second conduction type is located at adjacent described
Between first groove 14.
It should be noted that Fig. 5, into Figure 18, corresponding step resulting structures are only to be formed with one in the termination environment 13
The first groove 14 is used as example.
In one example, first conduction type in above steps may include N-type, at this point, described second leads
Electric type may include p-type.
In another example, first conduction type in above steps may include p-type, at this point, described second
Conduction type may include N-type.
Further include following steps after step 7) as an example, please referring to Figure 21 to Figure 24:
8) formation source electrode 27 and gate electrode (not shown) on the epitaxial layer 11 of the first conduction type of Yu Suoshu, and in
The lower surface of the substrate 10 of first conduction type forms drain electrode 28；Wherein, the source electrode 27 and described second
The first body area 24, first source polysilicon 17 and second source polysilicon 19 of conduction type are connected, institute
Gate electrode is stated to be connected with the gate polysilicon layer 22.
In one example, the source electrode 27 and institute can be formed on the epitaxial layer 11 prior to first conduction type
Gate electrode (not shown) is stated, forms the drain electrode 28 then at the lower surface of the substrate 10 of first conduction type.
In another example, the drain electrode can be formed prior to the lower surface of the substrate 10 of first conduction type
28, the source electrode 27 and the gate electrode are formed on the epitaxial layer 11 of first conduction type.
As an example, the source electrode 27, the gate electrode and the drain electrode 28 may each comprise metal electricity
Pole, for example, copper electrode, aluminium electrode, gold electrode, silver electrode or nickel electrode etc..
As an example, when the MOSFET terminal structure includes the second body area 25 of second conduction type, the source
Pole electrode 27 is also connected with the second body area 25 of second conduction type.
In the MOSFET terminal structure of the preparation method preparation of the utility model, it is located at described in the termination environment 13
The thickness of the first medium layer 16 of the side wall and bottom of first groove 14, which is greater than, to be located at described second in the active area 12
The thickness of the second dielectric layer 18 of the side wall and bottom of groove 15 can make the breakdown voltage of the termination environment 13 high
In the breakdown voltage of the active area 12, so that MOSFET terminal structure described in effective protection, improves the MOSFET terminal knot
The performance of structure；Described second in active area 12 described in the MOSFET terminal structure of the preparation method preparation of the utility model
The drift of the active area 12 can be improved than relatively thin in the thickness of the second dielectric layer 18 of the side wall and bottom of groove 15
The concentration for moving layer (epitaxial layer 11 of i.e. described first conduction type), to optimize the electric conduction of the MOSFET terminal structure
Resistance.
Embodiment two
Incorporated by reference to Fig. 2 to Figure 22 with continued reference to Figure 23 and Figure 24, the utility model also provides a kind of MOSFET terminal structure,
The MOSFET terminal structure includes: the substrate 10 of the first conduction type；The epitaxial layer 11 of first conduction type, described first leads
The epitaxial layer 11 of electric type is located at the upper surface of the substrate 10 of first conduction type；The epitaxial layer of first conduction type
11 and the substrate 10 of first conduction type include the active area 12 that is transversely distributed and termination environment 13；First source electrode polycrystalline
Silicon layer 17, first source polysilicon 17 are located in the epitaxial layer 11 of first conduction type, and are located at the terminal
In area 13；First medium layer 16, the first medium layer 16 are located at first source polysilicon 17 and first conduction
Between the epitaxial layer 11 of type；Second source polysilicon 19, it is conductive that second source polysilicon 19 is located at described first
In the epitaxial layer 11 of type, and it is located in the active area 12；Second dielectric layer 18, the second dielectric layer 18 are located at described
Between second source polysilicon 19 and the epitaxial layer 11 of first conduction type, the thickness of the second dielectric layer 18 is less than
The thickness of the first medium layer 16；Gate polysilicon layer 22, the gate polysilicon layer 22 are located at first conduction type
Epitaxial layer 11 in, and be located at second source polysilicon 19 top；Gate oxide 21, the gate oxide 21 are located at
Between second source polysilicon 19 and the epitaxial layer 11 of first conduction type；Dielectric isolation layer 20, the insulation
Separation layer 20 is located in the epitaxial layer 11 of first conduction type, and is located at the gate polysilicon layer 22 and described second
Between source polysilicon 19；The first body area 24 in the first body area 24 of the second conduction type, second conduction type is located at
The periphery of the gate oxide 21；The source region 26 of the source region 26 of first conduction type, first conduction type is located at the grid
The periphery of oxide layer 21, and it is located at 24 top of the first body area of second conduction type.
As an example, the substrate 10 of first conduction type may include but be not limited only to the silicon lining of the first conduction type
The germanium silicon substrate at bottom, the silicon carbide substrates of the first conduction type or the first conduction type.Preferably, in the present embodiment, described
The substrate 10 of one conduction type is the silicon substrate of the first conduction type.Specifically, the substrate 10 of first conduction type can be with
For the substrate formed by the ion implanting for carrying out the first conduction type to intrinsic substrate.
As an example, the epitaxial layer 11 of first conduction type can be used as drift region.
As an example, the first medium layer 16 may include but be not limited only to silicon oxide layer；The first source electrode polycrystalline
Silicon layer 17 is preferably doped polysilicon layer, to ensure the electric conductivity of first source polysilicon 17.
As an example, the second dielectric layer 18 may include but be not limited only to silicon oxide layer；The second source electrode polycrystalline
Silicon layer 19 is preferably doped polysilicon layer, to ensure the electric conductivity of second source polysilicon 19.
As an example, the gate oxide 21 may include but be not limited only to silicon oxide layer, the thickness of the gate oxide 21
Degree is less than the thickness of the first medium layer 16.
As an example, the gate polysilicon layer 22 is preferably doped polysilicon layer, to ensure the gate polysilicon layer
22 electric conductivity.
As an example, second source polysilicon 19 is at least completely covered in the dielectric isolation layer 20.
As an example, the material of the dielectric isolation layer 20 can be identical as the material of the second dielectric layer 18, preferably
Ground, in the present embodiment, the material of the dielectric isolation layer 20 may include but be not limited only to silicon oxide layer.
As an example, the MOSFET terminal structure further include: gate electrode (not shown), the gate electrode with it is described
Gate polysilicon layer 22 is connected；First body area 24 of source electrode 27, the source electrode 27 and second conduction type,
First source polysilicon 17 and second source polysilicon 19 are connected；Drain electrode 28, the drain electrode
28 are located at the lower surface of the substrate 10 of first conduction type.
As an example, the source electrode 27, the gate electrode and the drain electrode 28 may each comprise metal electricity
Pole, for example, copper electrode, aluminium electrode, gold electrode, silver electrode or nickel electrode etc..
As an example, first source polysilicon 17 and be coated on 17 outer wall of the first source polysilicon
The first medium layer 16 constitutes terminal protection device 23, and the MOSFET terminal structure includes at least one second conduction type
Second body area 25 and multiple terminal protection devices 23；Multiple terminal protection devices 23 are spaced in the termination environment 13
Arrangement, the second body area 25 of second conduction type is between the adjacent terminal protection device 13；The source electrode
27 are also connected with the second body area 25 of second conduction type.
The quantity of the terminal protection device 23 can be one (as shown in figure 23), or multiple (such as Figure 24 institute
Show, wherein Figure 24 is two as an example, the terminal protection described in actual example with the quantity of the terminal protection device 23
The particular number of device 23 can also for three, four, five it is even more).
In one example, above-mentioned first conduction type may include N-type, at this point, second conduction type can
To include p-type.
In another example, above-mentioned first conduction type may include p-type, at this point, second conduction type
It may include N-type.
In the MOSFET terminal structure of the utility model, the side of the first groove 14 in the termination environment 13
The thickness of wall and the first medium layer 16 of bottom be greater than be located at the active area 12 in the second groove 15 side wall and
The thickness of the second dielectric layer 18 of bottom can make the breakdown voltage of the termination environment 13 be higher than the active area 12
Breakdown voltage, so that MOSFET terminal structure described in effective protection, improves the performance of the MOSFET terminal structure；This is practical new
Second Jie of the side wall of the second groove 15 and bottom in active area 12 described in the MOSFET terminal structure of type
Drift layer (the extension of i.e. described first conduction type of the active area 12 can be improved than relatively thin in the thickness of matter layer 18
The concentration of layer 11), to optimize the conducting resistance of the MOSFET terminal structure.
In conclusion the utility model provides a kind of MOSFET terminal structure, the MOSFET terminal structure includes: first
The substrate of conduction type；The epitaxial layer of first conduction type, positioned at the upper surface of the substrate of first conduction type；Described
The substrate of the epitaxial layer of one conduction type and first conduction type includes the active area being transversely distributed and termination environment；First
Source polysilicon in the epitaxial layer of first conduction type, and is located in the termination environment；First medium layer, position
Between first source polysilicon and the epitaxial layer of first conduction type；Second source polysilicon is located at institute
In the epitaxial layer for stating the first conduction type, and it is located in the active area；Second dielectric layer is located at second source polysilicon
Between layer and the epitaxial layer of first conduction type, the thickness of the second dielectric layer is less than the thickness of the first medium layer
Degree；Gate polysilicon layer in the epitaxial layer of first conduction type, and is located at the upper of second source polysilicon
Side；Gate oxide, between second source polysilicon and the epitaxial layer of first conduction type；It is dielectrically separated from
Layer in the epitaxial layer of first conduction type, and is located at the gate polysilicon layer and second source polysilicon
Between layer；First body area of the second conduction type, positioned at the periphery of the gate oxide；The source region of first conduction type, is located at
The periphery of the gate oxide, and it is located at the first body Qu Shangfang of second conduction type.The MOSFET of the utility model is whole
In end structure, the thickness of the side wall of first groove and the first medium layer of bottom, which is greater than, in termination environment is located in active area the
The thickness of the second dielectric layer of the side wall and bottom of two grooves can make the breakdown voltage of termination environment be higher than the breakdown of active area
Voltage, so that effective protection MOSFET terminal structure, improves the performance of MOSFET terminal structure；The MOSFET of the utility model is whole
The thickness of the second dielectric layer of the side wall and bottom of second groove can be improved active than relatively thin in active area in end structure
The concentration of the drift layer in area, to optimize the conducting resistance of MOSFET terminal structure.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.
Claims (6)
1. a kind of MOSFET terminal structure characterized by comprising
The substrate of first conduction type；
The epitaxial layer of first conduction type, positioned at the upper surface of the substrate of first conduction type；First conduction type
Epitaxial layer and the substrate of first conduction type include the active area being transversely distributed and termination environment；
First source polysilicon in the epitaxial layer of first conduction type, and is located in the termination environment；
First medium layer, between first source polysilicon and the epitaxial layer of first conduction type；
Second source polysilicon in the epitaxial layer of first conduction type, and is located in the active area；
Second dielectric layer, between second source polysilicon and the epitaxial layer of first conduction type, described
The thickness of second medium layer is less than the thickness of the first medium layer；
Gate polysilicon layer in the epitaxial layer of first conduction type, and is located at second source polysilicon
Top；
Gate oxide, between second source polysilicon and the epitaxial layer of first conduction type；
Dielectric isolation layer in the epitaxial layer of first conduction type, and is located at the gate polysilicon layer and described the
Between two source polysilicons；
First body area of the second conduction type, positioned at the periphery of the gate oxide；
The source region of first conduction type positioned at the periphery of the gate oxide, and is located at the first body of second conduction type
Above area.
2. MOSFET terminal structure according to claim 1, it is characterised in that: the thickness of the gate oxide is less than described
The thickness of first medium layer.
3. MOSFET terminal structure according to claim 1, it is characterised in that: first conduction type includes N-type, and
Second conduction type includes p-type.
4. MOSFET terminal structure according to claim 1, it is characterised in that: first conduction type includes p-type, and
Second conduction type includes N-type.
5. MOSFET terminal structure according to any one of claim 1 to 4, it is characterised in that: the MOSFET terminal
Structure further include:
Gate electrode is connected with the gate polysilicon layer；
Source electrode, the first body area, first source polysilicon and second source electrode with second conduction type
Polysilicon layer is connected；
Drain electrode, positioned at the lower surface of the substrate of first conduction type.
6. MOSFET terminal structure according to claim 5, it is characterised in that: first source polysilicon and with packet
The first medium layer for being overlying on the first source polysilicon outer wall constitutes terminal protection device, the MOSFET terminal knot
Structure include at least one second conduction type the second body area and multiple terminal protection devices；Multiple terminal protection devices
Be intervally arranged in the termination environment, the second body area of second conduction type be located at the adjacent terminal protection device it
Between；The source electrode is also connected with the second body area of second conduction type.
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