CN207009443U - Schottky device structure - Google Patents
Schottky device structure Download PDFInfo
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- CN207009443U CN207009443U CN201720655357.2U CN201720655357U CN207009443U CN 207009443 U CN207009443 U CN 207009443U CN 201720655357 U CN201720655357 U CN 201720655357U CN 207009443 U CN207009443 U CN 207009443U
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 48
- 229920005591 polysilicon Polymers 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 238000000407 epitaxy Methods 0.000 claims abstract description 23
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 61
- 238000003475 lamination Methods 0.000 claims description 56
- 229910016570 AlCu Inorganic materials 0.000 claims description 30
- 239000007772 electrode material Substances 0.000 claims description 11
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 claims description 10
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000007769 metal material Substances 0.000 claims description 3
- 230000006835 compression Effects 0.000 abstract description 16
- 238000007906 compression Methods 0.000 abstract description 16
- 238000012360 testing method Methods 0.000 abstract description 12
- 230000004888 barrier function Effects 0.000 abstract description 8
- 238000013517 stratification Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 6
- 238000004806 packaging method and process Methods 0.000 abstract description 6
- 238000012536 packaging technology Methods 0.000 abstract description 5
- 230000002093 peripheral effect Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 abstract 5
- 239000011229 interlayer Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 230000008569 process Effects 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 238000011049 filling Methods 0.000 description 8
- 229910000510 noble metal Inorganic materials 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
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- 229910052782 aluminium Inorganic materials 0.000 description 1
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- 239000010953 base metal Substances 0.000 description 1
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- 150000001875 compounds Chemical class 0.000 description 1
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- 239000003574 free electron Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
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Abstract
The utility model provides a kind of schottky device structure, including：N-type epitaxy layer, it is formed with multiple first grooves and the second groove positioned at first groove outer peripheral areas；Oxide layer and polysilicon, it is formed in first groove and second groove；3rd groove, removes the partial polysilicon in first groove and oxide layer forms；Metal silicide, it is formed at bottom and the side wall of the 3rd groove；Conductive material, it is filled in the 3rd groove；And upper metal electrode structure.The utility model can be effectively increased schottky area area, drop low forward conduction voltage VF；And groove structure is utilized, reduces leakage current IR；Simultaneously in the metal of test and packaging and routing and underlying device interlayer increase dielectric layer, to buffer the effect of extraneous stress, external compression is set to be distributed to whole chip by dielectric layer.Schottky junction of the present utility model is changed to vertical stratification from planar structure, additional compression is not applied directly to Schottky barrier, can increase packaging technology window.
Description
Technical field
A kind of semiconductor device structure and its manufacture method are the utility model is related to, more particularly to a kind of schottky device
Structure and its manufacture method.
Background technology
With the continuous development of semiconductor technology, power device is widely used in disk as a kind of new device
The fields such as driving, automotive electronics.Power device is required to bear larger voltage, electric current and power termination.And existing MOS
The devices such as transistor can not meet the demand, and therefore, in order to meet the needs of application, various power devices turn into Jiao of concern
Point.
Existing Schottky diode is usually that noble metal (gold, silver, aluminium, platinum etc.) is positive pole, is negative using N-type semiconductor
Pole, there is rectification characteristic using the potential barrier formed on the two contact surface and manufactured metal-semiconductor device.Because N-type is partly led
There is substantial amounts of electronics in body, only minimal amount of free electron in noble metal, so electronics is just partly led from the high N-type of concentration
Spread in body into the low noble metal of concentration.Obviously, there is no hole in noble metal, hole is also just not present half from metal to N-type
The diffusion motion of conductor.As electronics is constantly diffused into noble metal from N-type semiconductor, N-type semiconductor sheet electron concentration is gradual
Reduce, surface electroneutrality is destroyed, and then just forms potential barrier, and its direction of an electric field is N-type semiconductor towards noble metal.But in the electricity
Under field action, the electronics in noble metal can also produce the drift motion from noble metal to N-type semiconductor, so as to weaken due to
Diffusion motion and the electric field formed.After the space-charge region of one fixed width is set up, electronics drift motion caused by electric field and
Electrons spread motion reaches relative balance caused by concentration difference, just forms Schottky barrier.
It can be seen that Schottky diode is the majority carrier that the rectification characteristic based on metal and semiconductor contact is operated
Device, have the characteristics that forward voltage drop is low, reverse recovery current is small, switching speed is fast, noise coefficient is small, low in energy consumption, it is wide at present
It is general to be applied to the fields such as Switching Power Supply, frequency converter, driver.
Existing Schottky is mostly the schottky device of planar structure, as shown in figure 1, and groove structure Schottky device
Part, as shown in Figure 2.
The advantages of schottky device of planar structure is relatively low forward conduction voltage VF, and shortcoming is its leakage current IR
It is higher；
The advantages of schottky device of groove structure is that can pass through groove structure to reduce leakage current IR；Shortcoming is positive guide
The pressure that is powered VF is of a relatively high, because groove structure makes device have larger stress in itself, therefore it is more sensitive to extraneous stress ratio.
In actual applications, because Schottky is surface device, therefore surveyed eventually after chip-scale is tested and is encapsulated, easily
Influenceed by test pressure and encapsulation stress, and cause element leakage higher, actual effect is tested after encapsulation, is resurveyed endless, reliably
Property failure etc..
Based on described above, there is provided one kind can integrate the advantages of groove-shaped Schottky and Planar Schottky, solve ditch
The packaging and testing problem of groove profile schottky device, and the new schottky device structure for effectively improving device synthesis performance belongs in fact
It is necessary.
Utility model content
In view of the above the shortcomings that prior art, the purpose of this utility model is to provide a kind of schottky device structure
And its manufacture method, the advantages of to integrate groove-shaped Schottky and Planar Schottky, solve the envelope of trench schottky device
Test problem is filled, and effectively improves device synthesis performance.
In order to achieve the above objects and other related objects, the utility model provides a kind of manufacturer of schottky device structure
Method, the manufacture method include：1) in forming multiple first grooves in N-type epitaxy layer and outside the multiple first groove
Enclose the second groove in region；2) form oxide layer in the first groove and second groove surface, and in the first groove and
Filling polysilicon in second groove；3) partial polysilicon and oxide layer in the first groove are removed, forms the 3rd groove, is protected
Stay the polysilicon and oxide layer in the second groove；4) schottky metal is formed in the bottom of the 3rd groove and side wall
Layer, and anneal and form metal silicide；5) in filling conductive material in the 3rd groove；And 6) make upper metal electrode knot
Structure.
Preferably, in step 2), oxide layer is formed in the first groove and second groove surface using thermal oxidation process,
The thickness of the oxide layer is 50nm~1000nm.
Preferably, in step 2), using chemical vapour deposition technique in filling polycrystalline in the first groove and second groove
Silicon, the doping concentration of the polysilicon is 1019~1021/cm3, and the polysilicon is returned using dry etch process and carved to institute
State the top surface of first groove and second groove.
Preferably, in step 3), the partial polysilicon in the first groove is removed using photo etching process, then
The exposed oxide layer of the first groove side wall is removed using wet etching, to form the 3rd groove.
Preferably, the depth of the 3rd groove is 0.2~0.8 times of the first groove depth.
Preferably, the depth of the 3rd groove is 0.4~0.6 times of the first groove depth.
Preferably, step 4) includes：Xiao Te 4-1) is formed in the bottom of the 3rd groove and side wall using sputtering technology
Base metal layer, the material of the schottky metal layer include one kind in Pt, Ni, Ti, Cr, W, Mo and Co；4-2) using quick
Schottky metal layer described in the method for heat treatment method or furnace annealing forms metallic silicon with the bottom of the 3rd groove and side wall
Compound, to form schottky junction.
Preferably, in step 5), using sputtering, evaporation coating method or its be incorporated into the 3rd groove and fill conduction material
Material, the conductive material include Al layers, AlCu layers, AlSiCu layers, TiN/AlSiCu/TiN/Ti/Ni/Ag laminations, TiN/
In AlSiCu laminations, TiN/AlCu/TiN/Ti/Ni/Ag laminations, TiN/AlCu laminations, TiN/AlSi laminations or TiN/Al laminations
One kind.
Preferably, step 6) includes：6-1) using chemical vapour deposition technique in the N-type epitaxy layer, the first groove
And form dielectric layer in the second groove；Metal connecting line hole 6-2) is opened in the dielectric layer using photo etching process；
6-3) using sputtering, evaporation coating method or its be incorporated into and electrode material filled in the metal connecting line hole in, the electrode material includes
Al layers, AlCu layers, AlSiCu layers, TiN/AlSiCu/TiN/Ti/Ni/Ag laminations, TiN/AlSiCu laminations, TiN/AlCu/TiN/
One kind in Ti/Ni/Ag laminations, TiN/AlCu laminations, TiN/AlSi laminations or TiN/Al laminations.
The utility model also provides a kind of schottky device structure, including：N-type epitaxy layer, formed in the N-type epitaxy layer
There are multiple first grooves and the second groove positioned at the multiple first groove outer peripheral areas；Oxide layer, it is formed at described
One groove and second groove surface；Polysilicon, it is filled in the first groove and second groove；3rd groove, described in removal
Partial polysilicon and oxide layer in first groove form；Metal silicide, bottom and the side wall of the 3rd groove are formed at,
To form schottky junction；Conductive material, it is filled in the 3rd groove；And upper metal electrode structure.
Preferably, the thickness of the oxide layer is 50nm~1000nm, and the doping concentration of the polysilicon is 1019~
1021/cm3。
Preferably, the depth of the 3rd groove is 0.2~0.8 times of the first groove depth.
Preferably, the depth of the 3rd groove is 0.5~0.6 times of the first groove depth.
Preferably, the metal material of the metal silicide includes one kind in Pt, Ni, Ti, Cr, W, Mo and Co.
Preferably, the conductive material is folded including Al layers, AlCu layers, AlSiCu layers, TiN/AlSiCu/TiN/Ti/Ni/Ag
Layer, TiN/AlSiCu laminations, TiN/AlCu/TiN/Ti/Ni/Ag laminations, TiN/AlCu laminations, TiN/AlSi laminations or TiN/Al
One kind in lamination.
Preferably, the upper metal electrode structure includes：Dielectric layer, it is formed at the N-type epitaxy layer, the first groove
And in the second groove；Metal connecting line hole, it is formed in the dielectric layer；And electrode material, it is filled in the metal and connects
In string holes, the electrode material includes Al layers, AlCu layers, AlSiCu layers, TiN/AlSiCu/TiN/Ti/Ni/Ag laminations, TiN/
In AlSiCu laminations, TiN/AlCu/TiN/Ti/Ni/Ag laminations, TiN/AlCu laminations, TiN/AlSi laminations or TiN/Al laminations
One kind.
As described above, schottky device structure of the present utility model and its manufacture method, have the advantages that：
The utility model, which solves trench schottky device, easily to be influenceed and is produced by external world's test or encapsulation stress
The problem of raw electric leakage is bigger than normal, the advantages of by comprehensive groove-shaped Schottky and Planar Schottky, propose a kind of new Xiao Te
Base device and structure.
The Schottky barrier of plane is converted to vertical stratification by schottky device structure of the present utility model first, makes Xiao Te
Base junction is not positioned immediately on below the metal level of extraneous test and encapsulation, and direct extraneous compression is avoided to reach.
Schottky device structure of the present utility model is relative to traditional groove-shaped Schottky, increase schottky area face
Product, drop low forward conduction voltage VF；And groove structure is utilized, reduces leakage current IR；Simultaneously in test and packaging and routing
Increase dielectric layer among metal and underlying device layer, schottky device is isolated with Top electrode and the external world using dielectric layer, reached
The effect of extraneous stress is buffered, reduces influence of the external compression to schottky junction, external compression is passed through dielectric layer point
It is scattered to whole chip.Meanwhile schottky junction of the present utility model is changed to vertical stratification from planar structure, make additional compression not straight
Connect and be applied to Schottky barrier, while packaging technology window can also be increased.
Brief description of the drawings
Fig. 1 is shown as the structural representation of the schottky device of planar structure of the prior art.
Fig. 2 is shown as the structural representation of the schottky device of groove structure of the prior art.
Fig. 3~Figure 12 is shown as the structure that each step of manufacture method of schottky device structure of the present utility model is presented
Schematic diagram.
Component label instructions
101 N-type epitaxy layers
102 earth silicon masks
103 first grooves
104 second grooves
105 oxide layers
106 polysilicons
107 photoresists
108 the 3rd grooves
109 metal silicides
110 conductive materials
111 dielectric layers
112 metal connecting line holes
113 electrode materials
Embodiment
Illustrate embodiment of the present utility model below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the present utility model easily.The utility model can also be by addition
Different embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With, without departing from it is of the present utility model spirit under carry out various modifications or alterations.
Refer to Fig. 3~Figure 12.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, when the component relevant with the utility model is only shown in illustrating then rather than being implemented according to reality
Component count, shape and size are drawn, and it is actual when implementing kenel, quantity and the ratio of each component can be a kind of changing arbitrarily
Become, and its assembly layout kenel may also be increasingly complex.
As shown in Fig. 3~Figure 12, the present embodiment provides a kind of manufacture method of schottky device structure, the manufacture method
Including：
As shown in figure 3, step 1) is carried out first, in forming multiple first grooves 103 in N-type epitaxy layer 101 and be located at
The second groove 104 of the multiple outer peripheral areas of first groove 103.
As an example, step 1) includes：The substrate (being unillustrated) of a N-type heavy doping is provided, in the substrate surface shape
Into N-type epitaxy layer 101, the N-type epitaxy layer 101 is the silicon epitaxy layer that N-type is lightly doped.In the present embodiment, the N-type is heavily doped
The material of miscellaneous substrate is silicon, and its resistivity is no more than 0.01 ohmcm, and the thickness for the silicon epitaxy layer that the N-type is lightly doped is
Between 2.5~30 μm, concentration 1014~1017/cm3Between.The follow-up first groove 103102 and second groove 104103
It is prepared in the silicon epitaxy layer.
As an example, the earth silicon mask 102 with window is made in the surface of N-type epitaxy layer 101 first, then
Using dry etch process in the N-type epitaxy layer 101 simultaneously formed multiple first grooves 103 and positioned at terminal second
Groove 104, the second groove 104 are used to make terminal decompression ring structure.The width of the first groove 103 is 0.2~1 μ
M, depth are 2.5~10 μm, and specifically, the width of the first groove 103 and second groove 104 is 0.5 μm, and depth is 5 μm.
The flat shape of the first groove 103 can be trap shape, continuous strip, discontinuous strip or be sealing
The shapes such as straight-flanked ring, circular rings.The flat shape of the second groove 104 can be around the multiple first groove 103
Seal loop configuration, or ring-shaped distributed multiple circular configurations etc..
As shown in Fig. 4~Fig. 5, step 2) is then carried out, is formed in the first groove 103 and the surface of second groove 104
Oxide layer 105, and in filling polysilicon 106 in the first groove 103 and second groove 104.
As an example, in step 2), retain above-mentioned earth silicon mask 102, using thermal oxidation process in described first
Groove 103 and the surface of second groove 104 form oxide layer 105, and the thermal oxidation process is in hot stove Guan Zhongjin in the present embodiment
OK, the thickness of the oxide layer 105 is 50nm~1000nm, as shown in Figure 4.
As an example, in step 2), retain above-mentioned earth silicon mask 102, using chemical vapour deposition technique in described
Filling polysilicon 106 in first groove 103 and second groove 104, the doping concentration of the polysilicon 106 is 1019~1021/
cm3, and the polysilicon 106 is returned to the top of the first groove 103 and second groove 104 by quarter using dry etch process
Face, as shown in Figure 5.
As shown in Fig. 6~Fig. 7, then carry out step 3), remove partial polysilicon 106 in the first groove 103 and
Oxide layer 105, the 3rd groove 108 is formed, retains the polysilicon 106 and oxide layer 105 in the second groove 104；
As an example, in step 3), retain above-mentioned earth silicon mask 102, and using photoetching process in described second
Photoresist 107 is formed on groove 104, the earth silicon mask 102 based on above-mentioned reservation, described the is removed using etching technics
Partial polysilicon 106 in one groove 103, the exposed oxidation of the side wall of first groove 103 is then removed using wet etching
Layer 105, to form the 3rd groove 108, the depth of the 3rd groove 108 determines the area of follow-up schottky junction.
As an example, the depth of the 3rd groove 108 is 0.2~0.8 times of the depth of first groove 103.It is preferred that
Ground, the depth of the 3rd groove 108 are 0.4~0.6 times of the depth of first groove 103.In the present embodiment, described
The depth of three grooves 108 is 0.5 times of the depth of first groove 103.The present embodiment is by making the in the first groove 103
Three grooves 108, and schottky junction is made in the side wall of the 3rd groove 108, the area of schottky junction is considerably increased, so as to significantly
Low forward conduction voltage VF is dropped, also, by retaining the oxide layer 105 and polysilicon 106 of the bottom of first groove 103, can be dropped
Low-leakage current IR, so as to the overall performance for improving schottky device structure.
As shown in Fig. 8~Fig. 9, step 4) is then carried out, Schottky is formed in the bottom of the 3rd groove 108 and side wall
Metal level, and anneal and form metal silicide 109.
As an example, step 4) includes：
4-1) retain above-mentioned earth silicon mask 102, using sputtering technology in the bottom and side of the 3rd groove 108
Wall forms schottky metal layer, and the material of the schottky metal layer includes one kind in Pt, Ni, Ti, Cr, W, Mo and Co；
4-2) using schottky metal layer described in the method for quick heat treatment method or furnace annealing and the 3rd groove 108
Bottom and side wall formed metal silicide 109, to form schottky junction；
4-3) utilize NH4OH solution removes the metal that unreacted on the earth silicon mask 102 forms silicide；
4-4) earth silicon mask 102 is removed using chemical mechanical milling tech.
As shown in Figure 10, step 5) is then carried out, in filling conductive material 110 in the 3rd groove 108.
As an example, in step 5), using sputtering, evaporation coating method or its be incorporated into filling in the 3rd groove 108 and lead
Electric material 110, the conductive material 110 include Al layers, AlCu layers, AlSiCu layers, TiN/AlSiCu/TiN/Ti/Ni/Ag and folded
Layer, TiN/AlSiCu laminations, TiN/AlCu/TiN/Ti/Ni/Ag laminations, TiN/AlCu laminations, TiN/AlSi laminations or TiN/Al
One kind in lamination.
Then, the conductive material 110 on the surface of N-type epitaxy layer 101, the institute made are removed using the methods of dry etching, polishing
The top surface and the surface of the N-type epitaxy layer 101 for stating conductive material 110 maintain an equal level.
As shown in Figure 11~Figure 12, step 6) is finally carried out, metal electrode structure in making.
As an example, step 6) includes：
6-1) using chemical vapour deposition technique in the N-type epitaxy layer 101, the first groove 103 and second ditch
Dielectric layer 111 is formed on groove 104, in the present embodiment, the material selection of the dielectric layer 111 is silica；
Metal connecting line hole 112 6-2) is opened in the dielectric layer 111 using photo etching process；
6-3) using sputtering, evaporation coating method or its be incorporated into filling electrode material 113, institute in the metal connecting line hole 112
Stating electrode material 113 includes Al layers, AlCu layers, AlSiCu layers, TiN/AlSiCu/TiN/Ti/Ni/Ag laminations, TiN/AlSiCu
One kind in lamination, TiN/AlCu/TiN/Ti/Ni/Ag laminations, TiN/AlCu laminations, TiN/AlSi laminations or TiN/Al laminations.
The utility model increases dielectric layer 111 among the metal and underlying device layer of test and packaging and routing, utilizes Jie
Matter layer 111 isolates schottky device with Top electrode and the external world, has the function that to buffer extraneous stress, reduces external compression
Influence to schottky junction, external compression is set to be distributed to whole chip by dielectric layer 111.Meanwhile Xiao of the present utility model
Special base junction is changed to vertical stratification from planar structure, additional compression is not applied directly to Schottky barrier, while can also increase
Big packaging technology window.
As shown in figure 12, the present embodiment also provides a kind of schottky device structure, including：N-type epitaxy layer 101, the N-type
Second groove in epitaxial layer 101 formed with multiple first grooves 103 and positioned at the multiple outer peripheral areas of first groove 103
104；Oxide layer 105, it is formed at first groove 103 and second groove 104 surface；Polysilicon 106, it is filled in described first
In groove 103 and second groove 104；3rd groove 108, remove the partial polysilicon 106 in the first groove 103 and oxidation
Layer 105 forms；Metal silicide 109, bottom and the side wall of the 3rd groove 108 are formed at, to form schottky junction；It is conductive
Material 110, it is filled in the 3rd groove 108；And upper metal electrode structure.
As an example, the thickness of the oxide layer 105 is 50nm~1000nm, the doping concentration of the polysilicon 106 is
1019~1021/cm3。
As an example, the depth of the 3rd groove 108 is 0.2~0.8 times of the depth of first groove 103.It is preferred that
Ground, the depth of the 3rd groove 108 are 0.5~0.6 times of the depth of first groove 103.In the present embodiment, described
The depth of three grooves 108 is 0.5 times of the depth of first groove 103.The present embodiment is by making the in the first groove 103
Three grooves 108, and schottky junction is made in the side wall of the 3rd groove 108, the area of schottky junction is considerably increased, so as to significantly
Low forward conduction voltage VF is dropped, also, by retaining the oxide layer 105 and polysilicon 106 of the bottom of first groove 103, can be dropped
Low-leakage current IR, so as to the overall performance for improving schottky device structure.
As an example, the metal material of the metal silicide 109 includes one kind in Pt, Ni, Ti, Cr, W, Mo and Co.
As an example, as an example, the conductive material 110 includes Al layers, AlCu layers, AlSiCu layers, TiN/AlSiCu/
TiN/Ti/Ni/Ag laminations, TiN/AlSiCu laminations, TiN/AlCu/TiN/Ti/Ni/Ag laminations, TiN/AlCu laminations, TiN/
One kind in AlSi laminations or TiN/Al laminations.
Preferably, the upper metal electrode structure includes：Dielectric layer 111, it is formed at the N-type epitaxy layer 101, described
On one groove 103 and the second groove 104；Metal connecting line hole 112, it is formed in the dielectric layer 111；And electrode material
113, it is filled in the metal connecting line hole 112, the electrode material 113 includes Al layers, AlCu layers, AlSiCu layers, TiN/
AlSiCu/TiN/Ti/Ni/Ag laminations, TiN/AlSiCu laminations, TiN/AlCu/TiN/Ti/Ni/Ag laminations, TiN/AlCu are folded
One kind in layer, TiN/AlSi laminations or TiN/Al laminations.The utility model is in the metal of test and packaging and routing and lower section device
Increase dielectric layer 111 among part layer, schottky device is isolated with Top electrode and the external world using dielectric layer 111, it is outer to reach buffering
The effect of boundary's stress, influence of the external compression to schottky junction is reduced, external compression is distributed to by dielectric layer 111
Whole chip.Meanwhile schottky junction of the present utility model is changed to vertical stratification from planar structure, additional compression is set not make directly
Schottky barrier is used, while packaging technology window can also be increased.
As described above, schottky device structure of the present utility model and its manufacture method, have the advantages that：
The utility model, which solves trench schottky device, easily to be influenceed and is produced by external world's test or encapsulation stress
The problem of raw electric leakage is bigger than normal, the advantages of by comprehensive groove-shaped Schottky and Planar Schottky, propose a kind of new Xiao Te
Base device and structure.
The Schottky barrier of plane is converted to vertical stratification by schottky device structure of the present utility model first, makes Xiao Te
Base junction is not positioned immediately on below the metal level of extraneous test and encapsulation, and direct extraneous compression is avoided to reach.
Schottky device structure of the present utility model is relative to traditional groove-shaped Schottky, increase schottky area face
Product, drop low forward conduction voltage VF；And groove structure is utilized, reduces leakage current IR；Simultaneously in test and packaging and routing
Increase dielectric layer 111 among metal and underlying device layer, using dielectric layer 111 by schottky device and Top electrode and it is extraneous every
From, have the function that buffer extraneous stress, reduce influence of the external compression to schottky junction, external compression is passed through Jie
Matter layer 111 is distributed to whole chip.Meanwhile schottky junction of the present utility model is changed to vertical stratification from planar structure, make additional
Compression is not applied directly to Schottky barrier, while can also increase packaging technology window.
So the utility model effectively overcomes various shortcoming of the prior art and has high industrial utilization.
Above-described embodiment only illustrative principle of the present utility model and its effect are new not for this practicality is limited
Type.Any person skilled in the art can all be carried out without prejudice under spirit and scope of the present utility model to above-described embodiment
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the essence disclosed in the utility model
God and all equivalent modifications completed under technological thought or change, should be covered by claim of the present utility model.
Claims (7)
- A kind of 1. schottky device structure, it is characterised in that including：N-type epitaxy layer, formed with multiple first grooves and positioned at the multiple first groove external zones in the N-type epitaxy layer The second groove in domain；Oxide layer, it is formed at first groove and the second groove surface；Polysilicon, it is filled in the first groove and second groove；3rd groove, removes the partial polysilicon in the first groove and oxide layer forms；Metal silicide, bottom and the side wall of the 3rd groove are formed at, to form schottky junction；Conductive material, it is filled in the 3rd groove；AndUpper metal electrode structure.
- 2. schottky device structure according to claim 1, it is characterised in that：The thickness of the oxide layer be 50nm~ 1000nm, the doping concentration of the polysilicon is 1019~1021/cm3。
- 3. schottky device structure according to claim 1, it is characterised in that：The depth of 3rd groove is described the 0.2~0.8 times of one gash depth.
- 4. schottky device structure according to claim 3, it is characterised in that：The depth of 3rd groove is described the 0.5~0.6 times of one gash depth.
- 5. schottky device structure according to claim 1, it is characterised in that：The metal material bag of the metal silicide Include one kind in Pt, Ni, Ti, Cr, W, Mo and Co.
- 6. schottky device structure according to claim 1, it is characterised in that：The conductive material includes Al layers, AlCu Layer, AlSiCu layers, TiN/AlSiCu/TiN/Ti/Ni/Ag laminations, TiN/AlSiCu laminations, TiN/AlCu/TiN/Ti/Ni/Ag One kind in lamination, TiN/AlCu laminations, TiN/AlSi laminations or TiN/Al laminations.
- 7. schottky device structure according to claim 1, it is characterised in that：The upper metal electrode structure includes：Dielectric layer, it is formed in the N-type epitaxy layer, the first groove and the second groove；Metal connecting line hole, it is formed in the dielectric layer；Electrode material, it is filled in the metal connecting line hole, the electrode material includes Al layers, AlCu layers, AlSiCu layers, TiN/ AlSiCu/TiN/Ti/Ni/Ag laminations, TiN/AlSiCu laminations, TiN/AlCu/TiN/Ti/Ni/Ag laminations, TiN/AlCu are folded One kind in layer, TiN/AlSi laminations or TiN/Al laminations.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720655357.2U CN207009443U (en) | 2017-06-07 | 2017-06-07 | Schottky device structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201720655357.2U CN207009443U (en) | 2017-06-07 | 2017-06-07 | Schottky device structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109004035A (en) * | 2017-06-07 | 2018-12-14 | 中航（重庆）微电子有限公司 | Schottky device structure and its manufacturing method |
| CN109300799A (en) * | 2018-11-19 | 2019-02-01 | 北京燕东微电子科技有限公司 | Semiconductor structure, test macro, the production method of test method and semiconductor structure |
-
2017
- 2017-06-07 CN CN201720655357.2U patent/CN207009443U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109004035A (en) * | 2017-06-07 | 2018-12-14 | 中航（重庆）微电子有限公司 | Schottky device structure and its manufacturing method |
| CN109004035B (en) * | 2017-06-07 | 2024-02-13 | 华润微电子（重庆）有限公司 | Schottky device structure and manufacturing method thereof |
| CN109300799A (en) * | 2018-11-19 | 2019-02-01 | 北京燕东微电子科技有限公司 | Semiconductor structure, test macro, the production method of test method and semiconductor structure |
| CN109300799B (en) * | 2018-11-19 | 2024-02-02 | 北京燕东微电子科技有限公司 | Semiconductor structure, test system, test method and manufacturing method of semiconductor structure |
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