CN109300799B - Semiconductor structure, test system, test method and manufacturing method of semiconductor structure - Google Patents
Semiconductor structure, test system, test method and manufacturing method of semiconductor structure Download PDFInfo
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- CN109300799B CN109300799B CN201811373008.7A CN201811373008A CN109300799B CN 109300799 B CN109300799 B CN 109300799B CN 201811373008 A CN201811373008 A CN 201811373008A CN 109300799 B CN109300799 B CN 109300799B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 154
- 238000012360 testing method Methods 0.000 title claims abstract description 131
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000010998 test method Methods 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 210000000746 body region Anatomy 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 238000005468 ion implantation Methods 0.000 claims description 21
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- 238000011049 filling Methods 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 abstract description 4
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- 238000000137 annealing Methods 0.000 description 3
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- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Abstract
The application discloses a semiconductor structure, a testing system, a testing method and a manufacturing method of the semiconductor structure. The semiconductor structure includes: a substrate; a doped layer formed on the first surface of the substrate; and a plurality of trenches, each trench extending through the doped layer and into the substrate, wherein the plurality of trenches includes at least one first trench and at least one second trench, each second trench for forming a gate of a respective semiconductor device, each first trench defining and isolating the test region having a closed loop boundary in the doped layer. The semiconductor structure forms the test region while forming the semiconductor device, and the test region comprises the doped layer and the first groove penetrating through the doped layer, so that the doped layer has a clear boundary, key parameters such as the body region resistance of the semiconductor device can be more accurately represented, and the yield and the reliability of products are improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and more particularly, to a semiconductor structure, a test system, a test method, and a method for manufacturing a semiconductor structure.
Background
A Metal-Oxide-semiconductor field effect transistor (MOSFET) is a voltage control element, abbreviated as MOS transistor. The MOS tube is suitable for the condition that only less current is allowed to be acquired from a signal source; under the condition that the signal voltage is lower and more current is allowed to be obtained from the signal source, a bipolar transistor is adopted. The substrate or well is also called as a Body of the MOS transistor, the MOS transistor can work under the condition of very small current and very low voltage, and the manufacturing process can integrate a plurality of field effect transistors on a silicon wafer very conveniently, so that the MOS transistor is widely applied to large-scale integrated circuits.
A Vertical Double-diffused metal-oxide semiconductor field effect transistor (VDMOS) has the advantages of both a bipolar transistor and a normal MOS device. Compared with a bipolar transistor, the switching speed and the switching loss of the bipolar transistor are small; the input impedance is high, and the driving power is low; the frequency characteristic is good; the transconductance is highly linear. And it has negative temperature coefficient, no secondary breakdown problem of power transistor, and large safe working area. Thus, VDMOS is an ideal power device, whether for switching applications or linear applications. Trench VDMOS has special device structures, such as processes of shorting Source and body regions, maskless implantation of body regions, maskless back etching of Gate polysilicon (Gate poly), etc., using conductive structures to improve device performance or reduce manufacturing cost.
During the chip manufacturing process, manufacturers often need to monitor various electrical parameters of the devices to determine whether the process is normal. The body resistance of a semiconductor device is a very important parameter, and has a very important effect on many characteristics of the device. Therefore, measurement of body resistance is very important. However, the above process makes it impossible to measure and extract parameters of borderless structures during the manufacturing process of the device, which results in reduced success rate of development and increased cost.
It is therefore desirable to design an effective test area in a semiconductor structure for process parameter and device parameter extraction.
Disclosure of Invention
In view of the foregoing, an object of the present invention is to provide a semiconductor structure, a testing system, a testing method, and a method for manufacturing a semiconductor structure, where the semiconductor structure includes a semiconductor device and a testing region, and the testing region includes a doped layer and a first trench penetrating through the doped layer, so that the doped layer has a clear boundary, and it is convenient to more accurately characterize key parameters such as a body resistance of the semiconductor device.
According to an aspect of the present invention, there is provided a semiconductor structure for forming at least one semiconductor device and at least one test region, characterized in that the semiconductor structure comprises: a substrate; a doped layer formed on the first surface of the substrate; and a plurality of trenches, each trench extending through the doped layer and into the substrate, wherein the plurality of trenches includes at least one first trench and at least one second trench, each second trench for forming a gate of a respective semiconductor device, each first trench defining and isolating the test region having a closed loop boundary in the doped layer.
Preferably, the semiconductor structure has an inactive area and an active area, the at least one semiconductor device is located in the active area, and the at least one test area is located in the inactive area.
Preferably, the inactive area corresponds to a scribe line location of the semiconductor structure.
Preferably, the semiconductor structure further comprises: a dielectric layer formed on the exposed surface of each trench; and polysilicon filled in each groove.
Preferably, the doped layer located in the active area forms a body region of the corresponding semiconductor device, the dielectric layer located in the active area forms a gate dielectric layer of the corresponding semiconductor device, and the polysilicon located in the active area forms a gate of the corresponding semiconductor device.
Preferably, the method further comprises: and the dielectric layer is positioned on the doped layer.
Preferably, the method further comprises: and a plurality of conductive structures extending through the dielectric layer and into the doped layer, each conductive structure electrically connected to a corresponding test region, thereby leading out a test node for detecting an electrical parameter of the test region.
Preferably, each of the test areas has two of the test nodes, respectively.
Preferably, the test area is defined as a closed area by the corresponding first grooves, and the two test nodes are respectively positioned at two ends of the test area and are not in contact with the first grooves.
Preferably, the method further comprises: pads located over the dielectric layer, each of the pads being respectively contiguous with a respective one of the conductive structures, thereby connecting the test node of the respective test region to a test circuit.
According to another aspect of the present invention, there is provided a test system for a semiconductor structure, comprising: a semiconductor structure as described above; and the test circuit is electrically connected with the test area and obtains the electrical parameters of the semiconductor device by detecting the electrical parameters of the test area.
According to another aspect of the present invention, there is provided a method for testing a semiconductor device, comprising: forming a doped layer in a first surface of a substrate; forming a plurality of trenches, each of the trenches extending through the doped layer and into the substrate, the plurality of trenches including at least one first trench and at least one second trench, each of the second trenches for forming a gate of a respective semiconductor device, each of the first trenches defining and isolating the test region having a closed-loop boundary in the doped layer; and obtaining corresponding parameters of the semiconductor device by measuring the electrical parameters of the test area.
According to another aspect of the present invention, there is provided a method of fabricating a semiconductor structure for forming at least one semiconductor device and at least one test region, the method comprising: providing a substrate; forming a doped layer on the first surface of the substrate; and forming a plurality of trenches, each trench extending through the doped layer and into the substrate, wherein the plurality of trenches includes at least one first trench and at least one second trench, each second trench for forming a gate of a respective semiconductor device, each first trench defining and isolating the test region having a closed-loop boundary in the doped layer.
Preferably, the semiconductor structure has an inactive area and an active area, the at least one semiconductor device is located in the active area, and the at least one test area is located in the inactive area.
Preferably, the inactive area corresponds to a scribe line location of the semiconductor structure.
Preferably, the method further comprises: forming a dielectric layer on the exposed surface of each groove; and forming polysilicon, and filling the inside of each groove.
Preferably, the doped layer located in the active area forms a body region of the corresponding semiconductor device, the dielectric layer located in the active area forms a gate dielectric layer of the corresponding semiconductor device, and the polysilicon located in the active area forms a gate of the corresponding semiconductor device.
Preferably, the method further comprises: a dielectric layer is formed over the doped layer.
Preferably, the method further comprises: a plurality of conductive structures are formed through the dielectric layer and extending into the doped layer, each of the conductive structures being electrically connected to a respective one of the test regions, thereby leading out a test node for detecting an electrical parameter of the test region.
Preferably, each of the test areas has two of the test nodes, respectively.
Preferably, the test area is defined as a closed area by the corresponding first grooves, and the two test nodes are respectively positioned at two ends of the test area and are not in contact with the first grooves.
Preferably, the method further comprises: pads are formed over the dielectric layer, each of the pads being respectively adjacent to a respective one of the conductive structures, thereby connecting the test node of the respective test region to a test circuit.
Preferably, the method of forming the doped layer includes: and carrying out ion implantation in the substrate, wherein the depth of the ion implantation does not exceed the depth of the groove, and the type of the ion implantation dopant comprises an N-type dopant or a P-type dopant.
Preferably, the method of performing ion implantation includes ion implantation using a mask or ion implantation without using a mask.
The semiconductor structure comprises the semiconductor device and the test region, and the test region comprises the doped layer and the groove penetrating through the doped layer, so that the doped layer in the test region has a definite boundary, and parameters such as the body region resistance of the MOS semiconductor device can be measured. In the prior art, there are special device structures in the Trench VDMOS, such as processes of shorting a Source (Source) and a body region, maskless implantation of the body region, maskless back etching (Etch back) of Gate polysilicon (Gate poly), and the like, by using a conductive structure, so as to improve the device performance or reduce the manufacturing cost. However, the above-described process setup makes the device lacking a well-defined test area for extracting and monitoring process parameters during the manufacturing process, which results in reduced success rate of development and increased cost. The test area of the embodiment of the invention can provide an effective test structure for extracting and monitoring the process parameters of the borderless structure, thereby improving the yield and the reliability of the product.
Furthermore, the semiconductor structure provided by the invention can be compatible with most processes and has universality.
Furthermore, the semiconductor structure provided by the invention does not need to add an extra mask when forming the test area, and can provide an effective test area without increasing the cost and the process complexity.
Further, the test area in the semiconductor structure provided by the invention does not occupy the effective area on the wafer, so that the additional cost is not increased.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a perspective view of a semiconductor structure provided according to an embodiment of the present invention.
Fig. 2 shows a top view of a semiconductor structure provided in accordance with an embodiment of the present invention.
Fig. 3 illustrates a top view of a test region in a semiconductor structure provided in accordance with an embodiment of the present invention.
Fig. 4a to 4j show cross-sectional views of various stages of a method of manufacturing a test region in a semiconductor structure according to an embodiment of the invention.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of embodiments of the invention, certain specific details are set forth in order to provide a thorough understanding of the invention. Well-known processes and procedures have not been described in detail so as not to obscure the present invention.
Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings. The flowcharts, block diagrams in the figures illustrate the possible architecture, functionality, and operation of systems, devices according to embodiments of the present invention, and the order of the blocks in the figures are merely for better illustrating the processes and steps of the embodiments, and should not be taken as limiting the invention itself.
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.
It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.
If, for the purposes of describing a situation directly on top of another layer, another region, the expression "a directly on top of B" or "a directly on top of B and adjoining it" will be used herein. In this application, "a is directly in B" means that a is in B and a is directly adjacent to B, rather than a being in the doped region formed in B.
In this application, the term "semiconductor structure" refers to a generic term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed. Hereinafter, unless otherwise indicated, "semiconductor structure" refers to an intermediate structure that includes a test region and a semiconductor device.
Numerous specific details of the invention, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 1 shows a perspective view of a semiconductor structure according to an embodiment of the present invention.
As shown in fig. 1, the semiconductor structure provided in the embodiment of the invention includes a test region and a semiconductor device, where the test region and the semiconductor device are formed on a wafer at the same time.
The test region includes a first semiconductor substrate 101, a first doped layer 102, a dielectric layer 103 (see fig. 4 j), a pad 104 (see fig. 4 j), a first conductive structure 105, and an isolation layer 106. The first semiconductor substrate 101, the first doped layer 102, the dielectric layer 103 and the bonding pad 104 are stacked in sequence, and the isolation layer 106 is in a closed loop structure and extends from the inside of the first semiconductor substrate 101 to the interface between the first doped layer 102 and the dielectric layer 103. In this embodiment, the isolation layer 106 comprises trenches and dielectric layers and polysilicon inside the trenches, the test region is defined by the respective trenches as an enclosed region, the isolation layer 106 is for example in the shape of an enclosed dumbbell, the isolation layer 106 is for example composed of or formed by a dielectric layer and doped polysilicon. The isolation layer 106 includes a first conductive structure 105 inside, the first conductive structure 105 extending from inside the first doped layer 102 to the interface of the dielectric layer 103 and the pad 104.
The semiconductor device includes a second semiconductor substrate 201, a second doped layer 202, a second gate dielectric layer 207, a dielectric layer (not shown), a pad (not shown), a second conductive structure 205, a source region 210, and a gate 206. The second semiconductor substrate 201 is adjacent to the second doped layer 202, the source region 210 is located in the second doped layer 202, the surface of the second doped layer is covered with a second gate dielectric layer 207, a gate 206 is included above the second gate dielectric layer, the gate 206 is located between the two source regions 210, the source regions 210 are connected to an extraction electrode, in this embodiment, for example, the second conductive structure 205, and the surface of the gate 206 is further covered with a dielectric layer for preventing a short circuit between the source 210 and the gate 206.
However, the present invention is not limited thereto, and the semiconductor device 200 may be any semiconductor device including a Body region (Body) in the prior art, and the test region 100 and the semiconductor device 200 in the present invention are formed simultaneously, the test region 100 is located in an inactive region of the wafer, the semiconductor device 200 is located in an active region of the wafer, and the test region 100 is used to test critical parameters such as Body resistance in the semiconductor device 200.
Fig. 2 shows a top view of a semiconductor structure provided in accordance with an embodiment of the present invention.
As shown in fig. 2, the test area 100 is located in an inactive area of the wafer 300 and the semiconductor device 200 is located in an active area of the wafer 300.
Fig. 3 illustrates a top view of a test region in a semiconductor structure provided in accordance with an embodiment of the present invention.
As shown in fig. 3, in this embodiment, the isolation layer 106 isolates the first doped layer 102 into a doped layer 102a and a doped layer 102b. The doped layer 102a has a well-defined boundary, and in the subsequent process, parameters such as the body resistance of the doped layer 102a can be measured by using an extraction electrode, so as to provide a test area for extracting device parameters. In this embodiment, the first conductive structure 105 is used as an extraction electrode, for example, to connect to an external circuit to test the body resistance.
Fig. 4a to 4j show cross-sectional views of the semiconductor structure at various stages of the method of manufacturing the test region, taken along line AA in fig. 1, in a cut-away position through the isolation layer 106 and the first conductive structure 105, in accordance with an embodiment of the present invention. Only the cross-sectional views of the test region 100 at various stages of the manufacturing method are shown, and it should be understood that the test region 100 and the semiconductor device 200 are formed simultaneously, and the constituent components of the test region 100 correspond to those of the semiconductor device 200, but the shape, size, position, etc. of the two are different, and the test region 100 is used to test parameters such as body resistance in the semiconductor device 200.
The invention starts with providing a first semiconductor substrate 101 as shown in fig. 4 a.
The first semiconductor substrate 101 is located in an inactive area of the wafer 300. The first semiconductor substrate 101 is, for example, a P-type or N-type semiconductor layer or region, and a corresponding type of dopant may be doped in the semiconductor layer and region, for example, the P-type dopant includes boron, and the N-type dopant includes phosphorus or arsenic or antimony. In this embodiment, the first semiconductor substrate 101 is a heavily doped N-type substrate, the dopant is arsenic, and the specific doping concentration is the prior art, and may be selected according to practical requirements.
While a second semiconductor substrate 201 is provided in the active area of the substrate, the second semiconductor substrate 201 being located in the active area of the wafer 300. The second semiconductor substrate 201 is the same material as the first semiconductor substrate 101.
Further, a plurality of first trenches 110 are formed in the first semiconductor substrate 101, as shown in fig. 4 b.
The first trench 110 has a closed-loop structure in cross-sectional shape, as viewed in a direction perpendicular to the first semiconductor substrate 101, with a certain space inside the loop. In a preferred embodiment, the annular structure of the first groove 110 is a closed dumbbell-shaped annular structure. As will be described below, the first semiconductor substrate 101 is ion-implanted to form a first doped layer 102, and a first trench 110 is located in the first doped layer 102 and extends through the first doped layer 102 to define and isolate the first doped layer into at least one test region having a closed-loop boundary. Methods of forming the first trenches 110 include photolithography or anisotropic etching methods, such as dry etching, e.g., ion milling, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time, etching is stopped inside the first semiconductor substrate 101.
Meanwhile, a trench is formed in the second semiconductor substrate 201, and is used for forming a gate dielectric layer and a gate of the semiconductor device.
Further, a first gate dielectric layer 107 is formed on the surface of the semiconductor structure, as shown in fig. 4 c.
The first gate dielectric layer 107 is located on the upper surface of the semiconductor structure and the surface of the first trench 110, for example, a thermal oxidation method is used to form the first gate dielectric layer 107, and the first gate dielectric layer 107 is, for example, silicon oxide.
A second gate dielectric layer 207 is formed in the trench in the second semiconductor substrate 201 at the same time, the second gate dielectric layer 207 being formed at the same time as the first gate dielectric layer 107, and being of the same material.
Further, polysilicon 112 is formed within the first trench 110, as shown in fig. 4 d.
The polysilicon 112 is formed inside the first trench 110 and fills the first trench 110 sufficiently, for example, by atomic layer deposition (Atomic Layer Deposition, ALD), physical vapor deposition (Physical Vapor Deposition, PVD) or chemical vapor deposition (Chemical Vapor Deposition, CVD), to form the polysilicon 112, and the polysilicon 112 is, for example, P-type ion doped polysilicon.
A gate 206 is formed over the second gate dielectric layer at the same time, the gate 206 being formed of the same material as the polysilicon 112.
Further, the planarization process is performed on the polysilicon 112 located on the semiconductor surface, so that the surface of the polysilicon 112 in the first trench 110 is leveled with the surface of the first semiconductor substrate 101, the polysilicon 112 in the first trench 110 is remained, and the trench 110, the first gate dielectric layer 107 in the trench 110 and the polysilicon 112 together form the isolation layer 106, as shown in fig. 4 e.
The isolation layer 106 has a closed-loop structure in cross-sectional shape, as viewed in a direction perpendicular to the first semiconductor substrate 101, with a certain space inside the loop. In a preferred embodiment, the annular structure of the spacer layer 106 is a closed dumbbell-shaped annular structure. As will be described below, the first semiconductor substrate 101 is subjected to ion implantation to form a first doped layer 102, and an isolation layer 106 is located in the first doped layer 102, and an inside surrounded by the isolation layer 106 includes a doped layer 102a, and the inside of the doped layer 102a is connected to the first conductive structure 105. The surface of the polysilicon 112 is etched using an anisotropic etching process, such as a dry etch, e.g., ion milling, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time, etching is stopped near the surface of the first semiconductor substrate 101. Preferably, after dry etching, chemical mechanical polishing (Chemical Mechanical Polishing, CMP) is used to planarize the semiconductor surface.
Further, ion implantation is performed in the first semiconductor substrate 101 to form a first doped layer 102, as shown in fig. 4 f.
In forming the first doping layer 102 by ion implantation, a mask may be used or not. For example, the mask is used for ion implantation, the shape of the mask plate is designed according to the requirement, and then the ion implantation is performed at an inclined angle through the mask plate, in this embodiment, the N ion implantation is controlled to be performed into the N-type first semiconductor substrate 101, so that a doped N-type first doped layer 102 is formed, and the depth of the first doped layer 102 does not exceed the depth of the trench 110. However, the present invention is not limited thereto, and the first doped layer 102 may be formed by implanting ions of different ion species, energies and doses to an appropriate depth using a plurality of ion implantation processes. Preferably, after ion implantation, an annealing treatment, for example a rapid thermal annealing treatment, is used, the annealing temperature being for example 1000 to 1100 ℃, and the annealing time being for example 1 to 60 seconds.
At the same time, ion implantation is performed in the second semiconductor substrate 201 to form a second doped layer 202, where the second doped layer 202 is the body region of the semiconductor device. The second doped layer 202 is formed simultaneously with the first doped layer 102 and is the same material, thereby achieving the purpose of testing the body resistance of the semiconductor device by testing the resistance of the first doped layer 102.
Further, a Dielectric Layer (ILD) 103 is formed on the semiconductor structure surface, as shown in fig. 4 g. For example, atomic layer deposition, physical vapor deposition or chemical vapor deposition is used to form the dielectric layer 103, and the dielectric layer 103 is, for example, a silicon dioxide layer or borophosphosilicate glass. A dielectric layer (not shown) is formed on the surface of the gate electrode 206 to prevent a short circuit between the source electrode 210 and the gate electrode 206.
Further, at least two contact holes 111 are formed in the semiconductor structure, as shown in fig. 4 h.
The contact hole 111 extends from the inside of the first doped layer 102 to the surface of the semiconductor structure, penetrating through the dielectric layer 103. Methods of forming the contact hole 111 include photolithography or anisotropic etching methods, for example, dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time, etching is stopped inside the first doped layer 102. At the same time, a contact hole is formed in the dielectric layer on the surface of the gate 206, for forming the second conductive structure 205.
Further, a first conductive structure 105 is formed within the contact hole 111, as shown in fig. 4 i.
The first conductive structure 105 extends from inside the first doped layer 102 to the surface of the semiconductor structure and penetrates the dielectric layer 103. Each first conductive structure 105 is electrically connected to a respective one of the test zones, thereby leading out a test node for detecting an electrical parameter of the test zone. The test nodes are located at the front and rear ends of the test region and do not contact the first trench 110. The first conductive structure 105 is, for example, a tungsten plug. The first conductive structure 105 is formed by atomic layer deposition, physical vapor deposition or chemical vapor deposition. Meanwhile, a second conductive structure 205 is formed in a contact hole in a dielectric layer on the surface of the gate 206, and a method of forming the second conductive structure 205 is the same as that of forming the first conductive structure 105.
Further, a pad 104 is formed on the semiconductor structure surface, as shown in fig. 4 j.
The pads 104 are in close proximity to the first conductive structures 105, thereby connecting the test nodes of the respective test areas to the test circuit. The bonding pad 104 is formed, for example, by atomic layer deposition, physical vapor deposition or chemical vapor deposition, and the bonding pad 104 is, for example, tungsten or aluminum. The shape, size and thickness of the bonding pad can be selected according to the requirement.
In this embodiment, a test system for a semiconductor structure includes the semiconductor structure and a test circuit. In the test region 100 of the semiconductor structure, the first trench 110 forms a closed loop structure, and the doped layer 102a is formed around the first doped layer 102, such that the doped layer 102a has a boundary of a closed loop boundary, and finally a test region with a test node is formed. The test area is electrically connected to the test circuit through the conductive structure and the test node, and the test circuit obtains the electrical parameters of the semiconductor device by detecting the electrical parameters of the test area.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, article or apparatus that comprises the element.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (15)
1. A semiconductor structure for forming at least one semiconductor device and at least one test region, wherein the semiconductor structure has an inactive area and an active area, the at least one semiconductor device being located in the active area, the at least one test region being located in the inactive area, the inactive area corresponding to a scribe line location of the semiconductor structure; the semiconductor structure includes:
a substrate;
a doped layer formed on the first surface of the substrate;
a plurality of trenches, each of the trenches extending through the doped layer and into the substrate;
a dielectric layer over the doped layer; and
a plurality of conductive structures extending through the dielectric layer and into the doped layer,
wherein the plurality of trenches includes at least one first trench and at least one second trench, each second trench for forming a gate of a respective semiconductor device, each first trench defining and isolating the test region having a closed loop boundary in the doped layer; the test area is limited by the corresponding first groove to be a closed area, and the closed area is dumbbell-shaped;
each of the conductive structures is electrically connected to a corresponding one of the test zones, thereby leading out a test node for detecting an electrical parameter of the test zone.
2. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:
a dielectric layer formed on the exposed surface of each trench; and
and polysilicon filled in each groove.
3. The semiconductor structure of claim 2, wherein,
the doped layers located within the active regions form body regions of the respective semiconductor devices,
the dielectric layer located in the active area forms a gate dielectric layer of the corresponding semiconductor device,
the polysilicon located within the active area forms a gate of the corresponding semiconductor device.
4. The semiconductor structure of claim 1, wherein each of said test regions has two of said test nodes.
5. The semiconductor structure of claim 4, wherein two of the test nodes are located at opposite ends of the test region and are not in contact with the first trench.
6. The semiconductor structure of claim 1, further comprising: pads located over the dielectric layer, each of the pads being respectively contiguous with a respective one of the conductive structures, thereby connecting the test node of the respective test region to a test circuit.
7. A system for testing a semiconductor structure, comprising:
the semiconductor structure of any one of claims 1 to 6; and
and the test circuit is electrically connected with the test area and obtains the electrical parameters of the semiconductor device by detecting the electrical parameters of the test area.
8. A method for fabricating a semiconductor structure for forming at least one semiconductor device and at least one test region, wherein the semiconductor structure has an inactive region and an active region, the at least one semiconductor device is located in the active region, the inactive region corresponds to a scribe line location of the semiconductor structure, and the at least one test region is located in the inactive region;
the manufacturing method comprises the following steps:
providing a substrate;
forming a doped layer on the first surface of the substrate;
forming a plurality of trenches, each of which penetrates through the doped layer and extends into the substrate;
forming a dielectric layer over the doped layer; and
forming a plurality of conductive structures extending through the dielectric layer and into the doped layer,
wherein the plurality of trenches includes at least one first trench and at least one second trench, each second trench for forming a gate of a respective semiconductor device, each first trench defining and isolating the test region having a closed loop boundary in the doped layer;
the test area is limited by the corresponding first groove to be a closed area, and the closed area is dumbbell-shaped;
each of the conductive structures is electrically connected to a corresponding one of the test zones, thereby leading out a test node for detecting an electrical parameter of the test zone.
9. The method of manufacturing of claim 8, further comprising:
forming a dielectric layer on the exposed surface of each groove; and
and forming polycrystalline silicon, and filling the inside of each groove.
10. The method of claim 9, wherein,
the doped layers located within the active regions form body regions of the respective semiconductor devices,
the dielectric layer located in the active area forms a gate dielectric layer of the corresponding semiconductor device,
the polysilicon located within the active area forms a gate of the corresponding semiconductor device.
11. The method of claim 8, wherein each test area has two of the test nodes.
12. The method of claim 11, wherein two of the test nodes are located at opposite ends of the test region and are not in contact with the first trench.
13. The method of manufacturing of claim 8, further comprising: pads are formed over the dielectric layer, each of the pads being respectively adjacent to a respective one of the conductive structures, thereby connecting the test node of the respective test region to a test circuit.
14. The method of claim 8, wherein the forming the doped layer comprises: and carrying out ion implantation in the substrate, wherein the depth of the ion implantation does not exceed the depth of the groove, and the type of the ion implantation dopant comprises an N-type dopant or a P-type dopant.
15. The method of claim 14, wherein the ion implantation comprises ion implantation using a mask or ion implantation without a mask.
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| CN112259527A (en) * | 2020-10-21 | 2021-01-22 | 北京燕东微电子科技有限公司 | Test structure of wafer |
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