CN209434179U - Semiconductor structure and test macro - Google Patents

Abstract

This application discloses a kind of semiconductor structure and test macros.The semiconductor structure includes: substrate；Multiple grooves in the substrate；Dielectric layer is formed in the exposed surface of each groove；And polysilicon, it is filled in each trench interiors, wherein, the multiple groove includes at least one first groove and at least one second groove, it is filled in the grid that the polysilicon inside the second groove forms the semiconductor devices, each first groove has closed loop side wall, and the polysilicon in the first groove forms the test island for having closed loop boundary and being isolated with the substrate.The semiconductor structure forms test island while forming semiconductor devices, it include the polysilicon with closed loop boundary in test island, more accurate characterization is carried out convenient for key parameters such as grid resistances to semiconductor devices, to improve the yield and reliability of product.

Description

Semiconductor structure and test macro

Technical field

The utility model relates to technical field of manufacturing semiconductors, are more particularly, to a kind of semiconductor structure and test System.

Background technique

Metal Oxide Semiconductor Field Effect Transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) it is a kind of voltage controlled element, abbreviation metal-oxide-semiconductor.Metal-oxide-semiconductor is suitable for only allowing to obtain from signal source The case where less electric current；And it is lower in signal voltage, and allow to select bipolar under conditions of the more electric current of signal source acquisition Transistor.Substrate or trap are also referred to as " body " (Body) of metal-oxide-semiconductor, and metal-oxide-semiconductor can be under conditions of very little electric current and very low-voltage Work, and its manufacturing process can easily be integrated in many field-effect tube on one piece of silicon wafer, therefore metal-oxide-semiconductor is big It is widely used in scale integrated circuit.

Vertical double diffused metal-oxide semiconductor field effect transistor (Vertical Double-diffused MOSFET, VDMOS) the advantages of having bipolar transistor and common MOS device concurrently.Compared with bipolar transistor, its switching speed, Switching loss is small；Input impedance is high, and driving power is small；Frequency characteristic is good；Mutual conductance highly linear.Also, it has negative temperature Coefficient, the second breakdown problem of power transistor, safety operation area be not big.Therefore, it whether switch application or linearly answers With VDMOS is ideal power device.The sexual valence of VDMOS is relatively high, wherein possesses the VDMOS of U-shaped channel (Trench) Structure is that this field designer is widely used, and has been widely used in various fields, including electric machine speed regulation, inverter, power supply, Electronic switch, sound equipment, car electrics etc..Trench VDMOS has a special device architecture, such as using conductive structure by source Pole (Source) and body area be shorted, body area is carved without exposure mask injection, returning without exposure mask for grid polycrystalline silicon (Gate poly) (Etchback) techniques, to improve device performance or reduce cost of manufacture such as.

In chip manufacturing proces, manufacturer usually requires each electrical parameter of monitoring device, thus to judge technique mistake It is whether normal in journey.The grid resistance of device is a wherein very important parameter, is had to many characteristics of device critically important Influence.Therefore, the measurement of grid resistance is extremely important.But the setting of above-mentioned technique is so that device in the fabrication process, lacks Effective test section carries out parameter measurement and extraction to the structure to non-boundary, will lead to the success rate reduction and cost of research and development Rising.

Therefore it needs to design a kind of effective test structure in the semiconductor structure, joins to technological parameter and device Several extractions.

Utility model content

In view of the above problems, the purpose of this utility model is to provide a kind of semiconductor structure and test macro, semiconductors Structure includes semiconductor devices and test island, includes the polysilicon with closed loop boundary in test island, convenient for semiconductor device The key parameters such as the grid resistance of part carry out more accurate characterization.

One side according to the present utility model provides a kind of semiconductor structure, is used to form at least one semiconductor device Part and at least one test island, the semiconductor structure includes: substrate；Multiple grooves in the substrate；Dielectric layer, shape At in the exposed surface of each groove；And polysilicon, it is filled in each trench interiors, wherein the multiple ditch Slot includes at least one first groove and at least one second groove, is filled in the polysilicon inside the second groove and forms institute The grid of semiconductor devices is stated, each first groove has closed loop side wall, the polysilicon shape in the first groove At the test island being isolated with closed loop boundary and with the substrate, each test island is respectively provided at least two tests Node.

Preferably, the semiconductor structure has non-active area and effective coverage, at least one described semiconductor devices Positioned at the effective coverage, at least one described test island is located at the non-active area.

Preferably, the non-active area is corresponding with the scribing line position of the semiconductor structure.

Preferably, the semiconductor structure further include: doped layer is formed in the first surface of the substrate.

The doped layer being preferably located in the effective coverage forms each function of the corresponding semiconductor devices Energy area, the dielectric layer in the effective coverage form the gate dielectric layer of the corresponding semiconductor devices.

Preferably, further includes: dielectric layer is located on the polysilicon.

Preferably, further includes: through the dielectric layer and extend to multiple conductive structures in the polysilicon, Mei Gesuo It states conductive structure to be electrically connected with the corresponding test island, to draw the test of the electrical parameter for detecting the test island Node.

Preferably, each test island has the first test section, second under the restriction of the corresponding first groove Test section and the bonding pad for being connected to first test section with second test section, the first test island and described the At least one described test node is respectively provided in two test islands, the bonding pad is in rectangle or snakelike.

Preferably, further includes: the pad on the dielectric layer, each pad described are led with corresponding respectively Electric structure is adjacent, so that the test node on the corresponding test island is connected to test circuit.

Another aspect according to the present utility model provides a kind of test macro of semiconductor structure, comprising: as described above Semiconductor structure；And test circuit, it is electrically connected with the test island, the test circuit is by detecting the test island Electrical parameter obtains the electrical parameter of the semiconductor devices.

Semiconductor structure provided by the utility model and test macro, semiconductor structure include test island and semiconductor device Part forms test island in the non-active area of wafer while forming semiconductor devices, in test island, grid polycrystalline silicon (Gate poly) is formed in groove, and is surrounded by dielectric layer, so that grid has specific boundary, so as to survey Measure the parameters such as the grid resistance of MOS transistor.In the prior art, Trench VDMOS has special device architecture, such as Techniques such as (Etchback) are carved in returning without exposure mask for polysilicon, to improve device performance or reduce cost of manufacture.However, above-mentioned technique Setting so that device in the fabrication process, lacks the test island with clear boundary extracting and monitor procedure parameter, will The success rate of research and development is caused to reduce the rising with cost.The test island of the utility model embodiment can provide effective test structure Procedure parameter is extracted and monitored to the structure to non-boundary, to improve the yield and reliability of product.

Further, semiconductor structure provided by the utility model can be compatible with most of processing procedures, have universality.

Further, semiconductor structure provided by the utility model does not need to increase additional mask when forming test island, Effective test island can be provided in the case where not increasing cost and process complexity.

Further, the test island in semiconductor structure provided by the utility model prevents take up the effective area on wafer, Therefore additional cost is not increased.

Further, it can use bonding pad between the test island in semiconductor structure provided by the utility model mutually to interconnect It connects, may include multiple test nodes in each test island, test a variety of different lengths with two test islands so as to reach Polysilicon grid resistance purpose.

Detailed description of the invention

By referring to the drawings to the description of the utility model embodiment, above-mentioned and other mesh of the utility model , feature and advantage will be apparent from, in the accompanying drawings:

Fig. 1 shows the perspective view according to semiconductor structure provided by the embodiment of the utility model.

Fig. 2 shows the top views according to semiconductor structure provided by the embodiment of the utility model.

Fig. 3 shows the top view according to the test island in semiconductor structure provided by the embodiment of the utility model.

The manufacturing method that Fig. 4 a to 4j shows the test island in the semiconductor structure according to the utility model embodiment is each The sectional view in a stage.

Specific embodiment

The utility model is described below based on embodiment, but the utility model is not restricted to these implementations Example.It is detailed to describe some specific detail sections below in the datail description of the utility model embodiment, to this field The utility model can also be understood completely in the description of part without these details for technical staff.It is practical in order to avoid obscuring this Novel essence, well known process, process do not describe in detail.

In various figures, identical element, which is adopted, will be referred to by like reference numbers expression.For the sake of clarity, in attached drawing Various pieces are not necessarily to scale.In addition, certain well known parts may be not shown in figure.Flow chart, frame in attached drawing Figure illustrates the system of the embodiments of the present invention, possible System Framework, the function and operation of device, the box of attached drawing with And box sequence is used only to the process and step of better illustrated embodiment, without should be in this, as to utility model itself Limitation.

Hereinafter reference will be made to the drawings is more fully described the utility model.In various figures, identical element is using similar Appended drawing reference indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown Certain well known parts.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.

It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another Layer, another region " following " or " lower section ".

If, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario The form of presentation of face " or " A on B and therewith abut ".In this application, " A is in B " indicates that A is located in B, and And A and B is abutted directly against, rather than A is located in the doped region formed in B.

In this application, term " semiconductor structure " refers to entire half formed in each step of manufacturing semiconductor devices The general designation of conductor structure, including all layers formed or region.Hereinafter, unless otherwise indicated, " semiconductor structure " It refers to including the intermediate structure for testing island and semiconductor devices.

Many specific details of the utility model, such as the structure of device, material, size, place are described hereinafter Science and engineering skill and technology, to be more clearly understood that the utility model.But just as the skilled person will understand, The utility model can not be realized according to these specific details.

Fig. 1 shows the perspective view of the semiconductor structure according to the utility model embodiment.

As shown in Figure 1, semiconductor structure provided by the embodiment of the utility model includes test island and semiconductor devices, test Island and semiconductor devices are formed simultaneously on wafer.

Testing island includes the first semiconductor substrate 101, the first doped region 102, dielectric layer 103 (see Fig. 4 j), pad 104 (see Fig. 4 j), the first conductive structure 105, first medium layer 107 and polysilicon 106.First doped region 102, first medium layer 107 and polysilicon 106 be respectively positioned in the first semiconductor substrate 101, the first doped region 102 be the first semiconductor substrate 101 pass through It is obtained after ion implanting, first medium layer 107 and polysilicon 106 are formed in the groove of the first semiconductor substrate 101.First is situated between Polysilicon 106 is isolated test island between the first semiconductor substrate and polysilicon 106, as separation layer by matter layer 107, because This polysilicon has specific boundary, so that the resistance for the polysilicon being located in groove can be measured accurately.In this embodiment, Polysilicon is, for example, the polysilicon of P-type ion doping, is looked up in the side perpendicular to the first semiconductor substrate 101, groove example For example dumb-bell shape, so that polysilicon is also in dumb-bell shape.Polysilicon is connected at least two first conductive structures 105, to connect To test circuit, the characterization to polysilicon resistance is realized.

Semiconductor devices includes the second semiconductor substrate 201, the second doped region 202, second dielectric layer 207, dielectric layer (not shown), pad (not shown), the second conductive structure 205, source region 210 and grid 206.Second semiconductor Substrate 201 and the second doped region 202 are adjacent, and source region 210 is located in the second doped region 202, and 202 surface of the second doped region is covered with Second dielectric layer 207 includes grid 206 on second dielectric layer, and grid 206 is located between two source regions 210, source region 210 It is connected with extraction electrode, in this embodiment, extraction electrode is, for example, the second conductive structure 205, is also covered on 206 surface of grid There is dielectric layer, short circuit occurs between source electrode 210 and grid 206 for preventing.

However, the utility model is not limited to this, semiconductor devices can be any including polycrystalline in the prior art The semiconductor devices of silicon gate (Poly Gate), test island and semiconductor devices in the utility model are formed simultaneously, and test island In the non-active area of wafer, semiconductor devices is located in the effective coverage of wafer, and test island is for testing semiconductor device The key parameters such as the grid resistance in part.

Fig. 2 shows the top views according to semiconductor structure provided by the embodiment of the utility model.

As shown in Fig. 2, test island 100 is located in the non-active area of wafer 300, semiconductor devices 200 is located at wafer 300 Effective coverage in.

Fig. 3 a and 3b respectively illustrate bowing according to the test island in semiconductor structure provided by the embodiment of the utility model View.

As shown in Figure 3a, in this embodiment, first medium layer 107 (referring to Fig. 1) and polysilicon 106 are formed in the first half In the groove of conductor substrate, first medium layer 107 between the first semiconductor substrate and polysilicon 106, by polysilicon 106 every Test island is separated out, therefore polysilicon 106 has specific boundary, so that the resistance for the polysilicon 106 being located in groove can be quasi- It really measures, and then obtains the grid resistance of semiconductor devices.In this embodiment, polysilicon 106 is, for example, the polysilicon adulterated, Groove is, for example, dumb-bell shape, so that polysilicon 106 is also in dumb-bell shape.Polysilicon 106 have test node 112, and be connected with to Few two the first conductive structures realize the characterization to polysilicon resistance to be connected to test circuit.

As shown in Figure 3b, each test island under the restriction of corresponding first groove there is the first test section 150, second to survey Examination area 160 and the bonding pad 140 that is connected to first test section with second test section, the first test section 150 and the At least one test node is respectively provided in two test sections 160, bonding pad 140 is in rectangle or snakelike.In this embodiment, it connects Area 140 is serpentine-like, the first test section 150 and be respectively provided with four test nodes 112 in the second test section 160, test circuit When being connected to different test nodes 112, the resistance of the polysilicon of different length can be tested, so as in Gu Yi test island Test multiple resistance.

The manufacturing method that Fig. 4 a to 4j shows the test island in the semiconductor structure according to the utility model embodiment is each The sectional view in a stage, the sectional view are intercepted along AA line in Fig. 1, and the slice location of sectional view passes through first medium layer 107 With the first conductive structure 105.The sectional view in manufacturing method each stage on test island 100 is illustrated only in figure, it should be understood that survey What examination island 100 and semiconductor devices 200 were simultaneously formed, test the constituent on island 100 and the composition of semiconductor devices 200 Ingredient is corresponding, but the shape of the two, size, position are had any different, the grid that test island 100 is used to test in semiconductor devices 200 The parameters such as resistance.

The utility model starts from providing a kind of first semiconductor substrate 101, as shown in fig. 4 a.

First semiconductor substrate 101 is located at the non-active area of wafer 300.First semiconductor substrate 101 is, for example, p-type Or semiconductor layer or the region of N-type, the dopant of respective type can be adulterated in semiconductor layer and region, for example, p-type is adulterated Agent includes boron, and N type dopant includes phosphorus or arsenic or antimony.In this embodiment, the first semiconductor substrate 101 is heavily doped N-type lining Bottom, dopant are arsenic, and specific doping concentration is the prior art, can be selected according to actual needs.

The second semiconductor substrate 201 is provided simultaneously, and the second semiconductor substrate 201 is located at the effective coverage of wafer 300.The Two semiconductor substrates 201 are identical as the material of the first semiconductor substrate 101.

Further, first groove 110 is formed in the first semiconductor substrate 101, as shown in Figure 4 b.

It is looked up in the side perpendicular to the first semiconductor substrate 101, the cross sectional shape of first groove 110 is closed shape Shape, shape is interior to have certain space.In this embodiment, the shape of first groove 110 is dumb-bell shape.As described below, will Ion implanting can be carried out to the first semiconductor substrate 101, to form the first doped region 102, first groove 110 is located at the first doping In area 102, the segment space inside first groove 110 will be used to form the first conductive structure 105.Form first groove 110 Method includes photoetching or anisotropic engraving method, for example, by using dry etching, such as ion beam milling etching, plasma etching, anti- Answer ion(ic) etching, laser ablation.For example, being stopped by control etching period so that being etched in inside the first semiconductor substrate 101 Only.

Groove is formed in the second semiconductor substrate 201 simultaneously, is used to form the gate dielectric layer and grid of semiconductor devices Pole.

Further, first medium layer 107 is formed in semicon-ductor structure surface, as illustrated in fig. 4 c.

First medium layer 107 is located at upper surface and the exposure outer surface of first groove 110 of semiconductor structure, such as Using thermal oxidation method, first medium layer 107 is formed, first medium layer 107 is, for example, silica.As described below, will be located at Polysilicon 106 is formed in first medium layer 107 in first groove 110, first medium layer 107 is located at the first semiconductor substrate Between 101 and polysilicon 106, the two is isolated as separation layer, therefore polysilicon has specific boundary, to be located at ditch The resistance of polysilicon in slot can be measured accurately.

Second dielectric layer 207, second dielectric layer 207 and first medium are formed on the second semiconductor substrate 201 simultaneously Formation, material are identical while layer 107, gate dielectric layer of the second dielectric layer 207 as semiconductor devices.

Further, polysilicon 106 is formed in first groove 110, as shown in figure 4d.

Polysilicon 106 is formed in inside first groove 110, and is sufficient filling with first groove 110, for example, by using atomic layer deposition Product (Atomic Layer Deposition, ALD), physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) Or chemical vapor deposition (Chemical Vapor Deposition, CVD), crystal silicon 106 is formed, polysilicon 106 is, for example, p-type The polysilicon of ion doping.

Form second grid 206 on second dielectric layer simultaneously, second grid 206 and polysilicon 106 be formed simultaneously, Material is identical.

Further, planarization process is carried out to the polysilicon 106 for the doping for being located at semiconductor surface, so that first groove 106 surface of polysilicon of doping in 110 and the surface of substrate 101 maintain an equal level, and retain the polycrystalline of the doping inside first groove 110 Silicon 106, as shown in fig 4e.

In the embodiment, looked up in the side perpendicular to the first semiconductor substrate 101, the cross sectional shape of polysilicon 106 For closed dumb-bell shape.Polysilicon 106 is surrounded by the first medium layer 107 of surrounding, therefore has specific boundary.Using each 106 surface of polysilicon of the engraving method etching doping of anisotropy, for example, by using dry etching, such as ion beam milling etching, plasma Etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in 106 table of polysilicon of doping Face nearby stops.Preferably, after dry etching, using chemically mechanical polishing (Chemical Mechanical Polishing, CMP) make semiconductor surface smooth.

Further, ion implanting is carried out in the first semiconductor substrate 101, the first doped region 102 is formed, such as Fig. 4 f institute Show.

During forming the first doped region 102 using the method for ion implanting, mask can not be used using mask or. For example, by using mask carry out ion implanting, designing mask plate shape as needed, then at an oblique angle via the mask plate Ion implanting is carried out, in this embodiment, N ion implanting is controlled into the first semiconductor substrate of N-type 101, to form doping The first doped region of N-type 102.However, the utility model is without being limited thereto, the ion of multiple different-energy and dosage can also be used Injection technology is injected into appropriate depth and forms the first doped region 102.Preferably, after carrying out ion implanting, using annealing, For example, by using quick thermal annealing process, annealing temperature is, for example, 1000 to 1100 DEG C, and annealing time is, for example, 1 to 60 second.

Ion implanting is carried out in the second semiconductor substrate 201 simultaneously, forms the second doped region 202, the second doped region is made For the functional areas of semiconductor devices.Second doped region 202 is formed simultaneously with the first doped region 102, material is identical.

Further, dielectric layer (Inter-Layer-Dielectric, ILD) 103 is formed in semicon-ductor structure surface, As shown in figure 4g.For example, by using atomic layer deposition, physical vapour deposition (PVD) or chemical vapor deposition form dielectric layer 103, dielectric layer 103 be, for example, silicon dioxide layer or boron-phosphorosilicate glass.Dielectric layer (not shown) is formed on 207 surface of grid simultaneously, is used for It prevents that short circuit occurs between source electrode 210 and grid 207.

Further, at least two contact holes 111 are formed in semiconductor structure, as shown in figure 4h.

Contact hole 111 runs through dielectric layer 103 from 106 internal stretch of polysilicon to semicon-ductor structure surface.Form contact The method in hole 111 includes photoetching or anisotropic engraving method, for example, by using dry etching, such as ion beam milling etching, plasma Etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in inside the first doped region 102 Stop.Contact hole is formed in the dielectric layer on 207 surface of grid simultaneously, is used to form the second conductive structure 205.

Further, the first conductive structure 105 is formed in contact hole 111, as shown in figure 4i.

First conductive structure 105 runs through dielectric layer 103 from 106 internal stretch of polysilicon to semicon-ductor structure surface.It surveys Examination node is located at the head and the tail both ends on test island and does not contact with first groove 110.First conductive structure 105 is, for example, tungsten plug.Shape Method at the first conductive structure 105 is, for example, atomic layer deposition, physical vapour deposition (PVD) or chemical vapor deposition.Simultaneously in grid The second conductive structure 205 is formed in contact hole in the dielectric layer on 207 surfaces, forms the method and shape of the second conductive structure 205 Method at the first conductive structure 105 is identical.

Further, pad 104 is formed in semicon-ductor structure surface, as shown in figure 4j.

Pad 104 and the first conductive structure 105 close to, for example, by using atomic layer deposition, physical vapour deposition (PVD) or chemical gas It mutually deposits, forms pad 104, pad 104 is, for example, tungsten or aluminium.The shape of pad, size, thickness can be selected as needed It selects.

In this embodiment, the test macro of semiconductor structure includes the semiconductor structure and test circuit.It partly leads at this It include the first medium layer 107 positioned at first groove surface and filling in the test island 100 of body structure, in first groove 110 The polysilicon 106 of first groove 110, first medium layer 107 between the first semiconductor substrate 101 and polysilicon 106 so that Polysilicon 106 has specific boundary, and ultimately forms the test island with test node.Test island is passed through into conduction Structure and test node are electrically connected to test circuit, and test circuit obtains semiconductor devices by the electrical parameter on detection test island Electrical parameter.

It should be noted that herein, relational terms such as first and second and the like are used merely to a reality Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to Non-exclusive inclusion, so that the process, article or the equipment that include a series of elements not only include those elements, but also Further include other elements that are not explicitly listed, or further includes for this process, article or the intrinsic element of equipment. In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including the element Process, there is also other identical elements in article or equipment.

It is as described above according to the embodiments of the present invention, these embodiments details all there is no detailed descriptionthe, Also not limiting the utility model is only the specific embodiment.Obviously, as described above, many modification and change can be made Change.These embodiments are chosen and specifically described to this specification, is in order to preferably explain the principles of the present invention and actually to answer With so that skilled artisan be enable to utilize the utility model and repairing on the basis of the utility model well Change use.The utility model is limited only by the claims and their full scope and equivalents.

Claims (10)

1. a kind of semiconductor structure is used to form at least one semiconductor devices and at least one test island, which is characterized in that institute Stating semiconductor structure includes:

Substrate；

Multiple grooves in the substrate；

Dielectric layer is formed in the exposed surface of each groove；And

Polysilicon is filled in each trench interiors,

Wherein, the multiple groove includes at least one first groove and at least one second groove, is filled in second ditch Polysilicon inside slot forms the grid of the semiconductor devices, and each first groove has closed loop side wall, is located at described Polysilicon in first groove forms the test island for having closed loop boundary and being isolated with the substrate, each test island It is respectively provided at least two test nodes.

2. semiconductor structure according to claim 1, which is characterized in that the semiconductor structure have non-active area and Effective coverage, at least one described semiconductor devices are located at the effective coverage, at least one described test island is located at described non- Effective coverage.

3. semiconductor structure according to claim 2, which is characterized in that the non-active area and the semiconductor structure Scribing line position it is corresponding.

4. semiconductor structure according to claim 2, which is characterized in that the semiconductor structure further include:

Doped layer is formed in the first surface of the substrate.

5. semiconductor structure according to claim 4, which is characterized in that

The doped layer in the effective coverage forms each functional areas of the corresponding semiconductor devices,

The dielectric layer in the effective coverage forms the gate dielectric layer of the corresponding semiconductor devices.

6. semiconductor structure according to claim 1, which is characterized in that further include: dielectric layer, be located at the polysilicon it On.

7. semiconductor structure according to claim 6, which is characterized in that further include:

Through the dielectric layer and extend to multiple conductive structures in the polysilicon, each conductive structure with it is corresponding The test island electrical connection, to draw the test node of the electrical parameter for detecting the test island.

8. semiconductor structure according to claim 7, which is characterized in that each test island is corresponding described first There is the first test section, the second test section under the restriction of groove and be connected to first test section with second test section Bonding pad,

It is respectively provided at least one described test node in the first test island and second test island, the bonding pad is in Rectangle is snakelike.

9. semiconductor structure according to claim 7, which is characterized in that further include: the weldering on the dielectric layer Disk, each pad is adjacent with the corresponding conductive structure respectively, thus by the test on the corresponding test island Node is connected to test circuit.

10. a kind of test macro of semiconductor structure, comprising:

Semiconductor structure as described in any one of claim 1 to 9；And

Circuit is tested, is electrically connected with the test island, the test circuit is obtained by detecting the electrical parameter on the test island The electrical parameter of the semiconductor devices.