KR100588733B1 - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention is to provide a semiconductor device and a method of manufacturing the same that can increase the operating speed of the device by preventing the increase of the parasitic resistance by increasing the length of the gate insulating film of the power MOS device, for this purpose the semiconductor A drain region formed at the bottom of the substrate, a drift region formed on the drain region, a plurality of base regions formed on the drift region, a source region formed in the base region, and a predetermined portion on the semiconductor substrate between the base region A semiconductor device including a gate insulating film divided into intervals and a conductive layer formed on the gate insulating film is provided.

DMOS, gate insulating film, length, parasitic resistance, capacitance.

Description

Semiconductor device and its manufacturing method {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a cross-sectional view showing the structure of a double diffused metal oxide semiconductor (DMOS) device according to the prior art.

FIG. 2 is an SEM diagram of the DMOS device according to FIG. 1. FIG.

3 is a cross-sectional view showing a DMOS device according to a preferred embodiment of the present invention.

4 is an SEM diagram of the DMOS device of FIG. 3;

5 through 10 are cross-sectional views illustrating a method of manufacturing the DMOS device illustrated in FIG. 3.

<Explanation of symbols for main parts of drawing>

110: drain region 111: drift region

112 gate insulating film 113 conductive layer

114: first photoresist pattern 115: first etching process

116: via hole 117: second photoresist pattern

118: second etching process 119: gate electrode

120 impurity implantation process 121 base region

122: source region 123: insulating film

124: spacer 125: gate structure

126: interlayer insulating film 127: contact plug

128: wiring layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a power diffused metal oxide semiconductor (DMOS) device and a method of manufacturing the same.

Power MOS devices, such as Power Oxide Semiconductor Field Effect Transistors (MOSFETs), are unipolar devices with MOS structures. This results in faster switching speed, higher thermal stability, and higher power gain at high input impedance compared to bipolar transistors. In addition, it is easy to control and has many features such as ease of use, and is being applied to a wide range of fields such as home appliances, electronic equipment, general industrial equipment, and the like.

Chip structures of power MOSFETs include a lateral structure (LMOS) and a trench structure, and trench structures include V Grooved MOS (VMOS), UMOS, and DMOS.

Among them, the DMOS is formed through a double diffusion process, the drain is disposed on the bottom surface of the semiconductor substrate, the source is disposed on the top surface. Accordingly, the current flows in the longitudinal direction through the vertical channel.

Hereinafter, a DMOS device according to the related art will be described with reference to FIGS. 1 and 2.

As shown in FIG. 1, an N− low concentration drift region 11 is formed on an N + high concentration drain region 10 formed in a semiconductor substrate (not shown). The P + high concentration base region 12 is formed in the upper predetermined region of the drift region 11, and the N + high concentration source region 13 is formed in the base region 12. Further, on the substrate of the drift region 11, a gate electrode 16 made of a gate insulating film 14 and a conductive layer 15 is formed.

However, the DMOS device according to the related art described above has a length of the gate electrode 16 as compared to a general MOSFET in order to prevent a phenomenon in which the gate electrode 16 is formed horizontally before the channel is vertically formed due to the short length of the gate electrode 16. Is formed long. As a result, the length of the gate insulating layer 14 is also increased to increase the parasitic resistance generated in the gate insulating layer 14. As a result, the amount of charge accumulated in the gate insulating film 14 increases, causing a problem of reducing the operation speed of the device.

Therefore, the present invention has been proposed to solve the above problems of the prior art, a semiconductor that can increase the operation speed of the device by preventing the increase of the parasitic resistance by increasing the length of the gate insulating film of the power MOS device The object is to provide an element.

Another object of the present invention is to provide a method of manufacturing the semiconductor device.

According to an aspect of the present invention, there is provided a drain region formed at a bottom of a semiconductor substrate, a drift region formed on the drain region, a plurality of base regions formed on the drift region, and the base. A semiconductor device includes a source insulating film formed in a region, a gate insulating film divided into portions separated by a predetermined interval between the base regions, and a conductive layer formed on the gate insulating film.

In one aspect of the invention, the conductive layer is characterized in that divided into the same pattern as the gate insulating film.

In one aspect of the present invention, a wiring layer for interconnecting the bisected conductive layers is further included.

In one aspect of the invention, it characterized in that it further comprises an insulating film interposed between the conductive layer divided into two.

According to another aspect of the present invention, there is provided a method of forming a drain region on a bottom of a semiconductor substrate, forming a drift region on the drain region, and forming a gate insulating film on the drift region. Forming a conductive layer, etching the gate insulating film and the conductive layer to form a via hole so as to expose a portion of the drift region, and etching the gate insulating film and the conductive layer into two portions by the via hole Forming a gate electrode, forming a base region in the drift region exposed to both sides of the divided gate electrode, and forming a source region in the base region. To provide.

According to another aspect of the invention, after the step of forming the source region, forming a first insulating film so as to fill the via hole, and forming a second insulating film on the entire structure including the first insulating film and And etching the second insulating film to form contact holes exposing the bisected gate electrodes, and forming contact plugs interconnected to fill the contact holes.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 and 4 are cross-sectional views of a DMOS device for explaining a semiconductor device according to a preferred embodiment of the present invention. Here, the N-channel DMOS device according to the present embodiment is shown for convenience of description.

First, as shown in FIG. 3, an N− low concentration drift region 111 is formed on an N + high concentration drain region 110 formed in a semiconductor substrate (not shown). The P + high concentration base region 121 is formed in the semiconductor substrate in the upper predetermined region of the drift region 111, and the N + high concentration source region 122 is formed in the base region 121. On the semiconductor substrate of the drift region 121, a plurality of gate structures 125 including the gate electrode 119 divided through the insulating layer 123 is formed.

That is, according to the exemplary embodiment of the present invention, the via hole 116 is formed in one gate electrode 119 to divide the gate electrode 119 into two parts. Subsequently, the gate electrode 119 divided into two wiring layers 128 is connected to each other so as to function as one gate electrode 119, thereby lengthening the length of the gate insulating layer 112 constituting one gate electrode 119. Can be reduced.

As a result, parasitic resistance that increases in proportion to the length of the gate insulating layer 112 can be reduced, and the capacitance of the gate insulating layer 112 can be reduced. This, in turn, makes it possible to improve the operating speed of the power MOS device.

Hereinafter, with reference to Table 1 by comparing the parasitic resistance and capacitance of the power DMOS device formed according to the prior art and the power DMOS device formed according to a preferred embodiment of the present invention, the advantages according to the preferred embodiment of the present invention Let's make it more clear.

In Table 1 below, the parasitic resistance is a resistance value calculated by dividing the measured drain voltage by the drain current by measuring the drain voltage under the condition of drain current = 7A and gate voltage = 4.5V. The capacitance is a value measured by the amount of charge accumulated in the gate insulating film when a ground terminal is connected to the gate electrode and a voltage of 30 V is applied to the drain. In this case, a separate capacitance measurement device for measuring the amount of charge is used.

TABLE 1

Prior art Embodiment of the present invention Parasitic Resistance (mOhm / Square) ≒ 8.5 ≒ 6.0 Capacitance (pF) ≒ 3000 ≒ 2000

First, referring to Table 1, the parasitic resistance of the gate insulating film is about 8.5 mOhm / SQ when the thickness of the gate insulating film is 400 μm and the length of the gate insulating film is 3 μm, as in the aforementioned conventional technology. On the other hand, the parasitic resistance of the gate insulating film is about 6.0mOhm / SQ when the thickness of the gate insulating film is 400 Å and the length of the gate insulating film is 1.8 μm, as in the above-mentioned embodiment of the present invention.

That is, according to the preferred embodiment of the present invention, by dividing the gate electrode to reduce the length of the gate insulating film by 1.2 μm, the parasitic resistance of the gate insulating film is reduced by 2.5 mOhm / SQ.

In addition, referring to Table 1, when the thickness of the gate insulating film is 400 Å and the length of the gate insulating film is 3 μm, the capacitance of the gate insulating film is 3000 pF. On the other hand, as in the above-described embodiment of the present invention, when the thickness of the gate insulating film is 400 μm and the length of the gate insulating film is 1.8 μm, the capacitance of the gate insulating film is 2000 pF.

That is, according to the preferred embodiment of the present invention, the gate electrode is divided into two parts to reduce the length of the gate insulating film by 1.2 µm, thereby reducing the capacitance of the gate insulating film by 1000 pF.

As a result, according to a preferred embodiment of the present invention, by reducing the length of the gate insulating film to reduce the parasitic resistance and capacitance, it is possible to improve the operating speed of the device.

Hereinafter, a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention shown in FIGS. 3 and 4 will be described with reference to FIGS. 5 to 10.

First, as shown in FIG. 5, a semiconductor substrate having an N + high concentration drain region 110 formed thereon and an N− low concentration drift region 111 formed by growing an epitaxial layer on the drain region 110. Not shown).

Subsequently, a device isolation film (not shown) is formed by performing a LOCOS (LOCal Oxidation of Silicon) process to perform a mask process and an etching process to planarize the device isolation film. In addition, the device isolation film may be formed by performing a shallow trench isolation (STI) process, which is advantageous for high integration.

Subsequently, the gate insulating film 112 is grown on the entire surface of the semiconductor substrate on which the drift region 111 is formed by performing an oxidation process, and then the conductive layer 113 for the gate electrode is deposited. In this case, the conductive layer 113 may be formed by depositing a doped or undoped polysilicon layer alone or by depositing a tungsten (W) or a tungsten silicide layer (WSi ₂ ) on top of the conductive layer 113.

Subsequently, as shown in FIG. 6, a mask process is performed to form a first photoresist pattern 114 on which a predetermined portion of the N-drift region 111 is exposed on the conductive layer 113.

Subsequently, the first etching process 115 using the first photoresist pattern 114 as a mask is performed to sequentially etch the conductive layer 113 and the gate insulating layer 112. Thus, a via hole 116 through which a portion of the drift region 111 is exposed is formed. In this case, the via hole 116 is preferably formed to have a width of 1.2 μm.

Accordingly, the length of the gate insulating layer 112 is reduced by the width (1.2 μm) in which the via hole 116 is formed. For example, the thickness of the gate insulating film 112 is 400 micrometers, and the length of the gate insulating film 112 is 1.8 micrometers with a short 1.2 micrometer.

Subsequently, as illustrated in FIG. 7, a strip process is performed to remove the first photoresist pattern 114.

Subsequently, a mask process is performed to form a second photoresist pattern 117 covering a portion of the conductive layer 113 including the via hole 116.

Next, a second etching process 118 using the second photoresist pattern 117 as a mask is performed to form the gate electrode 119. In this case, the gate electrode 119 has a structure divided into two by the via hole 116. The gate electrode 119 includes a gate insulating layer 112 and a conductive layer 113.

Subsequently, a channel ion implantation process is performed on the resultant in which the gate electrode 119 is formed, and a channel region (not shown) is formed vertically in the drift region 111 exposed to both sides of the second photoresist pattern 117.

Subsequently, an annealing process is performed to diffuse the ions implanted during the channel ion implantation process to the desired drain region 110 to form a channel region.

Subsequently, as shown in FIG. 8, an impurity implantation process 120 using the second photoresist pattern 117 as a mask is performed to uniformly set the drift region 111 exposed to both sides of the second photoresist pattern 117. P + high concentration base region 121 and N + high concentration source region 122 are formed in depth. At this time, the impurity implantation process 120 is performed twice. First, an impurity of P + is implanted to form a P + base region 121, and a second is implanted of an N + impurity to inject an N + source into the base region 121. Area 122 is formed.

Subsequently, as shown in FIG. 9, a strip process is performed to remove the second photoresist pattern 117 (see FIG. 8), thereby dividing the gate electrode 119 due to the formation of the via hole 116 (see FIG. 6). ) Are exposed respectively.

Subsequently, a high temperature low pressure dielectic (HLD) insulating layer 123 is deposited on the entire structure where the bi-divided gate electrode 119 is exposed.

Subsequently, as illustrated in FIG. 10, a chemical mechanical polishing (CMP) process is performed to fill the via hole 116 (see FIG. 6) with the HLD insulating layer 123. The gate electrode 119 bisected by the HLD insulating film 123 is electrically separated. Hereinafter, the entire structure of the gate electrode 119 which is divided into two by the HLD insulating layer 123 is collectively referred to as a gate structure 125.

Subsequently, an insulating film for a spacer (not shown) is deposited along the level of the upper portion of the entire structure on which the gate structure 125 is formed, and then a dry etching process is performed. Accordingly, spacers 124 are formed on both sidewalls of the gate structure 125.

Subsequently, after the interlayer insulating layer 126 is deposited on the resultant spacer 124, an etching process is performed to form a contact hole (not shown) to expose a portion of the conductive layer 113 of each gate electrode 119. do. In this case, the interlayer insulating layer 126 is formed of an oxide film-based material. For example, the interlayer insulating layer 126 may include an HDP (High Density Plasma) oxide film, a Boron Phosphorus Silicate Glass (BPSG) film, a Phosphorus Silicate Glass (PSG) film, a Plasma Enhanced Tetra Ethyle Ortho Silicate (PETOS) film, and a Plasma Enhanced Chemical Vapor (PECVD) film. A single layer film or a laminate of these layers is laminated using any one of a deposition film, a USG (Un-doped Silicate Glass) film, a FSG (Fluorinated Silicate Glass) film, a carbon doped oxide (CDO) film, and an organosilicate glass (OSG) film Form into a film.

Subsequently, a conductive material filling the contact hole is deposited to form a contact plug 127 to connect each gate electrode 127 with the upper wiring layer 128 to be formed through a subsequent process thereon.

Subsequently, a wiring material is deposited on the entire surface of the product on which the contact plug 127 is formed, and then a mask process and an etching process are performed to form a wiring layer 128 connected to each gate structure 125. Accordingly, two contact plugs 127 respectively formed on the divided gate electrode 119 are electrically connected through one wiring layer 128. Thus, the divided gate electrode 119 can function as one gate electrode 119.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, by providing a gate electrode divided into a predetermined interval by the via hole (via hole), through this to reduce the length of the gate insulating film by the spaced apart by the length of the gate insulating film Increasing parasitic resistance and capacitance can be reduced. This, in turn, makes it possible to improve the operating speed of the power MOS device.

Claims (6)

A drain region formed at the bottom of the semiconductor substrate; A drift region formed on the drain region; A plurality of base regions formed on the drift region; A source region formed in the base region; A gate insulating film divided into two parts to be spaced apart at regular intervals between the base areas; And A conductive layer formed on the gate insulating film; Semiconductor device comprising a. The method of claim 1, The conductive layer is divided into two parts in the same pattern as the gate insulating film. The method of claim 2, And a wiring layer for interconnecting the bisected conductive layers. The method of claim 2, The semiconductor device further comprises an insulating film interposed between the divided conductive layer. Forming a drain region at the bottom of the semiconductor substrate; Forming a drift region on the drain region; Forming a gate insulating film and a conductive layer on the drift region; Etching the gate insulating layer and the conductive layer to form a via hole to expose a portion of the drift region; Etching the gate insulating layer and the conductive layer to form a gate electrode divided by the via hole; Forming a base region in the drift region exposed to both sides of the bidivided gate electrode; And Forming a source region in the base region; Method of manufacturing a semiconductor device comprising a. The method of claim 5, After forming the source region, Forming a first insulating film to fill the via hole; Forming a second insulating film on the entire structure including the first insulating film; Etching the second insulating layer to form a contact hole exposing the bisected gate electrode; And Forming contact plugs interconnected to fill the contact holes; Method of manufacturing a semiconductor device further comprising.

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